3 # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4 # Licensed and distributed under the GPL
8 bool "EDAC (Error Detection And Correction) reporting"
10 depends on X86 || PPC || TILE
12 EDAC is designed to report errors in the core system.
13 These are low-level errors that are reported in the CPU or
14 supporting chipset or other subsystems:
15 memory errors, cache errors, PCI errors, thermal throttling, etc..
16 If unsure, select 'Y'.
18 If this code is reporting problems on your system, please
19 see the EDAC project web pages for more information at:
21 <http://bluesmoke.sourceforge.net/>
25 <http://buttersideup.com/edacwiki>
27 There is also a mailing list for the EDAC project, which can
28 be found via the sourceforge page.
32 comment "Reporting subsystems"
37 This turns on debugging information for the entire EDAC
38 sub-system. You can insert module with "debug_level=x", current
39 there're four debug levels (x=0,1,2,3 from low to high).
40 Usually you should select 'N'.
42 config EDAC_DECODE_MCE
43 tristate "Decode MCEs in human-readable form (only on AMD for now)"
44 depends on CPU_SUP_AMD && (X86_MCE_AMD || X86_XEN_MCE)
47 Enable this option if you want to decode Machine Check Exceptions
48 occurring on your machine in human-readable form.
50 You should definitely say Y here in case you want to decode MCEs
51 which occur really early upon boot, before the module infrastructure
55 tristate "Simple MCE injection interface over /sysfs"
56 depends on EDAC_DECODE_MCE
59 This is a simple interface to inject MCEs over /sysfs and test
60 the MCE decoding code in EDAC.
62 This is currently AMD-only.
65 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
67 Some systems are able to detect and correct errors in main
68 memory. EDAC can report statistics on memory error
69 detection and correction (EDAC - or commonly referred to ECC
70 errors). EDAC will also try to decode where these errors
71 occurred so that a particular failing memory module can be
72 replaced. If unsure, select 'Y'.
75 tristate "AMD64 (Opteron, Athlon64) K8, F10h"
76 depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
79 Support for error detection and correction of DRAM ECC errors on
80 the AMD64 families of memory controllers (K8 and F10h)
82 config EDAC_AMD64_ERROR_INJECTION
83 bool "Sysfs HW Error injection facilities"
86 Recent Opterons (Family 10h and later) provide for Memory Error
87 Injection into the ECC detection circuits. The amd64_edac module
88 allows the operator/user to inject Uncorrectable and Correctable
91 When enabled, in each of the respective memory controller directories
92 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
94 - inject_section (0..3, 16-byte section of 64-byte cacheline),
95 - inject_word (0..8, 16-bit word of 16-byte section),
96 - inject_ecc_vector (hex ecc vector: select bits of inject word)
98 In addition, there are two control files, inject_read and inject_write,
99 which trigger the DRAM ECC Read and Write respectively.
102 tristate "AMD 76x (760, 762, 768)"
103 depends on EDAC_MM_EDAC && PCI && X86_32
105 Support for error detection and correction on the AMD 76x
106 series of chipsets used with the Athlon processor.
109 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
110 depends on EDAC_MM_EDAC && PCI && X86_32
112 Support for error detection and correction on the Intel
113 E7205, E7500, E7501 and E7505 server chipsets.
116 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
117 depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
119 Support for error detection and correction on the Intel
120 E7520, E7525, E7320 server chipsets.
122 config EDAC_I82443BXGX
123 tristate "Intel 82443BX/GX (440BX/GX)"
124 depends on EDAC_MM_EDAC && PCI && X86_32
127 Support for error detection and correction on the Intel
128 82443BX/GX memory controllers (440BX/GX chipsets).
131 tristate "Intel 82875p (D82875P, E7210)"
132 depends on EDAC_MM_EDAC && PCI && X86_32
134 Support for error detection and correction on the Intel
135 DP82785P and E7210 server chipsets.
138 tristate "Intel 82975x (D82975x)"
139 depends on EDAC_MM_EDAC && PCI && X86
141 Support for error detection and correction on the Intel
142 DP82975x server chipsets.
145 tristate "Intel 3000/3010"
146 depends on EDAC_MM_EDAC && PCI && X86
148 Support for error detection and correction on the Intel
149 3000 and 3010 server chipsets.
152 tristate "Intel 3200"
153 depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
155 Support for error detection and correction on the Intel
156 3200 and 3210 server chipsets.
160 depends on EDAC_MM_EDAC && PCI && X86
162 Support for error detection and correction on the Intel
166 tristate "Intel 5400 (Seaburg) chipsets"
167 depends on EDAC_MM_EDAC && PCI && X86
169 Support for error detection and correction the Intel
170 i5400 MCH chipset (Seaburg).
173 tristate "Intel i7 Core (Nehalem) processors"
174 depends on EDAC_MM_EDAC && PCI && X86 && (X86_MCE_INTEL || X86_XEN_MCE)
176 Support for error detection and correction the Intel
177 i7 Core (Nehalem) Integrated Memory Controller that exists on
178 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
179 and Xeon 55xx processors.
182 tristate "Intel 82860"
183 depends on EDAC_MM_EDAC && PCI && X86_32
185 Support for error detection and correction on the Intel
189 tristate "Radisys 82600 embedded chipset"
190 depends on EDAC_MM_EDAC && PCI && X86_32
192 Support for error detection and correction on the Radisys
193 82600 embedded chipset.
196 tristate "Intel Greencreek/Blackford chipset"
197 depends on EDAC_MM_EDAC && X86 && PCI
199 Support for error detection and correction the Intel
200 Greekcreek/Blackford chipsets.
203 tristate "Intel San Clemente MCH"
204 depends on EDAC_MM_EDAC && X86 && PCI
206 Support for error detection and correction the Intel
210 tristate "Intel Clarksboro MCH"
211 depends on EDAC_MM_EDAC && X86 && PCI
213 Support for error detection and correction the Intel
214 Clarksboro MCH (Intel 7300 chipset).
217 tristate "Intel Sandy-Bridge Integrated MC"
218 depends on EDAC_MM_EDAC && PCI && X86_64 && (X86_MCE_INTEL || X86_XEN_MCE)
219 depends on PCI_MMCONFIG && EXPERIMENTAL
221 Support for error detection and correction the Intel
222 Sandy Bridge Integrated Memory Controller.
225 tristate "Freescale MPC83xx / MPC85xx"
226 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
228 Support for error detection and correction on the Freescale
229 MPC8349, MPC8560, MPC8540, MPC8548
232 tristate "Marvell MV64x60"
233 depends on EDAC_MM_EDAC && MV64X60
235 Support for error detection and correction on the Marvell
236 MV64360 and MV64460 chipsets.
239 tristate "PA Semi PWRficient"
240 depends on EDAC_MM_EDAC && PCI
241 depends on PPC_PASEMI
243 Support for error detection and correction on PA Semi
247 tristate "Cell Broadband Engine memory controller"
248 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
250 Support for error detection and correction on the
251 Cell Broadband Engine internal memory controller
252 on platform without a hypervisor
255 tristate "PPC4xx IBM DDR2 Memory Controller"
256 depends on EDAC_MM_EDAC && 4xx
258 This enables support for EDAC on the ECC memory used
259 with the IBM DDR2 memory controller found in various
260 PowerPC 4xx embedded processors such as the 405EX[r],
261 440SP, 440SPe, 460EX, 460GT and 460SX.
264 tristate "AMD8131 HyperTransport PCI-X Tunnel"
265 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
267 Support for error detection and correction on the
268 AMD8131 HyperTransport PCI-X Tunnel chip.
269 Note, add more Kconfig dependency if it's adopted
270 on some machine other than Maple.
273 tristate "AMD8111 HyperTransport I/O Hub"
274 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
276 Support for error detection and correction on the
277 AMD8111 HyperTransport I/O Hub chip.
278 Note, add more Kconfig dependency if it's adopted
279 on some machine other than Maple.
282 tristate "IBM CPC925 Memory Controller (PPC970FX)"
283 depends on EDAC_MM_EDAC && PPC64
285 Support for error detection and correction on the
286 IBM CPC925 Bridge and Memory Controller, which is
287 a companion chip to the PowerPC 970 family of
291 tristate "Tilera Memory Controller"
292 depends on EDAC_MM_EDAC && TILE
295 Support for error detection and correction on the
296 Tilera memory controller.