drivers/dma/ioat/hw.h

   1 /*
   2  * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59
  16  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called COPYING.
  20  */
  21 #ifndef _IOAT_HW_H_
  22 #define _IOAT_HW_H_
  23
  24 /* PCI Configuration Space Values */
  25 #define IOAT_PCI_VID            0x8086
  26 #define IOAT_MMIO_BAR           0
  27
  28 /* CB device ID's */
  29 #define IOAT_PCI_DID_5000       0x1A38
  30 #define IOAT_PCI_DID_CNB        0x360B
  31 #define IOAT_PCI_DID_SCNB       0x65FF
  32 #define IOAT_PCI_DID_SNB        0x402F
  33
  34 #define IOAT_PCI_RID            0x00
  35 #define IOAT_PCI_SVID           0x8086
  36 #define IOAT_PCI_SID            0x8086
  37 #define IOAT_VER_1_2            0x12    /* Version 1.2 */
  38 #define IOAT_VER_2_0            0x20    /* Version 2.0 */
  39 #define IOAT_VER_3_0            0x30    /* Version 3.0 */
  40 #define IOAT_VER_3_2            0x32    /* Version 3.2 */
  41
  42 #ifndef CONFIG_XEN
  43 int system_has_dca_enabled(struct pci_dev *pdev);
  44 #else
  45 static inline int system_has_dca_enabled(struct pci_dev *pdev) { return 0; }
  46 #endif
  47
  48 struct ioat_dma_descriptor {
  49         uint32_t        size;
  50         union {
  51                 uint32_t ctl;
  52                 struct {
  53                         unsigned int int_en:1;
  54                         unsigned int src_snoop_dis:1;
  55                         unsigned int dest_snoop_dis:1;
  56                         unsigned int compl_write:1;
  57                         unsigned int fence:1;
  58                         unsigned int null:1;
  59                         unsigned int src_brk:1;
  60                         unsigned int dest_brk:1;
  61                         unsigned int bundle:1;
  62                         unsigned int dest_dca:1;
  63                         unsigned int hint:1;
  64                         unsigned int rsvd2:13;
  65                         #define IOAT_OP_COPY 0x00
  66                         unsigned int op:8;
  67                 } ctl_f;
  68         };
  69         uint64_t        src_addr;
  70         uint64_t        dst_addr;
  71         uint64_t        next;
  72         uint64_t        rsv1;
  73         uint64_t        rsv2;
  74         /* store some driver data in an unused portion of the descriptor */
  75         union {
  76                 uint64_t        user1;
  77                 uint64_t        tx_cnt;
  78         };
  79         uint64_t        user2;
  80 };
  81
  82 struct ioat_fill_descriptor {
  83         uint32_t        size;
  84         union {
  85                 uint32_t ctl;
  86                 struct {
  87                         unsigned int int_en:1;
  88                         unsigned int rsvd:1;
  89                         unsigned int dest_snoop_dis:1;
  90                         unsigned int compl_write:1;
  91                         unsigned int fence:1;
  92                         unsigned int rsvd2:2;
  93                         unsigned int dest_brk:1;
  94                         unsigned int bundle:1;
  95                         unsigned int rsvd4:15;
  96                         #define IOAT_OP_FILL 0x01
  97                         unsigned int op:8;
  98                 } ctl_f;
  99         };
 100         uint64_t        src_data;
 101         uint64_t        dst_addr;
 102         uint64_t        next;
 103         uint64_t        rsv1;
 104         uint64_t        next_dst_addr;
 105         uint64_t        user1;
 106         uint64_t        user2;
 107 };
 108
 109 struct ioat_xor_descriptor {
 110         uint32_t        size;
 111         union {
 112                 uint32_t ctl;
 113                 struct {
 114                         unsigned int int_en:1;
 115                         unsigned int src_snoop_dis:1;
 116                         unsigned int dest_snoop_dis:1;
 117                         unsigned int compl_write:1;
 118                         unsigned int fence:1;
 119                         unsigned int src_cnt:3;
 120                         unsigned int bundle:1;
 121                         unsigned int dest_dca:1;
 122                         unsigned int hint:1;
 123                         unsigned int rsvd:13;
 124                         #define IOAT_OP_XOR 0x87
 125                         #define IOAT_OP_XOR_VAL 0x88
 126                         unsigned int op:8;
 127                 } ctl_f;
 128         };
 129         uint64_t        src_addr;
 130         uint64_t        dst_addr;
 131         uint64_t        next;
 132         uint64_t        src_addr2;
 133         uint64_t        src_addr3;
 134         uint64_t        src_addr4;
 135         uint64_t        src_addr5;
 136 };
 137
 138 struct ioat_xor_ext_descriptor {
 139         uint64_t        src_addr6;
 140         uint64_t        src_addr7;
 141         uint64_t        src_addr8;
 142         uint64_t        next;
 143         uint64_t        rsvd[4];
 144 };
 145
 146 struct ioat_pq_descriptor {
 147         uint32_t        size;
 148         union {
 149                 uint32_t ctl;
 150                 struct {
 151                         unsigned int int_en:1;
 152                         unsigned int src_snoop_dis:1;
 153                         unsigned int dest_snoop_dis:1;
 154                         unsigned int compl_write:1;
 155                         unsigned int fence:1;
 156                         unsigned int src_cnt:3;
 157                         unsigned int bundle:1;
 158                         unsigned int dest_dca:1;
 159                         unsigned int hint:1;
 160                         unsigned int p_disable:1;
 161                         unsigned int q_disable:1;
 162                         unsigned int rsvd:11;
 163                         #define IOAT_OP_PQ 0x89
 164                         #define IOAT_OP_PQ_VAL 0x8a
 165                         unsigned int op:8;
 166                 } ctl_f;
 167         };
 168         uint64_t        src_addr;
 169         uint64_t        p_addr;
 170         uint64_t        next;
 171         uint64_t        src_addr2;
 172         uint64_t        src_addr3;
 173         uint8_t         coef[8];
 174         uint64_t        q_addr;
 175 };
 176
 177 struct ioat_pq_ext_descriptor {
 178         uint64_t        src_addr4;
 179         uint64_t        src_addr5;
 180         uint64_t        src_addr6;
 181         uint64_t        next;
 182         uint64_t        src_addr7;
 183         uint64_t        src_addr8;
 184         uint64_t        rsvd[2];
 185 };
 186
 187 struct ioat_pq_update_descriptor {
 188         uint32_t        size;
 189         union {
 190                 uint32_t ctl;
 191                 struct {
 192                         unsigned int int_en:1;
 193                         unsigned int src_snoop_dis:1;
 194                         unsigned int dest_snoop_dis:1;
 195                         unsigned int compl_write:1;
 196                         unsigned int fence:1;
 197                         unsigned int src_cnt:3;
 198                         unsigned int bundle:1;
 199                         unsigned int dest_dca:1;
 200                         unsigned int hint:1;
 201                         unsigned int p_disable:1;
 202                         unsigned int q_disable:1;
 203                         unsigned int rsvd:3;
 204                         unsigned int coef:8;
 205                         #define IOAT_OP_PQ_UP 0x8b
 206                         unsigned int op:8;
 207                 } ctl_f;
 208         };
 209         uint64_t        src_addr;
 210         uint64_t        p_addr;
 211         uint64_t        next;
 212         uint64_t        src_addr2;
 213         uint64_t        p_src;
 214         uint64_t        q_src;
 215         uint64_t        q_addr;
 216 };
 217
 218 struct ioat_raw_descriptor {
 219         uint64_t        field[8];
 220 };
 221 #endif