2 * Low-Level PCI Support for PC -- Routing of Interrupts
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
7 #include <linux/types.h>
8 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/dmi.h>
14 #include <linux/smp.h>
15 #include <asm/io_apic.h>
16 #include <linux/irq.h>
17 #include <linux/acpi.h>
18 #include <asm/pci_x86.h>
20 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
21 #define PIRQ_VERSION 0x0100
23 static int broken_hp_bios_irq9;
24 static int acer_tm360_irqrouting;
26 static struct irq_routing_table *pirq_table;
28 static int pirq_enable_irq(struct pci_dev *dev);
31 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
32 * Avoid using: 13, 14 and 15 (FP error and IDE).
33 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
35 unsigned int pcibios_irq_mask = 0xfff8;
37 static int pirq_penalty[16] = {
38 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
39 0, 0, 0, 0, 1000, 100000, 100000, 100000
45 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
46 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq,
50 struct irq_router_handler {
52 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
55 int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq;
56 void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL;
59 * Check passed address for the PCI IRQ Routing Table signature
60 * and perform checksum verification.
63 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr)
65 struct irq_routing_table *rt;
69 rt = (struct irq_routing_table *) addr;
70 if (rt->signature != PIRQ_SIGNATURE ||
71 rt->version != PIRQ_VERSION ||
73 rt->size < sizeof(struct irq_routing_table))
76 for (i = 0; i < rt->size; i++)
79 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n",
89 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
92 static struct irq_routing_table * __init pirq_find_routing_table(void)
95 struct irq_routing_table *rt;
98 if (!is_initial_xendomain())
101 if (pirq_table_addr) {
102 rt = pirq_check_routing_table((u8 *) isa_bus_to_virt(pirq_table_addr));
105 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
107 for (addr = (u8 *) isa_bus_to_virt(0xf0000);
108 addr < (u8 *) isa_bus_to_virt(0x100000); addr += 16) {
109 rt = pirq_check_routing_table(addr);
117 * If we have a IRQ routing table, use it to search for peer host
118 * bridges. It's a gross hack, but since there are no other known
119 * ways how to get a list of buses, we have to go this way.
122 static void __init pirq_peer_trick(void)
124 struct irq_routing_table *rt = pirq_table;
129 memset(busmap, 0, sizeof(busmap));
130 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
135 DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
136 for (j = 0; j < 4; j++)
137 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
143 for (i = 1; i < 256; i++) {
145 if (!busmap[i] || pci_find_bus(0, i))
147 node = get_mp_bus_to_node(i);
148 if (pci_scan_bus_on_node(i, &pci_root_ops, node))
149 printk(KERN_INFO "PCI: Discovered primary peer "
150 "bus %02x [IRQ]\n", i);
152 pcibios_last_bus = -1;
156 * Code for querying and setting of IRQ routes on various interrupt routers.
159 void eisa_set_level_irq(unsigned int irq)
161 unsigned char mask = 1 << (irq & 7);
162 unsigned int port = 0x4d0 + (irq >> 3);
164 static u16 eisa_irq_mask;
166 if (irq >= 16 || (1 << irq) & eisa_irq_mask)
169 eisa_irq_mask |= (1 << irq);
170 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq);
173 DBG(KERN_DEBUG " -> edge");
174 outb(val | mask, port);
179 * Common IRQ routing practice: nibbles in config space,
180 * offset by some magic constant.
182 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
185 unsigned reg = offset + (nr >> 1);
187 pci_read_config_byte(router, reg, &x);
188 return (nr & 1) ? (x >> 4) : (x & 0xf);
191 static void write_config_nybble(struct pci_dev *router, unsigned offset,
192 unsigned nr, unsigned int val)
195 unsigned reg = offset + (nr >> 1);
197 pci_read_config_byte(router, reg, &x);
198 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
199 pci_write_config_byte(router, reg, x);
203 * ALI pirq entries are damn ugly, and completely undocumented.
204 * This has been figured out from pirq tables, and it's not a pretty
207 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
209 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
211 WARN_ON_ONCE(pirq > 16);
212 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
215 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
217 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
218 unsigned int val = irqmap[irq];
220 WARN_ON_ONCE(pirq > 16);
222 write_config_nybble(router, 0x48, pirq-1, val);
229 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
230 * just a pointer to the config space.
232 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
236 pci_read_config_byte(router, pirq, &x);
237 return (x < 16) ? x : 0;
240 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
242 pci_write_config_byte(router, pirq, irq);
247 * The VIA pirq rules are nibble-based, like ALI,
248 * but without the ugly irq number munging.
249 * However, PIRQD is in the upper instead of lower 4 bits.
251 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
253 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
256 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
258 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
263 * The VIA pirq rules are nibble-based, like ALI,
264 * but without the ugly irq number munging.
265 * However, for 82C586, nibble map is different .
267 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
269 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
271 WARN_ON_ONCE(pirq > 5);
272 return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
275 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
277 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
279 WARN_ON_ONCE(pirq > 5);
280 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
285 * ITE 8330G pirq rules are nibble-based
286 * FIXME: pirqmap may be { 1, 0, 3, 2 },
287 * 2+3 are both mapped to irq 9 on my system
289 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
291 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
293 WARN_ON_ONCE(pirq > 4);
294 return read_config_nybble(router, 0x43, pirqmap[pirq-1]);
297 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
299 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
301 WARN_ON_ONCE(pirq > 4);
302 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
307 * OPTI: high four bits are nibble pointer..
308 * I wonder what the low bits do?
310 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
312 return read_config_nybble(router, 0xb8, pirq >> 4);
315 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
317 write_config_nybble(router, 0xb8, pirq >> 4, irq);
322 * Cyrix: nibble offset 0x5C
323 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
324 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
326 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
328 return read_config_nybble(router, 0x5C, (pirq-1)^1);
331 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
333 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
338 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
339 * We have to deal with the following issues here:
340 * - vendors have different ideas about the meaning of link values
341 * - some onboard devices (integrated in the chipset) have special
342 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
343 * - different revision of the router have a different layout for
344 * the routing registers, particularly for the onchip devices
346 * For all routing registers the common thing is we have one byte
347 * per routeable link which is defined as:
348 * bit 7 IRQ mapping enabled (0) or disabled (1)
349 * bits [6:4] reserved (sometimes used for onchip devices)
350 * bits [3:0] IRQ to map to
351 * allowed: 3-7, 9-12, 14-15
352 * reserved: 0, 1, 2, 8, 13
354 * The config-space registers located at 0x41/0x42/0x43/0x44 are
355 * always used to route the normal PCI INT A/B/C/D respectively.
356 * Apparently there are systems implementing PCI routing table using
357 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
358 * We try our best to handle both link mappings.
360 * Currently (2003-05-21) it appears most SiS chipsets follow the
361 * definition of routing registers from the SiS-5595 southbridge.
362 * According to the SiS 5595 datasheets the revision id's of the
363 * router (ISA-bridge) should be 0x01 or 0xb0.
365 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
366 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
367 * They seem to work with the current routing code. However there is
368 * some concern because of the two USB-OHCI HCs (original SiS 5595
369 * had only one). YMMV.
371 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
374 * bits [6:5] must be written 01
375 * bit 4 channel-select primary (0), secondary (1)
378 * bit 6 OHCI function disabled (0), enabled (1)
380 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
382 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
384 * We support USBIRQ (in addition to INTA-INTD) and keep the
385 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
387 * Currently the only reported exception is the new SiS 65x chipset
388 * which includes the SiS 69x southbridge. Here we have the 85C503
389 * router revision 0x04 and there are changes in the register layout
390 * mostly related to the different USB HCs with USB 2.0 support.
392 * Onchip routing for router rev-id 0x04 (try-and-error observation)
394 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
395 * bit 6-4 are probably unused, not like 5595
398 #define PIRQ_SIS_IRQ_MASK 0x0f
399 #define PIRQ_SIS_IRQ_DISABLE 0x80
400 #define PIRQ_SIS_USB_ENABLE 0x40
402 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
408 if (reg >= 0x01 && reg <= 0x04)
410 pci_read_config_byte(router, reg, &x);
411 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
414 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
420 if (reg >= 0x01 && reg <= 0x04)
422 pci_read_config_byte(router, reg, &x);
423 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
424 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
425 pci_write_config_byte(router, reg, x);
431 * VLSI: nibble offset 0x74 - educated guess due to routing table and
432 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
433 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
434 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
435 * for the busbridge to the docking station.
438 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
440 WARN_ON_ONCE(pirq >= 9);
442 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
445 return read_config_nybble(router, 0x74, pirq-1);
448 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
450 WARN_ON_ONCE(pirq >= 9);
452 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
455 write_config_nybble(router, 0x74, pirq-1, irq);
460 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
461 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
462 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
463 * register is a straight binary coding of desired PIC IRQ (low nibble).
465 * The 'link' value in the PIRQ table is already in the correct format
466 * for the Index register. There are some special index values:
467 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
468 * and 0x03 for SMBus.
470 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
473 return inb(0xc01) & 0xf;
476 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev,
484 /* Support for AMD756 PCI IRQ Routing
485 * Jhon H. Caicedo <jhcaiced@osso.org.co>
486 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
487 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
488 * The AMD756 pirq rules are nibble-based
489 * offset 0x56 0-3 PIRQA 4-7 PIRQB
490 * offset 0x57 0-3 PIRQC 4-7 PIRQD
492 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
497 irq = read_config_nybble(router, 0x56, pirq - 1);
499 "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n",
500 dev->vendor, dev->device, pirq, irq);
504 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
507 "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n",
508 dev->vendor, dev->device, pirq, irq);
510 write_config_nybble(router, 0x56, pirq - 1, irq);
517 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
519 outb(0x10 + ((pirq - 1) >> 1), 0x24);
520 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf);
523 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
527 outb(0x10 + ((pirq - 1) >> 1), 0x24);
529 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq));
534 #ifdef CONFIG_PCI_BIOS
536 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
538 struct pci_dev *bridge;
539 int pin = pci_get_interrupt_pin(dev, &bridge);
540 return pcibios_set_irq_routing(bridge, pin - 1, irq);
545 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
547 static struct pci_device_id __initdata pirq_440gx[] = {
548 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
549 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
553 /* 440GX has a proprietary PIRQ router -- don't use it */
554 if (pci_dev_present(pirq_440gx))
558 case PCI_DEVICE_ID_INTEL_82371FB_0:
559 case PCI_DEVICE_ID_INTEL_82371SB_0:
560 case PCI_DEVICE_ID_INTEL_82371AB_0:
561 case PCI_DEVICE_ID_INTEL_82371MX:
562 case PCI_DEVICE_ID_INTEL_82443MX_0:
563 case PCI_DEVICE_ID_INTEL_82801AA_0:
564 case PCI_DEVICE_ID_INTEL_82801AB_0:
565 case PCI_DEVICE_ID_INTEL_82801BA_0:
566 case PCI_DEVICE_ID_INTEL_82801BA_10:
567 case PCI_DEVICE_ID_INTEL_82801CA_0:
568 case PCI_DEVICE_ID_INTEL_82801CA_12:
569 case PCI_DEVICE_ID_INTEL_82801DB_0:
570 case PCI_DEVICE_ID_INTEL_82801E_0:
571 case PCI_DEVICE_ID_INTEL_82801EB_0:
572 case PCI_DEVICE_ID_INTEL_ESB_1:
573 case PCI_DEVICE_ID_INTEL_ICH6_0:
574 case PCI_DEVICE_ID_INTEL_ICH6_1:
575 case PCI_DEVICE_ID_INTEL_ICH7_0:
576 case PCI_DEVICE_ID_INTEL_ICH7_1:
577 case PCI_DEVICE_ID_INTEL_ICH7_30:
578 case PCI_DEVICE_ID_INTEL_ICH7_31:
579 case PCI_DEVICE_ID_INTEL_TGP_LPC:
580 case PCI_DEVICE_ID_INTEL_ESB2_0:
581 case PCI_DEVICE_ID_INTEL_ICH8_0:
582 case PCI_DEVICE_ID_INTEL_ICH8_1:
583 case PCI_DEVICE_ID_INTEL_ICH8_2:
584 case PCI_DEVICE_ID_INTEL_ICH8_3:
585 case PCI_DEVICE_ID_INTEL_ICH8_4:
586 case PCI_DEVICE_ID_INTEL_ICH9_0:
587 case PCI_DEVICE_ID_INTEL_ICH9_1:
588 case PCI_DEVICE_ID_INTEL_ICH9_2:
589 case PCI_DEVICE_ID_INTEL_ICH9_3:
590 case PCI_DEVICE_ID_INTEL_ICH9_4:
591 case PCI_DEVICE_ID_INTEL_ICH9_5:
592 case PCI_DEVICE_ID_INTEL_EP80579_0:
593 case PCI_DEVICE_ID_INTEL_ICH10_0:
594 case PCI_DEVICE_ID_INTEL_ICH10_1:
595 case PCI_DEVICE_ID_INTEL_ICH10_2:
596 case PCI_DEVICE_ID_INTEL_ICH10_3:
597 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0:
598 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1:
599 r->name = "PIIX/ICH";
600 r->get = pirq_piix_get;
601 r->set = pirq_piix_set;
605 if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN &&
606 device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX)
607 || (device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
608 device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX)
609 || (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN &&
610 device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX)
611 || (device >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
612 device <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) {
613 r->name = "PIIX/ICH";
614 r->get = pirq_piix_get;
615 r->set = pirq_piix_set;
622 static __init int via_router_probe(struct irq_router *r,
623 struct pci_dev *router, u16 device)
625 /* FIXME: We should move some of the quirk fixup stuff here */
628 * workarounds for some buggy BIOSes
630 if (device == PCI_DEVICE_ID_VIA_82C586_0) {
631 switch (router->device) {
632 case PCI_DEVICE_ID_VIA_82C686:
634 * Asus k7m bios wrongly reports 82C686A
637 device = PCI_DEVICE_ID_VIA_82C686;
639 case PCI_DEVICE_ID_VIA_8235:
641 * Asus a7v-x bios wrongly reports 8235
644 device = PCI_DEVICE_ID_VIA_8235;
646 case PCI_DEVICE_ID_VIA_8237:
648 * Asus a7v600 bios wrongly reports 8237
651 device = PCI_DEVICE_ID_VIA_8237;
657 case PCI_DEVICE_ID_VIA_82C586_0:
659 r->get = pirq_via586_get;
660 r->set = pirq_via586_set;
662 case PCI_DEVICE_ID_VIA_82C596:
663 case PCI_DEVICE_ID_VIA_82C686:
664 case PCI_DEVICE_ID_VIA_8231:
665 case PCI_DEVICE_ID_VIA_8233A:
666 case PCI_DEVICE_ID_VIA_8235:
667 case PCI_DEVICE_ID_VIA_8237:
668 /* FIXME: add new ones for 8233/5 */
670 r->get = pirq_via_get;
671 r->set = pirq_via_set;
677 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
680 case PCI_DEVICE_ID_VLSI_82C534:
681 r->name = "VLSI 82C534";
682 r->get = pirq_vlsi_get;
683 r->set = pirq_vlsi_set;
690 static __init int serverworks_router_probe(struct irq_router *r,
691 struct pci_dev *router, u16 device)
694 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
695 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
696 r->name = "ServerWorks";
697 r->get = pirq_serverworks_get;
698 r->set = pirq_serverworks_set;
704 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
706 if (device != PCI_DEVICE_ID_SI_503)
710 r->get = pirq_sis_get;
711 r->set = pirq_sis_set;
715 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
718 case PCI_DEVICE_ID_CYRIX_5520:
720 r->get = pirq_cyrix_get;
721 r->set = pirq_cyrix_set;
727 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
730 case PCI_DEVICE_ID_OPTI_82C700:
732 r->get = pirq_opti_get;
733 r->set = pirq_opti_set;
739 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
742 case PCI_DEVICE_ID_ITE_IT8330G_0:
744 r->get = pirq_ite_get;
745 r->set = pirq_ite_set;
751 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
754 case PCI_DEVICE_ID_AL_M1533:
755 case PCI_DEVICE_ID_AL_M1563:
757 r->get = pirq_ali_get;
758 r->set = pirq_ali_set;
764 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
767 case PCI_DEVICE_ID_AMD_VIPER_740B:
770 case PCI_DEVICE_ID_AMD_VIPER_7413:
773 case PCI_DEVICE_ID_AMD_VIPER_7443:
779 r->get = pirq_amd756_get;
780 r->set = pirq_amd756_set;
784 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
787 case PCI_DEVICE_ID_PICOPOWER_PT86C523:
788 r->name = "PicoPower PT86C523";
789 r->get = pirq_pico_get;
790 r->set = pirq_pico_set;
793 case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP:
794 r->name = "PicoPower PT86C523 rev. BB+";
795 r->get = pirq_pico_get;
796 r->set = pirq_pico_set;
802 static __initdata struct irq_router_handler pirq_routers[] = {
803 { PCI_VENDOR_ID_INTEL, intel_router_probe },
804 { PCI_VENDOR_ID_AL, ali_router_probe },
805 { PCI_VENDOR_ID_ITE, ite_router_probe },
806 { PCI_VENDOR_ID_VIA, via_router_probe },
807 { PCI_VENDOR_ID_OPTI, opti_router_probe },
808 { PCI_VENDOR_ID_SI, sis_router_probe },
809 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
810 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
811 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
812 { PCI_VENDOR_ID_AMD, amd_router_probe },
813 { PCI_VENDOR_ID_PICOPOWER, pico_router_probe },
814 /* Someone with docs needs to add the ATI Radeon IGP */
817 static struct irq_router pirq_router;
818 static struct pci_dev *pirq_router_dev;
822 * FIXME: should we have an option to say "generic for
826 static void __init pirq_find_router(struct irq_router *r)
828 struct irq_routing_table *rt = pirq_table;
829 struct irq_router_handler *h;
831 #ifdef CONFIG_PCI_BIOS
832 if (!rt->signature) {
833 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
834 r->set = pirq_bios_set;
840 /* Default unless a driver reloads it */
845 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n",
846 rt->rtr_vendor, rt->rtr_device);
848 pirq_router_dev = pci_get_bus_and_slot(rt->rtr_bus, rt->rtr_devfn);
849 if (!pirq_router_dev) {
850 DBG(KERN_DEBUG "PCI: Interrupt router not found at "
851 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
855 for (h = pirq_routers; h->vendor; h++) {
856 /* First look for a router match */
857 if (rt->rtr_vendor == h->vendor &&
858 h->probe(r, pirq_router_dev, rt->rtr_device))
860 /* Fall back to a device match */
861 if (pirq_router_dev->vendor == h->vendor &&
862 h->probe(r, pirq_router_dev, pirq_router_dev->device))
865 dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n",
867 pirq_router_dev->vendor, pirq_router_dev->device);
869 /* The device remains referenced for the kernel lifetime */
872 static struct irq_info *pirq_get_info(struct pci_dev *dev)
874 struct irq_routing_table *rt = pirq_table;
875 int entries = (rt->size - sizeof(struct irq_routing_table)) /
876 sizeof(struct irq_info);
877 struct irq_info *info;
879 for (info = rt->slots; entries--; info++)
880 if (info->bus == dev->bus->number &&
881 PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
886 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
889 struct irq_info *info;
893 struct irq_router *r = &pirq_router;
894 struct pci_dev *dev2 = NULL;
898 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
900 dev_dbg(&dev->dev, "no interrupt pin\n");
904 if (io_apic_assign_pci_irqs)
907 /* Find IRQ routing entry */
912 info = pirq_get_info(dev);
914 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n",
918 pirq = info->irq[pin - 1].link;
919 mask = info->irq[pin - 1].bitmap;
921 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin - 1);
924 dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x",
925 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs);
926 mask &= pcibios_irq_mask;
928 /* Work around broken HP Pavilion Notebooks which assign USB to
929 IRQ 9 even though it is actually wired to IRQ 11 */
931 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
933 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
934 r->set(pirq_router_dev, dev, pirq, 11);
937 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
938 if (acer_tm360_irqrouting && dev->irq == 11 &&
939 dev->vendor == PCI_VENDOR_ID_O2) {
942 dev->irq = r->get(pirq_router_dev, dev, pirq);
943 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
947 * Find the best IRQ to assign: use the one
948 * reported by the device if possible.
951 if (newirq && !((1 << newirq) & mask)) {
952 if (pci_probe & PCI_USE_PIRQ_MASK)
955 dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask "
956 "%#x; try pci=usepirqmask\n", newirq, mask);
958 if (!newirq && assign) {
959 for (i = 0; i < 16; i++) {
960 if (!(mask & (1 << i)))
962 if (pirq_penalty[i] < pirq_penalty[newirq] &&
963 can_request_irq(i, IRQF_SHARED))
967 dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin - 1, newirq);
969 /* Check if it is hardcoded */
970 if ((pirq & 0xf0) == 0xf0) {
973 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
974 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) {
976 eisa_set_level_irq(irq);
977 } else if (newirq && r->set &&
978 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
979 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
980 eisa_set_level_irq(newirq);
987 if (newirq && mask == (1 << newirq)) {
991 dev_dbg(&dev->dev, "can't route interrupt\n");
995 dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin - 1, irq);
997 /* Update IRQ for all devices with the same pirq value */
998 for_each_pci_dev(dev2) {
999 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
1003 info = pirq_get_info(dev2);
1006 if (info->irq[pin - 1].link == pirq) {
1008 * We refuse to override the dev->irq
1009 * information. Give a warning!
1011 if (dev2->irq && dev2->irq != irq && \
1012 (!(pci_probe & PCI_USE_PIRQ_MASK) || \
1013 ((1 << dev2->irq) & mask))) {
1014 #ifndef CONFIG_PCI_MSI
1015 dev_info(&dev2->dev, "IRQ routing conflict: "
1016 "have IRQ %d, want IRQ %d\n",
1022 pirq_penalty[irq]++;
1024 dev_info(&dev->dev, "sharing IRQ %d with %s\n",
1025 irq, pci_name(dev2));
1031 void __init pcibios_fixup_irqs(void)
1033 struct pci_dev *dev = NULL;
1036 DBG(KERN_DEBUG "PCI: IRQ fixup\n");
1037 for_each_pci_dev(dev) {
1039 * If the BIOS has set an out of range IRQ number, just
1040 * ignore it. Also keep track of which IRQ's are
1043 if (dev->irq >= 16) {
1044 dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq);
1048 * If the IRQ is already assigned to a PCI device,
1049 * ignore its ISA use penalty
1051 if (pirq_penalty[dev->irq] >= 100 &&
1052 pirq_penalty[dev->irq] < 100000)
1053 pirq_penalty[dev->irq] = 0;
1054 pirq_penalty[dev->irq]++;
1057 if (io_apic_assign_pci_irqs)
1061 for_each_pci_dev(dev) {
1062 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1067 * Still no IRQ? Try to lookup one...
1070 pcibios_lookup_irq(dev, 0);
1075 * Work around broken HP Pavilion Notebooks which assign USB to
1076 * IRQ 9 even though it is actually wired to IRQ 11
1078 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d)
1080 if (!broken_hp_bios_irq9) {
1081 broken_hp_bios_irq9 = 1;
1082 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1089 * Work around broken Acer TravelMate 360 Notebooks which assign
1090 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
1092 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d)
1094 if (!acer_tm360_irqrouting) {
1095 acer_tm360_irqrouting = 1;
1096 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1102 static struct dmi_system_id __initdata pciirq_dmi_table[] = {
1104 .callback = fix_broken_hp_bios_irq9,
1105 .ident = "HP Pavilion N5400 Series Laptop",
1107 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1108 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
1109 DMI_MATCH(DMI_PRODUCT_VERSION,
1110 "HP Pavilion Notebook Model GE"),
1111 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
1115 .callback = fix_acer_tm360_irqrouting,
1116 .ident = "Acer TravelMate 36x Laptop",
1118 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1119 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
1125 void __init pcibios_irq_init(void)
1127 DBG(KERN_DEBUG "PCI: IRQ init\n");
1129 if (raw_pci_ops == NULL)
1132 dmi_check_system(pciirq_dmi_table);
1134 pirq_table = pirq_find_routing_table();
1136 #ifdef CONFIG_PCI_BIOS
1137 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
1138 pirq_table = pcibios_get_irq_routing_table();
1142 pirq_find_router(&pirq_router);
1143 if (pirq_table->exclusive_irqs) {
1145 for (i = 0; i < 16; i++)
1146 if (!(pirq_table->exclusive_irqs & (1 << i)))
1147 pirq_penalty[i] += 100;
1150 * If we're using the I/O APIC, avoid using the PCI IRQ
1153 if (io_apic_assign_pci_irqs)
1157 x86_init.pci.fixup_irqs();
1159 if (io_apic_assign_pci_irqs && pci_routeirq) {
1160 struct pci_dev *dev = NULL;
1162 * PCI IRQ routing is set up by pci_enable_device(), but we
1163 * also do it here in case there are still broken drivers that
1164 * don't use pci_enable_device().
1166 printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
1167 for_each_pci_dev(dev)
1168 pirq_enable_irq(dev);
1172 static void pirq_penalize_isa_irq(int irq, int active)
1175 * If any ISAPnP device reports an IRQ in its list of possible
1176 * IRQ's, we try to avoid assigning it to PCI devices.
1180 pirq_penalty[irq] += 1000;
1182 pirq_penalty[irq] += 100;
1186 void pcibios_penalize_isa_irq(int irq, int active)
1190 acpi_penalize_isa_irq(irq, active);
1193 pirq_penalize_isa_irq(irq, active);
1196 static int pirq_enable_irq(struct pci_dev *dev)
1200 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1201 if (pin && !pcibios_lookup_irq(dev, 1)) {
1204 if (!io_apic_assign_pci_irqs && dev->irq)
1207 if (io_apic_assign_pci_irqs) {
1208 #ifdef CONFIG_X86_IO_APIC
1209 struct pci_dev *temp_dev;
1211 struct io_apic_irq_attr irq_attr;
1213 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number,
1214 PCI_SLOT(dev->devfn),
1215 pin - 1, &irq_attr);
1217 * Busses behind bridges are typically not listed in the MP-table.
1218 * In this case we have to look up the IRQ based on the parent bus,
1219 * parent slot, and pin number. The SMP code detects such bridged
1220 * busses itself so we should get into this branch reliably.
1223 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1224 struct pci_dev *bridge = dev->bus->self;
1226 pin = pci_swizzle_interrupt_pin(dev, pin);
1227 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1228 PCI_SLOT(bridge->devfn),
1229 pin - 1, &irq_attr);
1231 dev_warn(&dev->dev, "using bridge %s "
1232 "INT %c to get IRQ %d\n",
1233 pci_name(bridge), 'A' + pin - 1,
1239 io_apic_set_pci_routing(&dev->dev, irq,
1242 dev_info(&dev->dev, "PCI->APIC IRQ transform: "
1243 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq);
1246 msg = "; probably buggy MP table";
1248 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1251 msg = "; please try using pci=biosirq";
1254 * With IDE legacy devices the IRQ lookup failure is not
1257 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE &&
1258 !(dev->class & 0x5))
1261 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n",
1262 'A' + pin - 1, msg);