arch/x86/kernel/quirks.c

   1 /*
   2  * This file contains work-arounds for x86 and x86_64 platform bugs.
   3  */
   4 #include <linux/pci.h>
   5 #include <linux/irq.h>
   6
   7 #if defined(CONFIG_X86_IO_APIC) && (defined(CONFIG_SMP) || defined(CONFIG_XEN)) && defined(CONFIG_PCI)
   8
   9 static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
  10 {
  11         u8 config;
  12         u16 word;
  13
  14         /* BIOS may enable hardware IRQ balancing for
  15          * E7520/E7320/E7525(revision ID 0x9 and below)
  16          * based platforms.
  17          * Disable SW irqbalance/affinity on those platforms.
  18          */
  19         if (dev->revision > 0x9)
  20                 return;
  21
  22         /* enable access to config space*/
  23         pci_read_config_byte(dev, 0xf4, &config);
  24         pci_write_config_byte(dev, 0xf4, config|0x2);
  25
  26         /*
  27          * read xTPR register.  We may not have a pci_dev for device 8
  28          * because it might be hidden until the above write.
  29          */
  30         pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
  31
  32         if (!(word & (1 << 13))) {
  33                 dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
  34                         "disabling irq balancing and affinity\n");
  35 #ifndef CONFIG_XEN
  36                 noirqdebug_setup("");
  37 #ifdef CONFIG_PROC_FS
  38                 no_irq_affinity = 1;
  39 #endif
  40 #else
  41                 {
  42                         struct xen_platform_op op = {
  43                                 .cmd = XENPF_platform_quirk,
  44                                 .u.platform_quirk.quirk_id = QUIRK_NOIRQBALANCING
  45                         };
  46
  47                         WARN_ON(HYPERVISOR_platform_op(&op));
  48                 }
  49 #endif
  50         }
  51
  52         /* put back the original value for config space*/
  53         if (!(config & 0x2))
  54                 pci_write_config_byte(dev, 0xf4, config);
  55 }
  56 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
  57                         quirk_intel_irqbalance);
  58 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
  59                         quirk_intel_irqbalance);
  60 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
  61                         quirk_intel_irqbalance);
  62 #endif
  63
  64 #if defined(CONFIG_HPET_TIMER)
  65 #include <asm/hpet.h>
  66
  67 unsigned long force_hpet_address;
  68
  69 static enum {
  70         NONE_FORCE_HPET_RESUME,
  71         OLD_ICH_FORCE_HPET_RESUME,
  72         ICH_FORCE_HPET_RESUME,
  73         VT8237_FORCE_HPET_RESUME,
  74         NVIDIA_FORCE_HPET_RESUME,
  75         ATI_FORCE_HPET_RESUME,
  76 } force_hpet_resume_type;
  77
  78 static void __iomem *rcba_base;
  79
  80 static void ich_force_hpet_resume(void)
  81 {
  82         u32 val;
  83
  84         if (!force_hpet_address)
  85                 return;
  86
  87         BUG_ON(rcba_base == NULL);
  88
  89         /* read the Function Disable register, dword mode only */
  90         val = readl(rcba_base + 0x3404);
  91         if (!(val & 0x80)) {
  92                 /* HPET disabled in HPTC. Trying to enable */
  93                 writel(val | 0x80, rcba_base + 0x3404);
  94         }
  95
  96         val = readl(rcba_base + 0x3404);
  97         if (!(val & 0x80))
  98                 BUG();
  99         else
 100                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
 101
 102         return;
 103 }
 104
 105 static void ich_force_enable_hpet(struct pci_dev *dev)
 106 {
 107         u32 val;
 108         u32 uninitialized_var(rcba);
 109         int err = 0;
 110
 111         if (hpet_address || force_hpet_address)
 112                 return;
 113
 114         pci_read_config_dword(dev, 0xF0, &rcba);
 115         rcba &= 0xFFFFC000;
 116         if (rcba == 0) {
 117                 dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
 118                         "cannot force enable HPET\n");
 119                 return;
 120         }
 121
 122         /* use bits 31:14, 16 kB aligned */
 123         rcba_base = ioremap_nocache(rcba, 0x4000);
 124         if (rcba_base == NULL) {
 125                 dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
 126                         "cannot force enable HPET\n");
 127                 return;
 128         }
 129
 130         /* read the Function Disable register, dword mode only */
 131         val = readl(rcba_base + 0x3404);
 132
 133         if (val & 0x80) {
 134                 /* HPET is enabled in HPTC. Just not reported by BIOS */
 135                 val = val & 0x3;
 136                 force_hpet_address = 0xFED00000 | (val << 12);
 137                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 138                         "0x%lx\n", force_hpet_address);
 139                 iounmap(rcba_base);
 140                 return;
 141         }
 142
 143         /* HPET disabled in HPTC. Trying to enable */
 144         writel(val | 0x80, rcba_base + 0x3404);
 145
 146         val = readl(rcba_base + 0x3404);
 147         if (!(val & 0x80)) {
 148                 err = 1;
 149         } else {
 150                 val = val & 0x3;
 151                 force_hpet_address = 0xFED00000 | (val << 12);
 152         }
 153
 154         if (err) {
 155                 force_hpet_address = 0;
 156                 iounmap(rcba_base);
 157                 dev_printk(KERN_DEBUG, &dev->dev,
 158                         "Failed to force enable HPET\n");
 159         } else {
 160                 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
 161                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 162                         "0x%lx\n", force_hpet_address);
 163         }
 164 }
 165
 166 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
 167                          ich_force_enable_hpet);
 168 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
 169                          ich_force_enable_hpet);
 170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
 171                          ich_force_enable_hpet);
 172 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
 173                          ich_force_enable_hpet);
 174 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
 175                          ich_force_enable_hpet);
 176 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
 177                          ich_force_enable_hpet);
 178 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
 179                          ich_force_enable_hpet);
 180 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4,
 181                          ich_force_enable_hpet);
 182 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
 183                          ich_force_enable_hpet);
 184 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x3a16,   /* ICH10 */
 185                          ich_force_enable_hpet);
 186
 187 static struct pci_dev *cached_dev;
 188
 189 static void hpet_print_force_info(void)
 190 {
 191         printk(KERN_INFO "HPET not enabled in BIOS. "
 192                "You might try hpet=force boot option\n");
 193 }
 194
 195 static void old_ich_force_hpet_resume(void)
 196 {
 197         u32 val;
 198         u32 uninitialized_var(gen_cntl);
 199
 200         if (!force_hpet_address || !cached_dev)
 201                 return;
 202
 203         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
 204         gen_cntl &= (~(0x7 << 15));
 205         gen_cntl |= (0x4 << 15);
 206
 207         pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
 208         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
 209         val = gen_cntl >> 15;
 210         val &= 0x7;
 211         if (val == 0x4)
 212                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
 213         else
 214                 BUG();
 215 }
 216
 217 static void old_ich_force_enable_hpet(struct pci_dev *dev)
 218 {
 219         u32 val;
 220         u32 uninitialized_var(gen_cntl);
 221
 222         if (hpet_address || force_hpet_address)
 223                 return;
 224
 225         pci_read_config_dword(dev, 0xD0, &gen_cntl);
 226         /*
 227          * Bit 17 is HPET enable bit.
 228          * Bit 16:15 control the HPET base address.
 229          */
 230         val = gen_cntl >> 15;
 231         val &= 0x7;
 232         if (val & 0x4) {
 233                 val &= 0x3;
 234                 force_hpet_address = 0xFED00000 | (val << 12);
 235                 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
 236                         force_hpet_address);
 237                 return;
 238         }
 239
 240         /*
 241          * HPET is disabled. Trying enabling at FED00000 and check
 242          * whether it sticks
 243          */
 244         gen_cntl &= (~(0x7 << 15));
 245         gen_cntl |= (0x4 << 15);
 246         pci_write_config_dword(dev, 0xD0, gen_cntl);
 247
 248         pci_read_config_dword(dev, 0xD0, &gen_cntl);
 249
 250         val = gen_cntl >> 15;
 251         val &= 0x7;
 252         if (val & 0x4) {
 253                 /* HPET is enabled in HPTC. Just not reported by BIOS */
 254                 val &= 0x3;
 255                 force_hpet_address = 0xFED00000 | (val << 12);
 256                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 257                         "0x%lx\n", force_hpet_address);
 258                 cached_dev = dev;
 259                 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
 260                 return;
 261         }
 262
 263         dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
 264 }
 265
 266 /*
 267  * Undocumented chipset features. Make sure that the user enforced
 268  * this.
 269  */
 270 static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
 271 {
 272         if (hpet_force_user)
 273                 old_ich_force_enable_hpet(dev);
 274 }
 275
 276 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
 277                          old_ich_force_enable_hpet_user);
 278 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
 279                          old_ich_force_enable_hpet_user);
 280 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
 281                          old_ich_force_enable_hpet_user);
 282 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
 283                          old_ich_force_enable_hpet_user);
 284 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
 285                          old_ich_force_enable_hpet_user);
 286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
 287                          old_ich_force_enable_hpet);
 288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
 289                          old_ich_force_enable_hpet);
 290
 291
 292 static void vt8237_force_hpet_resume(void)
 293 {
 294         u32 val;
 295
 296         if (!force_hpet_address || !cached_dev)
 297                 return;
 298
 299         val = 0xfed00000 | 0x80;
 300         pci_write_config_dword(cached_dev, 0x68, val);
 301
 302         pci_read_config_dword(cached_dev, 0x68, &val);
 303         if (val & 0x80)
 304                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
 305         else
 306                 BUG();
 307 }
 308
 309 static void vt8237_force_enable_hpet(struct pci_dev *dev)
 310 {
 311         u32 uninitialized_var(val);
 312
 313         if (hpet_address || force_hpet_address)
 314                 return;
 315
 316         if (!hpet_force_user) {
 317                 hpet_print_force_info();
 318                 return;
 319         }
 320
 321         pci_read_config_dword(dev, 0x68, &val);
 322         /*
 323          * Bit 7 is HPET enable bit.
 324          * Bit 31:10 is HPET base address (contrary to what datasheet claims)
 325          */
 326         if (val & 0x80) {
 327                 force_hpet_address = (val & ~0x3ff);
 328                 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
 329                         force_hpet_address);
 330                 return;
 331         }
 332
 333         /*
 334          * HPET is disabled. Trying enabling at FED00000 and check
 335          * whether it sticks
 336          */
 337         val = 0xfed00000 | 0x80;
 338         pci_write_config_dword(dev, 0x68, val);
 339
 340         pci_read_config_dword(dev, 0x68, &val);
 341         if (val & 0x80) {
 342                 force_hpet_address = (val & ~0x3ff);
 343                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 344                         "0x%lx\n", force_hpet_address);
 345                 cached_dev = dev;
 346                 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
 347                 return;
 348         }
 349
 350         dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
 351 }
 352
 353 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
 354                          vt8237_force_enable_hpet);
 355 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
 356                          vt8237_force_enable_hpet);
 357 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CX700,
 358                          vt8237_force_enable_hpet);
 359
 360 static void ati_force_hpet_resume(void)
 361 {
 362         pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
 363         printk(KERN_DEBUG "Force enabled HPET at resume\n");
 364 }
 365
 366 static u32 ati_ixp4x0_rev(struct pci_dev *dev)
 367 {
 368         u32 d;
 369         u8  b;
 370
 371         pci_read_config_byte(dev, 0xac, &b);
 372         b &= ~(1<<5);
 373         pci_write_config_byte(dev, 0xac, b);
 374         pci_read_config_dword(dev, 0x70, &d);
 375         d |= 1<<8;
 376         pci_write_config_dword(dev, 0x70, d);
 377         pci_read_config_dword(dev, 0x8, &d);
 378         d &= 0xff;
 379         dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d);
 380         return d;
 381 }
 382
 383 static void ati_force_enable_hpet(struct pci_dev *dev)
 384 {
 385         u32 d, val;
 386         u8  b;
 387
 388         if (hpet_address || force_hpet_address)
 389                 return;
 390
 391         if (!hpet_force_user) {
 392                 hpet_print_force_info();
 393                 return;
 394         }
 395
 396         d = ati_ixp4x0_rev(dev);
 397         if (d  < 0x82)
 398                 return;
 399
 400         /* base address */
 401         pci_write_config_dword(dev, 0x14, 0xfed00000);
 402         pci_read_config_dword(dev, 0x14, &val);
 403
 404         /* enable interrupt */
 405         outb(0x72, 0xcd6); b = inb(0xcd7);
 406         b |= 0x1;
 407         outb(0x72, 0xcd6); outb(b, 0xcd7);
 408         outb(0x72, 0xcd6); b = inb(0xcd7);
 409         if (!(b & 0x1))
 410                 return;
 411         pci_read_config_dword(dev, 0x64, &d);
 412         d |= (1<<10);
 413         pci_write_config_dword(dev, 0x64, d);
 414         pci_read_config_dword(dev, 0x64, &d);
 415         if (!(d & (1<<10)))
 416                 return;
 417
 418         force_hpet_address = val;
 419         force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
 420         dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
 421                    force_hpet_address);
 422         cached_dev = dev;
 423 }
 424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
 425                          ati_force_enable_hpet);
 426
 427 /*
 428  * Undocumented chipset feature taken from LinuxBIOS.
 429  */
 430 static void nvidia_force_hpet_resume(void)
 431 {
 432         pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
 433         printk(KERN_DEBUG "Force enabled HPET at resume\n");
 434 }
 435
 436 static void nvidia_force_enable_hpet(struct pci_dev *dev)
 437 {
 438         u32 uninitialized_var(val);
 439
 440         if (hpet_address || force_hpet_address)
 441                 return;
 442
 443         if (!hpet_force_user) {
 444                 hpet_print_force_info();
 445                 return;
 446         }
 447
 448         pci_write_config_dword(dev, 0x44, 0xfed00001);
 449         pci_read_config_dword(dev, 0x44, &val);
 450         force_hpet_address = val & 0xfffffffe;
 451         force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
 452         dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
 453                 force_hpet_address);
 454         cached_dev = dev;
 455         return;
 456 }
 457
 458 /* ISA Bridges */
 459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
 460                         nvidia_force_enable_hpet);
 461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
 462                         nvidia_force_enable_hpet);
 463
 464 /* LPC bridges */
 465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
 466                         nvidia_force_enable_hpet);
 467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
 468                         nvidia_force_enable_hpet);
 469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
 470                         nvidia_force_enable_hpet);
 471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
 472                         nvidia_force_enable_hpet);
 473 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
 474                         nvidia_force_enable_hpet);
 475 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
 476                         nvidia_force_enable_hpet);
 477 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
 478                         nvidia_force_enable_hpet);
 479 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
 480                         nvidia_force_enable_hpet);
 481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
 482                         nvidia_force_enable_hpet);
 483
 484 void force_hpet_resume(void)
 485 {
 486         switch (force_hpet_resume_type) {
 487         case ICH_FORCE_HPET_RESUME:
 488                 ich_force_hpet_resume();
 489                 return;
 490         case OLD_ICH_FORCE_HPET_RESUME:
 491                 old_ich_force_hpet_resume();
 492                 return;
 493         case VT8237_FORCE_HPET_RESUME:
 494                 vt8237_force_hpet_resume();
 495                 return;
 496         case NVIDIA_FORCE_HPET_RESUME:
 497                 nvidia_force_hpet_resume();
 498                 return;
 499         case ATI_FORCE_HPET_RESUME:
 500                 ati_force_hpet_resume();
 501                 return;
 502         default:
 503                 break;
 504         }
 505 }
 506
 507 /*
 508  * HPET MSI on some boards (ATI SB700/SB800) has side effect on
 509  * floppy DMA. Disable HPET MSI on such platforms.
 510  * See erratum #27 (Misinterpreted MSI Requests May Result in
 511  * Corrupted LPC DMA Data) in AMD Publication #46837,
 512  * "SB700 Family Product Errata", Rev. 1.0, March 2010.
 513  */
 514 static void force_disable_hpet_msi(struct pci_dev *unused)
 515 {
 516         hpet_msi_disable = 1;
 517 }
 518
 519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
 520                          force_disable_hpet_msi);
 521
 522 #endif
 523
 524 #if defined(CONFIG_PCI) && defined(CONFIG_NUMA)
 525 /* Set correct numa_node information for AMD NB functions */
 526 static void __init quirk_amd_nb_node(struct pci_dev *dev)
 527 {
 528         struct pci_dev *nb_ht;
 529         unsigned int devfn;
 530         u32 node;
 531         u32 val;
 532
 533         devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
 534         nb_ht = pci_get_slot(dev->bus, devfn);
 535         if (!nb_ht)
 536                 return;
 537
 538         pci_read_config_dword(nb_ht, 0x60, &val);
 539         node = val & 7;
 540         /*
 541          * Some hardware may return an invalid node ID,
 542          * so check it first:
 543          */
 544         if (node_online(node))
 545                 set_dev_node(&dev->dev, node);
 546         pci_dev_put(nb_ht);
 547 }
 548
 549 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
 550                         quirk_amd_nb_node);
 551 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
 552                         quirk_amd_nb_node);
 553 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
 554                         quirk_amd_nb_node);
 555 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC,
 556                         quirk_amd_nb_node);
 557 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_HT,
 558                         quirk_amd_nb_node);
 559 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MAP,
 560                         quirk_amd_nb_node);
 561 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_DRAM,
 562                         quirk_amd_nb_node);
 563 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC,
 564                         quirk_amd_nb_node);
 565 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_LINK,
 566                         quirk_amd_nb_node);
 567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F0,
 568                         quirk_amd_nb_node);
 569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F1,
 570                         quirk_amd_nb_node);
 571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F2,
 572                         quirk_amd_nb_node);
 573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3,
 574                         quirk_amd_nb_node);
 575 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4,
 576                         quirk_amd_nb_node);
 577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F5,
 578                         quirk_amd_nb_node);
 579
 580 #endif