arch/x86/kernel/hpet.c

   1 #include <linux/clocksource.h>
   2 #include <linux/clockchips.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/export.h>
   5 #include <linux/delay.h>
   6 #include <linux/errno.h>
   7 #include <linux/i8253.h>
   8 #include <linux/slab.h>
   9 #include <linux/hpet.h>
  10 #include <linux/init.h>
  11 #include <linux/cpu.h>
  12 #include <linux/pm.h>
  13 #include <linux/io.h>
  14
  15 #include <asm/fixmap.h>
  16 #include <asm/hpet.h>
  17 #include <asm/time.h>
  18
  19 #define HPET_MASK                       CLOCKSOURCE_MASK(32)
  20
  21 /* FSEC = 10^-15
  22    NSEC = 10^-9 */
  23 #define FSEC_PER_NSEC                   1000000L
  24
  25 #define HPET_DEV_USED_BIT               2
  26 #define HPET_DEV_USED                   (1 << HPET_DEV_USED_BIT)
  27 #define HPET_DEV_VALID                  0x8
  28 #define HPET_DEV_FSB_CAP                0x1000
  29 #define HPET_DEV_PERI_CAP               0x2000
  30
  31 #define HPET_MIN_CYCLES                 128
  32 #define HPET_MIN_PROG_DELTA             (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
  33
  34 /*
  35  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  36  */
  37 unsigned long                           hpet_address;
  38 u8                                      hpet_blockid; /* OS timer block num */
  39 u8                                      hpet_msi_disable;
  40
  41 #ifdef CONFIG_PCI_MSI
  42 static unsigned long                    hpet_num_timers;
  43 #endif
  44 static void __iomem                     *hpet_virt_address;
  45 static int hpet_legacy_use_64_bits;
  46
  47 struct hpet_dev {
  48         struct clock_event_device       evt;
  49         unsigned int                    num;
  50         int                             cpu;
  51         unsigned int                    irq;
  52         unsigned int                    flags;
  53         char                            name[10];
  54 };
  55
  56 inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
  57 {
  58         return container_of(evtdev, struct hpet_dev, evt);
  59 }
  60
  61 inline unsigned int hpet_readl(unsigned int a)
  62 {
  63         return readl(hpet_virt_address + a);
  64 }
  65
  66 static inline void hpet_writel(unsigned int d, unsigned int a)
  67 {
  68         writel(d, hpet_virt_address + a);
  69 }
  70
  71 #ifdef CONFIG_X86_64
  72 #include <asm/pgtable.h>
  73 static inline unsigned long hpet_read_value(unsigned long a)
  74 {
  75         if (hpet_legacy_use_64_bits)
  76                 return readq(hpet_virt_address + a);
  77         else
  78                 return readl(hpet_virt_address + a);
  79 }
  80
  81 static void hpet_write_value(unsigned long d, unsigned long a)
  82 {
  83         if (hpet_legacy_use_64_bits)
  84                 writeq(d, hpet_virt_address + a);
  85         else
  86                 writel(d, hpet_virt_address + a);
  87 }
  88
  89 #else
  90
  91 static inline unsigned long hpet_read_value(unsigned long a)
  92 {
  93         return readl(hpet_virt_address + a);
  94 }
  95
  96 static void hpet_write_value(unsigned long d, unsigned long a)
  97 {
  98         writel(d, hpet_virt_address + a);
  99 }
 100 #endif
 101
 102 static inline void hpet_set_mapping(void)
 103 {
 104         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
 105 #ifdef CONFIG_X86_64
 106         __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE);
 107 #endif
 108 }
 109
 110 static inline void hpet_clear_mapping(void)
 111 {
 112         iounmap(hpet_virt_address);
 113         hpet_virt_address = NULL;
 114 }
 115
 116 /*
 117  * HPET command line enable / disable
 118  */
 119 static int boot_hpet_disable;
 120 int hpet_force_user;
 121 static int hpet_verbose;
 122
 123 static int __init hpet_setup(char *str)
 124 {
 125         if (str) {
 126                 if (!strncmp("disable", str, 7))
 127                         boot_hpet_disable = 1;
 128                 if (!strncmp("force", str, 5))
 129                         hpet_force_user = 1;
 130                 if (!strncmp("verbose", str, 7))
 131                         hpet_verbose = 1;
 132         }
 133         return 1;
 134 }
 135 __setup("hpet=", hpet_setup);
 136
 137 static int __init disable_hpet(char *str)
 138 {
 139         boot_hpet_disable = 1;
 140         return 1;
 141 }
 142 __setup("nohpet", disable_hpet);
 143
 144 #ifdef CONFIG_X86_64
 145 static int hpet64 = 0;
 146 static int __init hpet64_setup(char *str)
 147 {
 148         hpet64 = 1;
 149         return 1;
 150 }
 151 __setup("hpet64", hpet64_setup);
 152 #endif
 153
 154
 155 static inline int is_hpet_capable(void)
 156 {
 157         return !boot_hpet_disable && hpet_address;
 158 }
 159
 160 /*
 161  * HPET timer interrupt enable / disable
 162  */
 163 static int hpet_legacy_int_enabled;
 164
 165 /**
 166  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 167  */
 168 int is_hpet_enabled(void)
 169 {
 170         return is_hpet_capable() && hpet_legacy_int_enabled;
 171 }
 172 EXPORT_SYMBOL_GPL(is_hpet_enabled);
 173
 174 static void _hpet_print_config(const char *function, int line)
 175 {
 176         u32 i, timers, l, h;
 177         printk(KERN_INFO "hpet: %s(%d):\n", function, line);
 178         l = hpet_readl(HPET_ID);
 179         h = hpet_readl(HPET_PERIOD);
 180         timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 181         printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
 182         l = hpet_readl(HPET_CFG);
 183         h = hpet_readl(HPET_STATUS);
 184         printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
 185         l = hpet_readl(HPET_COUNTER);
 186         h = hpet_readl(HPET_COUNTER+4);
 187         printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
 188
 189         for (i = 0; i < timers; i++) {
 190                 l = hpet_readl(HPET_Tn_CFG(i));
 191                 h = hpet_readl(HPET_Tn_CFG(i)+4);
 192                 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
 193                        i, l, h);
 194                 l = hpet_readl(HPET_Tn_CMP(i));
 195                 h = hpet_readl(HPET_Tn_CMP(i)+4);
 196                 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
 197                        i, l, h);
 198                 l = hpet_readl(HPET_Tn_ROUTE(i));
 199                 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
 200                 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
 201                        i, l, h);
 202         }
 203 }
 204
 205 #define hpet_print_config()                                     \
 206 do {                                                            \
 207         if (hpet_verbose)                                       \
 208                 _hpet_print_config(__FUNCTION__, __LINE__);     \
 209 } while (0)
 210
 211 /*
 212  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 213  * timer 0 and timer 1 in case of RTC emulation.
 214  */
 215 #ifdef CONFIG_HPET
 216
 217 static void hpet_reserve_msi_timers(struct hpet_data *hd);
 218
 219 static void hpet_reserve_platform_timers(unsigned int id)
 220 {
 221         struct hpet __iomem *hpet = hpet_virt_address;
 222         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
 223         unsigned int nrtimers, i;
 224         struct hpet_data hd;
 225
 226         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 227
 228         memset(&hd, 0, sizeof(hd));
 229         hd.hd_phys_address      = hpet_address;
 230         hd.hd_address           = hpet;
 231         hd.hd_nirqs             = nrtimers;
 232         hpet_reserve_timer(&hd, 0);
 233
 234 #ifdef CONFIG_HPET_EMULATE_RTC
 235         hpet_reserve_timer(&hd, 1);
 236 #endif
 237
 238         /*
 239          * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
 240          * is wrong for i8259!) not the output IRQ.  Many BIOS writers
 241          * don't bother configuring *any* comparator interrupts.
 242          */
 243         hd.hd_irq[0] = HPET_LEGACY_8254;
 244         hd.hd_irq[1] = HPET_LEGACY_RTC;
 245
 246         for (i = 2; i < nrtimers; timer++, i++) {
 247                 hd.hd_irq[i] = (readl(&timer->hpet_config) &
 248                         Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
 249         }
 250
 251         hpet_reserve_msi_timers(&hd);
 252
 253         hpet_alloc(&hd);
 254
 255 }
 256 #else
 257 static void hpet_reserve_platform_timers(unsigned int id) { }
 258 #endif
 259
 260 /*
 261  * Common hpet info
 262  */
 263 static unsigned long hpet_freq;
 264 static int hpet_legacy_use_64_bits; /* configure T0 in 64-bit mode? */
 265
 266 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 267                           struct clock_event_device *evt);
 268 static int hpet_legacy_next_event(unsigned long delta,
 269                            struct clock_event_device *evt);
 270
 271 /*
 272  * The hpet clock event device
 273  */
 274 static struct clock_event_device hpet_clockevent = {
 275         .name           = "hpet",
 276         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 277         .set_mode       = hpet_legacy_set_mode,
 278         .set_next_event = hpet_legacy_next_event,
 279         .irq            = 0,
 280         .rating         = 50,
 281 };
 282
 283 static void hpet_stop_counter(void)
 284 {
 285         unsigned long cfg = hpet_readl(HPET_CFG);
 286         cfg &= ~HPET_CFG_ENABLE;
 287         hpet_writel(cfg, HPET_CFG);
 288 }
 289
 290 static void hpet_reset_counter(void)
 291 {
 292         hpet_writel(0, HPET_COUNTER);
 293         hpet_writel(0, HPET_COUNTER + 4);
 294 }
 295
 296 static void hpet_start_counter(void)
 297 {
 298         unsigned int cfg = hpet_readl(HPET_CFG);
 299         cfg |= HPET_CFG_ENABLE;
 300         hpet_writel(cfg, HPET_CFG);
 301 }
 302
 303 static void hpet_restart_counter(void)
 304 {
 305         hpet_stop_counter();
 306         hpet_reset_counter();
 307         hpet_start_counter();
 308 }
 309
 310 static void hpet_resume_device(void)
 311 {
 312         force_hpet_resume();
 313 }
 314
 315 static void hpet_resume_counter(struct clocksource *cs)
 316 {
 317         hpet_resume_device();
 318         hpet_restart_counter();
 319 }
 320
 321 static void hpet_enable_legacy_int(void)
 322 {
 323         unsigned int cfg = hpet_readl(HPET_CFG);
 324
 325         cfg |= HPET_CFG_LEGACY;
 326         hpet_writel(cfg, HPET_CFG);
 327         hpet_legacy_int_enabled = 1;
 328 }
 329
 330 static int timer0_use_64_bits(void)
 331 {
 332 #ifndef CONFIG_X86_64
 333         /* using the HPET in 64-bit mode without atomic 64-bit
 334          * accesses is too inefficient
 335          */
 336         return 0;
 337 #else
 338
 339         if (unlikely(hpet64)) {
 340                 u32 id, t0_cfg;
 341                 id = hpet_readl(HPET_ID);
 342                 t0_cfg = hpet_readl(HPET_Tn_CFG(0));
 343
 344                 if ((id & HPET_ID_64BIT) && (t0_cfg & HPET_TN_64BIT_CAP)) {
 345                         printk(KERN_DEBUG "hpet timer0 configured in 64-bit mode\n");
 346                         return 1;
 347                 }
 348                 else {
 349                         printk(KERN_DEBUG "hpet timer0 does not support 64-bit mode\n");
 350                         return 0;
 351                 }
 352         }
 353         else return 0;
 354 #endif
 355 }
 356
 357 static void hpet_legacy_clockevent_register(void)
 358 {
 359         /* Start HPET legacy interrupts */
 360         hpet_enable_legacy_int();
 361         hpet_legacy_use_64_bits = timer0_use_64_bits();
 362
 363         /*
 364          * Start hpet with the boot cpu mask and make it
 365          * global after the IO_APIC has been initialized.
 366          */
 367         hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
 368         clockevents_config_and_register(&hpet_clockevent, hpet_freq,
 369                                         HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
 370         global_clock_event = &hpet_clockevent;
 371         printk(KERN_DEBUG "hpet clockevent registered\n");
 372 }
 373
 374 static int hpet_setup_msi_irq(unsigned int irq);
 375
 376 static void hpet_set_mode(enum clock_event_mode mode,
 377                           struct clock_event_device *evt, int timer)
 378 {
 379         unsigned int cfg, cmp, now;
 380         uint64_t delta;
 381
 382         switch (mode) {
 383         case CLOCK_EVT_MODE_PERIODIC:
 384                 hpet_stop_counter();
 385                 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
 386                 delta >>= evt->shift;
 387                 now = hpet_readl(HPET_COUNTER);
 388                 cmp = now + (unsigned int) delta;
 389                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 390                 /* Make sure we use edge triggered interrupts */
 391                 cfg &= ~HPET_TN_LEVEL;
 392                 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
 393                        HPET_TN_SETVAL |
 394                        (hpet_legacy_use_64_bits ? 0 : HPET_TN_32BIT);
 395                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 396                 hpet_write_value(cmp, HPET_Tn_CMP(timer));
 397                 udelay(1);
 398                 /*
 399                  * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
 400                  * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
 401                  * bit is automatically cleared after the first write.
 402                  * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
 403                  * Publication # 24674)
 404                  */
 405                 hpet_write_value((unsigned long) delta, HPET_Tn_CMP(timer));
 406                 hpet_start_counter();
 407                 hpet_print_config();
 408                 break;
 409
 410         case CLOCK_EVT_MODE_ONESHOT:
 411                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 412                 cfg &= ~HPET_TN_PERIODIC;
 413                 cfg |= HPET_TN_ENABLE |
 414                        (hpet_legacy_use_64_bits ? 0 : HPET_TN_32BIT);
 415                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 416                 break;
 417
 418         case CLOCK_EVT_MODE_UNUSED:
 419         case CLOCK_EVT_MODE_SHUTDOWN:
 420                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 421                 cfg &= ~HPET_TN_ENABLE;
 422                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 423                 break;
 424
 425         case CLOCK_EVT_MODE_RESUME:
 426                 if (timer == 0) {
 427                         hpet_enable_legacy_int();
 428                 } else {
 429                         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 430                         hpet_setup_msi_irq(hdev->irq);
 431                         disable_irq(hdev->irq);
 432                         irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
 433                         enable_irq(hdev->irq);
 434                 }
 435                 hpet_print_config();
 436                 break;
 437         }
 438 }
 439
 440 static int hpet_next_event(unsigned long delta,
 441                            struct clock_event_device *evt, int timer)
 442 {
 443         unsigned long cnt;
 444         s32 res;
 445
 446         cnt = hpet_read_value(HPET_COUNTER);
 447         cnt += (u32) delta;
 448         hpet_write_value(cnt, HPET_Tn_CMP(timer));
 449
 450         /*
 451          * HPETs are a complete disaster. The compare register is
 452          * based on a equal comparison and neither provides a less
 453          * than or equal functionality (which would require to take
 454          * the wraparound into account) nor a simple count down event
 455          * mode. Further the write to the comparator register is
 456          * delayed internally up to two HPET clock cycles in certain
 457          * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
 458          * longer delays. We worked around that by reading back the
 459          * compare register, but that required another workaround for
 460          * ICH9,10 chips where the first readout after write can
 461          * return the old stale value. We already had a minimum
 462          * programming delta of 5us enforced, but a NMI or SMI hitting
 463          * between the counter readout and the comparator write can
 464          * move us behind that point easily. Now instead of reading
 465          * the compare register back several times, we make the ETIME
 466          * decision based on the following: Return ETIME if the
 467          * counter value after the write is less than HPET_MIN_CYCLES
 468          * away from the event or if the counter is already ahead of
 469          * the event. The minimum programming delta for the generic
 470          * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
 471          */
 472         res = (s32)((u32)cnt - (u32)hpet_readl(HPET_COUNTER));
 473
 474         return res < HPET_MIN_CYCLES ? -ETIME : 0;
 475 }
 476
 477 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 478                         struct clock_event_device *evt)
 479 {
 480         hpet_set_mode(mode, evt, 0);
 481 }
 482
 483 static int hpet_legacy_next_event(unsigned long delta,
 484                         struct clock_event_device *evt)
 485 {
 486         return hpet_next_event(delta, evt, 0);
 487 }
 488
 489 /*
 490  * HPET MSI Support
 491  */
 492 #ifdef CONFIG_PCI_MSI
 493
 494 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
 495 static struct hpet_dev  *hpet_devs;
 496
 497 void hpet_msi_unmask(struct irq_data *data)
 498 {
 499         struct hpet_dev *hdev = data->handler_data;
 500         unsigned int cfg;
 501
 502         /* unmask it */
 503         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 504         cfg |= HPET_TN_FSB;
 505         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 506 }
 507
 508 void hpet_msi_mask(struct irq_data *data)
 509 {
 510         struct hpet_dev *hdev = data->handler_data;
 511         unsigned int cfg;
 512
 513         /* mask it */
 514         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 515         cfg &= ~HPET_TN_FSB;
 516         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 517 }
 518
 519 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
 520 {
 521         hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
 522         hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
 523 }
 524
 525 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
 526 {
 527         msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
 528         msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
 529         msg->address_hi = 0;
 530 }
 531
 532 static void hpet_msi_set_mode(enum clock_event_mode mode,
 533                                 struct clock_event_device *evt)
 534 {
 535         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 536         hpet_set_mode(mode, evt, hdev->num);
 537 }
 538
 539 static int hpet_msi_next_event(unsigned long delta,
 540                                 struct clock_event_device *evt)
 541 {
 542         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 543         return hpet_next_event(delta, evt, hdev->num);
 544 }
 545
 546 static int hpet_setup_msi_irq(unsigned int irq)
 547 {
 548         if (arch_setup_hpet_msi(irq, hpet_blockid)) {
 549                 destroy_irq(irq);
 550                 return -EINVAL;
 551         }
 552         return 0;
 553 }
 554
 555 static int hpet_assign_irq(struct hpet_dev *dev)
 556 {
 557         unsigned int irq;
 558
 559         irq = create_irq_nr(0, -1);
 560         if (!irq)
 561                 return -EINVAL;
 562
 563         irq_set_handler_data(irq, dev);
 564
 565         if (hpet_setup_msi_irq(irq))
 566                 return -EINVAL;
 567
 568         dev->irq = irq;
 569         return 0;
 570 }
 571
 572 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
 573 {
 574         struct hpet_dev *dev = (struct hpet_dev *)data;
 575         struct clock_event_device *hevt = &dev->evt;
 576
 577         if (!hevt->event_handler) {
 578                 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
 579                                 dev->num);
 580                 return IRQ_HANDLED;
 581         }
 582
 583         hevt->event_handler(hevt);
 584         return IRQ_HANDLED;
 585 }
 586
 587 static int hpet_setup_irq(struct hpet_dev *dev)
 588 {
 589
 590         if (request_irq(dev->irq, hpet_interrupt_handler,
 591                         IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
 592                         dev->name, dev))
 593                 return -1;
 594
 595         disable_irq(dev->irq);
 596         irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
 597         enable_irq(dev->irq);
 598
 599         printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
 600                          dev->name, dev->irq);
 601
 602         return 0;
 603 }
 604
 605 /* This should be called in specific @cpu */
 606 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
 607 {
 608         struct clock_event_device *evt = &hdev->evt;
 609
 610         WARN_ON(cpu != smp_processor_id());
 611         if (!(hdev->flags & HPET_DEV_VALID))
 612                 return;
 613
 614         if (hpet_setup_msi_irq(hdev->irq))
 615                 return;
 616
 617         hdev->cpu = cpu;
 618         per_cpu(cpu_hpet_dev, cpu) = hdev;
 619         evt->name = hdev->name;
 620         hpet_setup_irq(hdev);
 621         evt->irq = hdev->irq;
 622
 623         evt->rating = 110;
 624         evt->features = CLOCK_EVT_FEAT_ONESHOT;
 625         if (hdev->flags & HPET_DEV_PERI_CAP)
 626                 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
 627
 628         evt->set_mode = hpet_msi_set_mode;
 629         evt->set_next_event = hpet_msi_next_event;
 630         evt->cpumask = cpumask_of(hdev->cpu);
 631
 632         clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
 633                                         0x7FFFFFFF);
 634 }
 635
 636 #ifdef CONFIG_HPET
 637 /* Reserve at least one timer for userspace (/dev/hpet) */
 638 #define RESERVE_TIMERS 1
 639 #else
 640 #define RESERVE_TIMERS 0
 641 #endif
 642
 643 static void hpet_msi_capability_lookup(unsigned int start_timer)
 644 {
 645         unsigned int id;
 646         unsigned int num_timers;
 647         unsigned int num_timers_used = 0;
 648         int i;
 649
 650         if (hpet_msi_disable)
 651                 return;
 652
 653         if (boot_cpu_has(X86_FEATURE_ARAT))
 654                 return;
 655         id = hpet_readl(HPET_ID);
 656
 657         num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
 658         num_timers++; /* Value read out starts from 0 */
 659         hpet_print_config();
 660
 661         hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
 662         if (!hpet_devs)
 663                 return;
 664
 665         hpet_num_timers = num_timers;
 666
 667         for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
 668                 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
 669                 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
 670
 671                 /* Only consider HPET timer with MSI support */
 672                 if (!(cfg & HPET_TN_FSB_CAP))
 673                         continue;
 674
 675                 hdev->flags = 0;
 676                 if (cfg & HPET_TN_PERIODIC_CAP)
 677                         hdev->flags |= HPET_DEV_PERI_CAP;
 678                 hdev->num = i;
 679
 680                 sprintf(hdev->name, "hpet%d", i);
 681                 if (hpet_assign_irq(hdev))
 682                         continue;
 683
 684                 hdev->flags |= HPET_DEV_FSB_CAP;
 685                 hdev->flags |= HPET_DEV_VALID;
 686                 num_timers_used++;
 687                 if (num_timers_used == num_possible_cpus())
 688                         break;
 689         }
 690
 691         printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
 692                 num_timers, num_timers_used);
 693 }
 694
 695 #ifdef CONFIG_HPET
 696 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 697 {
 698         int i;
 699
 700         if (!hpet_devs)
 701                 return;
 702
 703         for (i = 0; i < hpet_num_timers; i++) {
 704                 struct hpet_dev *hdev = &hpet_devs[i];
 705
 706                 if (!(hdev->flags & HPET_DEV_VALID))
 707                         continue;
 708
 709                 hd->hd_irq[hdev->num] = hdev->irq;
 710                 hpet_reserve_timer(hd, hdev->num);
 711         }
 712 }
 713 #endif
 714
 715 static struct hpet_dev *hpet_get_unused_timer(void)
 716 {
 717         int i;
 718
 719         if (!hpet_devs)
 720                 return NULL;
 721
 722         for (i = 0; i < hpet_num_timers; i++) {
 723                 struct hpet_dev *hdev = &hpet_devs[i];
 724
 725                 if (!(hdev->flags & HPET_DEV_VALID))
 726                         continue;
 727                 if (test_and_set_bit(HPET_DEV_USED_BIT,
 728                         (unsigned long *)&hdev->flags))
 729                         continue;
 730                 return hdev;
 731         }
 732         return NULL;
 733 }
 734
 735 struct hpet_work_struct {
 736         struct delayed_work work;
 737         struct completion complete;
 738 };
 739
 740 static void hpet_work(struct work_struct *w)
 741 {
 742         struct hpet_dev *hdev;
 743         int cpu = smp_processor_id();
 744         struct hpet_work_struct *hpet_work;
 745
 746         hpet_work = container_of(w, struct hpet_work_struct, work.work);
 747
 748         hdev = hpet_get_unused_timer();
 749         if (hdev)
 750                 init_one_hpet_msi_clockevent(hdev, cpu);
 751
 752         complete(&hpet_work->complete);
 753 }
 754
 755 static int hpet_cpuhp_notify(struct notifier_block *n,
 756                 unsigned long action, void *hcpu)
 757 {
 758         unsigned long cpu = (unsigned long)hcpu;
 759         struct hpet_work_struct work;
 760         struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
 761
 762         switch (action & 0xf) {
 763         case CPU_ONLINE:
 764                 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
 765                 init_completion(&work.complete);
 766                 /* FIXME: add schedule_work_on() */
 767                 schedule_delayed_work_on(cpu, &work.work, 0);
 768                 wait_for_completion(&work.complete);
 769                 destroy_timer_on_stack(&work.work.timer);
 770                 break;
 771         case CPU_DEAD:
 772                 if (hdev) {
 773                         free_irq(hdev->irq, hdev);
 774                         hdev->flags &= ~HPET_DEV_USED;
 775                         per_cpu(cpu_hpet_dev, cpu) = NULL;
 776                 }
 777                 break;
 778         }
 779         return NOTIFY_OK;
 780 }
 781 #else
 782
 783 static int hpet_setup_msi_irq(unsigned int irq)
 784 {
 785         return 0;
 786 }
 787 static void hpet_msi_capability_lookup(unsigned int start_timer)
 788 {
 789         return;
 790 }
 791
 792 #ifdef CONFIG_HPET
 793 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 794 {
 795         return;
 796 }
 797 #endif
 798
 799 static int hpet_cpuhp_notify(struct notifier_block *n,
 800                 unsigned long action, void *hcpu)
 801 {
 802         return NOTIFY_OK;
 803 }
 804
 805 #endif
 806
 807 /*
 808  * Clock source related code
 809  */
 810 static cycle_t read_hpet(struct clocksource *cs)
 811 {
 812         return (cycle_t)hpet_readl(HPET_COUNTER);
 813 }
 814
 815 static struct clocksource clocksource_hpet = {
 816         .name           = "hpet",
 817         .rating         = 250,
 818         .read           = read_hpet,
 819         .mask           = HPET_MASK,
 820         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 821         .resume         = hpet_resume_counter,
 822 #ifdef CONFIG_X86_64
 823         .archdata       = { .vclock_mode = VCLOCK_HPET },
 824 #endif
 825 };
 826
 827 static int hpet_clocksource_register(void)
 828 {
 829         u64 start, now;
 830         cycle_t t1;
 831
 832         /* Start the counter */
 833         hpet_restart_counter();
 834
 835         /* Verify whether hpet counter works */
 836         t1 = hpet_readl(HPET_COUNTER);
 837         rdtscll(start);
 838
 839         /*
 840          * We don't know the TSC frequency yet, but waiting for
 841          * 200000 TSC cycles is safe:
 842          * 4 GHz == 50us
 843          * 1 GHz == 200us
 844          */
 845         do {
 846                 rep_nop();
 847                 rdtscll(now);
 848         } while ((now - start) < 200000UL);
 849
 850         if (t1 == hpet_readl(HPET_COUNTER)) {
 851                 printk(KERN_WARNING
 852                        "HPET counter not counting. HPET disabled\n");
 853                 return -ENODEV;
 854         }
 855
 856         clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
 857         return 0;
 858 }
 859
 860 /**
 861  * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
 862  */
 863 int __init hpet_enable(void)
 864 {
 865         unsigned long hpet_period;
 866         unsigned int id;
 867         u64 freq;
 868         int i;
 869
 870         if (!is_hpet_capable())
 871                 return 0;
 872
 873         hpet_set_mapping();
 874
 875         /*
 876          * Read the period and check for a sane value:
 877          */
 878         hpet_period = hpet_readl(HPET_PERIOD);
 879
 880         /*
 881          * AMD SB700 based systems with spread spectrum enabled use a
 882          * SMM based HPET emulation to provide proper frequency
 883          * setting. The SMM code is initialized with the first HPET
 884          * register access and takes some time to complete. During
 885          * this time the config register reads 0xffffffff. We check
 886          * for max. 1000 loops whether the config register reads a non
 887          * 0xffffffff value to make sure that HPET is up and running
 888          * before we go further. A counting loop is safe, as the HPET
 889          * access takes thousands of CPU cycles. On non SB700 based
 890          * machines this check is only done once and has no side
 891          * effects.
 892          */
 893         for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
 894                 if (i == 1000) {
 895                         printk(KERN_WARNING
 896                                "HPET config register value = 0xFFFFFFFF. "
 897                                "Disabling HPET\n");
 898                         goto out_nohpet;
 899                 }
 900         }
 901
 902         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
 903                 goto out_nohpet;
 904
 905         /*
 906          * The period is a femto seconds value. Convert it to a
 907          * frequency.
 908          */
 909         freq = FSEC_PER_SEC;
 910         do_div(freq, hpet_period);
 911         hpet_freq = freq;
 912
 913         /*
 914          * Read the HPET ID register to retrieve the IRQ routing
 915          * information and the number of channels
 916          */
 917         id = hpet_readl(HPET_ID);
 918         hpet_print_config();
 919
 920 #ifdef CONFIG_HPET_EMULATE_RTC
 921         /*
 922          * The legacy routing mode needs at least two channels, tick timer
 923          * and the rtc emulation channel.
 924          */
 925         if (!(id & HPET_ID_NUMBER))
 926                 goto out_nohpet;
 927 #endif
 928
 929         if (hpet_clocksource_register())
 930                 goto out_nohpet;
 931
 932         if (id & HPET_ID_LEGSUP) {
 933                 hpet_legacy_clockevent_register();
 934                 return 1;
 935         }
 936         return 0;
 937
 938 out_nohpet:
 939         hpet_clear_mapping();
 940         hpet_address = 0;
 941         return 0;
 942 }
 943
 944 /*
 945  * Needs to be late, as the reserve_timer code calls kalloc !
 946  *
 947  * Not a problem on i386 as hpet_enable is called from late_time_init,
 948  * but on x86_64 it is necessary !
 949  */
 950 static __init int hpet_late_init(void)
 951 {
 952         int cpu;
 953
 954         if (boot_hpet_disable)
 955                 return -ENODEV;
 956
 957         if (!hpet_address) {
 958                 if (!force_hpet_address)
 959                         return -ENODEV;
 960
 961                 hpet_address = force_hpet_address;
 962                 hpet_enable();
 963         }
 964
 965         if (!hpet_virt_address)
 966                 return -ENODEV;
 967
 968         if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
 969                 hpet_msi_capability_lookup(2);
 970         else
 971                 hpet_msi_capability_lookup(0);
 972
 973         hpet_reserve_platform_timers(hpet_readl(HPET_ID));
 974         hpet_print_config();
 975
 976         if (hpet_msi_disable)
 977                 return 0;
 978
 979         if (boot_cpu_has(X86_FEATURE_ARAT))
 980                 return 0;
 981
 982         for_each_online_cpu(cpu) {
 983                 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
 984         }
 985
 986         /* This notifier should be called after workqueue is ready */
 987         hotcpu_notifier(hpet_cpuhp_notify, -20);
 988
 989         return 0;
 990 }
 991 fs_initcall(hpet_late_init);
 992
 993 void hpet_disable(void)
 994 {
 995         if (is_hpet_capable() && hpet_virt_address) {
 996                 unsigned int cfg = hpet_readl(HPET_CFG);
 997
 998                 if (hpet_legacy_int_enabled) {
 999                         cfg &= ~HPET_CFG_LEGACY;
1000                         hpet_legacy_int_enabled = 0;
1001                 }
1002                 cfg &= ~HPET_CFG_ENABLE;
1003                 hpet_writel(cfg, HPET_CFG);
1004         }
1005 }
1006
1007 #ifdef CONFIG_HPET_EMULATE_RTC
1008
1009 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
1010  * is enabled, we support RTC interrupt functionality in software.
1011  * RTC has 3 kinds of interrupts:
1012  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
1013  *    is updated
1014  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1015  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1016  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
1017  * (1) and (2) above are implemented using polling at a frequency of
1018  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
1019  * overhead. (DEFAULT_RTC_INT_FREQ)
1020  * For (3), we use interrupts at 64Hz or user specified periodic
1021  * frequency, whichever is higher.
1022  */
1023 #include <linux/mc146818rtc.h>
1024 #include <linux/rtc.h>
1025 #include <asm/rtc.h>
1026
1027 #define DEFAULT_RTC_INT_FREQ    64
1028 #define DEFAULT_RTC_SHIFT       6
1029 #define RTC_NUM_INTS            1
1030
1031 static unsigned long hpet_rtc_flags;
1032 static int hpet_prev_update_sec;
1033 static struct rtc_time hpet_alarm_time;
1034 static unsigned long hpet_pie_count;
1035 static u32 hpet_t1_cmp;
1036 static u32 hpet_default_delta;
1037 static u32 hpet_pie_delta;
1038 static unsigned long hpet_pie_limit;
1039
1040 static rtc_irq_handler irq_handler;
1041
1042 /*
1043  * Check that the hpet counter c1 is ahead of the c2
1044  */
1045 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1046 {
1047         return (s32)(c2 - c1) < 0;
1048 }
1049
1050 /*
1051  * Registers a IRQ handler.
1052  */
1053 int hpet_register_irq_handler(rtc_irq_handler handler)
1054 {
1055         if (!is_hpet_enabled())
1056                 return -ENODEV;
1057         if (irq_handler)
1058                 return -EBUSY;
1059
1060         irq_handler = handler;
1061
1062         return 0;
1063 }
1064 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1065
1066 /*
1067  * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1068  * and does cleanup.
1069  */
1070 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1071 {
1072         if (!is_hpet_enabled())
1073                 return;
1074
1075         irq_handler = NULL;
1076         hpet_rtc_flags = 0;
1077 }
1078 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1079
1080 /*
1081  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1082  * is not supported by all HPET implementations for timer 1.
1083  *
1084  * hpet_rtc_timer_init() is called when the rtc is initialized.
1085  */
1086 int hpet_rtc_timer_init(void)
1087 {
1088         unsigned int cfg, cnt, delta;
1089         unsigned long flags;
1090
1091         if (!is_hpet_enabled())
1092                 return 0;
1093
1094         if (!hpet_default_delta) {
1095                 uint64_t clc;
1096
1097                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1098                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1099                 hpet_default_delta = clc;
1100         }
1101
1102         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1103                 delta = hpet_default_delta;
1104         else
1105                 delta = hpet_pie_delta;
1106
1107         local_irq_save(flags);
1108
1109         cnt = delta + hpet_readl(HPET_COUNTER);
1110         hpet_writel(cnt, HPET_T1_CMP);
1111         hpet_t1_cmp = cnt;
1112
1113         cfg = hpet_readl(HPET_T1_CFG);
1114         cfg &= ~HPET_TN_PERIODIC;
1115         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1116         hpet_writel(cfg, HPET_T1_CFG);
1117
1118         local_irq_restore(flags);
1119
1120         return 1;
1121 }
1122 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1123
1124 static void hpet_disable_rtc_channel(void)
1125 {
1126         unsigned long cfg;
1127         cfg = hpet_readl(HPET_T1_CFG);
1128         cfg &= ~HPET_TN_ENABLE;
1129         hpet_writel(cfg, HPET_T1_CFG);
1130 }
1131
1132 /*
1133  * The functions below are called from rtc driver.
1134  * Return 0 if HPET is not being used.
1135  * Otherwise do the necessary changes and return 1.
1136  */
1137 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1138 {
1139         if (!is_hpet_enabled())
1140                 return 0;
1141
1142         hpet_rtc_flags &= ~bit_mask;
1143         if (unlikely(!hpet_rtc_flags))
1144                 hpet_disable_rtc_channel();
1145
1146         return 1;
1147 }
1148 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1149
1150 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1151 {
1152         unsigned long oldbits = hpet_rtc_flags;
1153
1154         if (!is_hpet_enabled())
1155                 return 0;
1156
1157         hpet_rtc_flags |= bit_mask;
1158
1159         if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1160                 hpet_prev_update_sec = -1;
1161
1162         if (!oldbits)
1163                 hpet_rtc_timer_init();
1164
1165         return 1;
1166 }
1167 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1168
1169 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1170                         unsigned char sec)
1171 {
1172         if (!is_hpet_enabled())
1173                 return 0;
1174
1175         hpet_alarm_time.tm_hour = hrs;
1176         hpet_alarm_time.tm_min = min;
1177         hpet_alarm_time.tm_sec = sec;
1178
1179         return 1;
1180 }
1181 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1182
1183 int hpet_set_periodic_freq(unsigned long freq)
1184 {
1185         uint64_t clc;
1186
1187         if (!is_hpet_enabled())
1188                 return 0;
1189
1190         if (freq <= DEFAULT_RTC_INT_FREQ)
1191                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1192         else {
1193                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1194                 do_div(clc, freq);
1195                 clc >>= hpet_clockevent.shift;
1196                 hpet_pie_delta = clc;
1197                 hpet_pie_limit = 0;
1198         }
1199         return 1;
1200 }
1201 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1202
1203 int hpet_rtc_dropped_irq(void)
1204 {
1205         return is_hpet_enabled();
1206 }
1207 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1208
1209 static void hpet_rtc_timer_reinit(void)
1210 {
1211         unsigned int delta;
1212         int lost_ints = -1;
1213
1214         if (unlikely(!hpet_rtc_flags))
1215                 hpet_disable_rtc_channel();
1216
1217         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1218                 delta = hpet_default_delta;
1219         else
1220                 delta = hpet_pie_delta;
1221
1222         /*
1223          * Increment the comparator value until we are ahead of the
1224          * current count.
1225          */
1226         do {
1227                 hpet_t1_cmp += delta;
1228                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1229                 lost_ints++;
1230         } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1231
1232         if (lost_ints) {
1233                 if (hpet_rtc_flags & RTC_PIE)
1234                         hpet_pie_count += lost_ints;
1235                 if (printk_ratelimit())
1236                         printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1237                                 lost_ints);
1238         }
1239 }
1240
1241 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1242 {
1243         struct rtc_time curr_time;
1244         unsigned long rtc_int_flag = 0;
1245
1246         hpet_rtc_timer_reinit();
1247         memset(&curr_time, 0, sizeof(struct rtc_time));
1248
1249         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1250                 get_rtc_time(&curr_time);
1251
1252         if (hpet_rtc_flags & RTC_UIE &&
1253             curr_time.tm_sec != hpet_prev_update_sec) {
1254                 if (hpet_prev_update_sec >= 0)
1255                         rtc_int_flag = RTC_UF;
1256                 hpet_prev_update_sec = curr_time.tm_sec;
1257         }
1258
1259         if (hpet_rtc_flags & RTC_PIE &&
1260             ++hpet_pie_count >= hpet_pie_limit) {
1261                 rtc_int_flag |= RTC_PF;
1262                 hpet_pie_count = 0;
1263         }
1264
1265         if (hpet_rtc_flags & RTC_AIE &&
1266             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1267             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1268             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1269                         rtc_int_flag |= RTC_AF;
1270
1271         if (rtc_int_flag) {
1272                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1273                 if (irq_handler)
1274                         irq_handler(rtc_int_flag, dev_id);
1275         }
1276         return IRQ_HANDLED;
1277 }
1278 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1279 #endif