1 #ifndef _ASM_X86_PGTABLE_3LEVEL_H
2 #define _ASM_X86_PGTABLE_3LEVEL_H
5 * Intel Physical Address Extension (PAE) Mode - three-level page
6 * tables on PPro+ CPUs.
8 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
11 #define pte_ERROR(e) \
12 printk("%s:%d: bad pte %p(%016Lx pfn %08lx).\n", \
13 __FILE__, __LINE__, &(e), __pte_val(e), pte_pfn(e))
14 #define pmd_ERROR(e) \
15 printk("%s:%d: bad pmd %p(%016Lx pfn %08Lx).\n", \
16 __FILE__, __LINE__, &(e), __pmd_val(e), \
17 (pmd_val(e) & PTE_PFN_MASK) >> PAGE_SHIFT)
18 #define pgd_ERROR(e) \
19 printk("%s:%d: bad pgd %p(%016Lx pfn %08Lx).\n", \
20 __FILE__, __LINE__, &(e), __pgd_val(e), \
21 (pgd_val(e) & PTE_PFN_MASK) >> PAGE_SHIFT)
23 /* Rules for using set_pte: the pte being assigned *must* be
24 * either not present or in a state where the hardware will
25 * not attempt to update the pte. In places where this is
26 * not possible, use pte_get_and_clear to obtain the old pte
27 * value and then use set_pte to update it. -ben
30 static inline void xen_set_pte(pte_t *ptep, pte_t pte)
32 ptep->pte_high = pte.pte_high;
34 ptep->pte_low = pte.pte_low;
37 static inline void xen_set_pmd(pmd_t *pmdp, pmd_t pmd)
39 xen_l2_entry_update(pmdp, pmd);
42 static inline void xen_set_pud(pud_t *pudp, pud_t pud)
44 xen_l3_entry_update(pudp, pud);
48 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
49 * entry, so clear the bottom half first and enforce ordering with a compiler
52 static inline void __xen_pte_clear(pte_t *ptep)
59 #define xen_pmd_clear(pmd) \
61 pmd_t *__pmdp = (pmd); \
62 PagePinned(virt_to_page(__pmdp)) \
63 ? set_pmd(__pmdp, __pmd(0)) \
64 : (void)(*__pmdp = __pmd(0)); \
67 static inline void __xen_pud_clear(pud_t *pudp)
69 set_pud(pudp, __pud(0));
72 * According to Intel App note "TLBs, Paging-Structure Caches,
73 * and Their Invalidation", April 2007, document 317080-001,
74 * section 8.1: in PAE mode we explicitly have to flush the
75 * TLB via cr3 if the top-level pgd is changed...
77 * Currently all places where pud_clear() is called either have
78 * flush_tlb_mm() followed or don't need TLB flush (x86_64 code or
79 * pud_clear_bad()), so we don't need TLB flush here.
83 #define xen_pud_clear(pudp) \
85 pud_t *__pudp = (pudp); \
86 PagePinned(virt_to_page(__pudp)) \
87 ? __xen_pud_clear(__pudp) \
88 : (void)(*__pudp = __pud(0)); \
92 static inline pte_t xen_ptep_get_and_clear(pte_t *ptep, pte_t res)
94 uint64_t val = __pte_val(res);
95 if (__cmpxchg64(&ptep->pte, val, 0) != val) {
96 /* xchg acts as a barrier before the setting of the high bits */
97 res.pte_low = xchg(&ptep->pte_low, 0);
98 res.pte_high = ptep->pte_high;
104 #define xen_ptep_get_and_clear(xp, pte) xen_local_ptep_get_and_clear(xp, pte)
107 #define __pte_mfn(_pte) (((_pte).pte_low >> PAGE_SHIFT) | \
108 ((_pte).pte_high << (32-PAGE_SHIFT)))
110 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
119 static inline pmd_t xen_pmdp_get_and_clear(pmd_t *pmdp)
121 union split_pmd res, *orig = (union split_pmd *)pmdp;
123 /* xchg acts as a barrier before setting of the high bits */
124 res.pmd_low = xchg(&orig->pmd_low, 0);
125 res.pmd_high = orig->pmd_high;
131 #define xen_pmdp_get_and_clear(xp) xen_local_pmdp_get_and_clear(xp)
136 * Bits 0, 6 and 7 are taken in the low part of the pte,
137 * put the 32 bits of offset into the high part.
139 #define pte_to_pgoff(pte) ((pte).pte_high)
140 #define pgoff_to_pte(off) \
141 ((pte_t) { { .pte_low = _PAGE_FILE, .pte_high = (off) } })
142 #define PTE_FILE_MAX_BITS 32
144 /* Encode and de-code a swap entry */
145 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5)
146 #define __swp_type(x) (((x).val) & 0x1f)
147 #define __swp_offset(x) ((x).val >> 5)
148 #define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5})
149 #define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
150 #define __swp_entry_to_pte(x) ((pte_t){ { .pte_high = (x).val } })
152 #endif /* _ASM_X86_PGTABLE_3LEVEL_H */