2 * arch/ia64/kernel/ivt.S
4 * Copyright (C) 1998-2001 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger <davidm@hpl.hp.com>
8 * 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling for SMP
9 * 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now uses virtual PT.
12 * This file defines the interruption vector table used by the CPU.
13 * It does not include one entry per possible cause of interruption.
15 * The first 20 entries of the table contain 64 bundles each while the
16 * remaining 48 entries contain only 16 bundles each.
18 * The 64 bundles are used to allow inlining the whole handler for critical
19 * interruptions like TLB misses.
21 * For each entry, the comment is as follows:
23 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
24 * entry offset ----/ / / / /
25 * entry number ---------/ / / /
26 * size of the entry -------------/ / /
27 * vector name -------------------------------------/ /
28 * interruptions triggering this vector ----------------------/
30 * The table is 32KB in size and must be aligned on 32KB boundary.
31 * (The CPU ignores the 15 lower bits of the address)
33 * Table is based upon EAS2.6 (Oct 1999)
36 #include <linux/config.h>
38 #include <asm/asmmacro.h>
39 #include <asm/break.h>
40 #include <asm/kregs.h>
41 #include <asm/offsets.h>
42 #include <asm/pgtable.h>
43 #include <asm/processor.h>
44 #include <asm/ptrace.h>
45 #include <asm/system.h>
46 #include <asm/thread_info.h>
47 #include <asm/unistd.h>
50 # define PSR_DEFAULT_BITS psr.ac
52 # define PSR_DEFAULT_BITS 0
57 * This lets you track the last eight faults that occurred on the CPU. Make sure ar.k2 isn't
58 * needed for something else before enabling this...
60 # define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16
65 #define MINSTATE_VIRT /* needed by minstate.h */
70 mov r19=n;; /* prepare to save predicates */ \
71 br.sptk.many dispatch_to_fault_handler
73 .section .text.ivt,"ax"
75 .align 32768 // align on 32KB boundary
78 /////////////////////////////////////////////////////////////////////////////////////////
79 // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
83 * The VHPT vector is invoked when the TLB entry for the virtual page table
84 * is missing. This happens only as a result of a previous
85 * (the "original") TLB miss, which may either be caused by an instruction
86 * fetch or a data access (or non-access).
88 * What we do here is normal TLB miss handing for the _original_ miss, followed
89 * by inserting the TLB entry for the virtual page table page that the VHPT
90 * walker was attempting to access. The latter gets inserted as long
91 * as both L1 and L2 have valid mappings for the faulting address.
92 * The TLB entry for the original miss gets inserted only if
93 * the L3 entry indicates that the page is present.
95 * do_page_fault gets invoked in the following cases:
96 * - the faulting virtual address uses unimplemented address bits
97 * - the faulting virtual address has no L1, L2, or L3 mapping
99 mov r16=cr.ifa // get address that caused the TLB miss
100 #ifdef CONFIG_HUGETLB_PAGE
105 rsm psr.dt // use physical addressing for data
106 mov r31=pr // save the predicate registers
107 mov r19=IA64_KR(PT_BASE) // get page table base address
108 shl r21=r16,3 // shift bit 60 into sign bit
109 shr.u r17=r16,61 // get the region number into r17
112 #ifdef CONFIG_HUGETLB_PAGE
115 cmp.eq p8,p0=HPAGE_SHIFT,r26
117 (p8) dep r25=r18,r25,2,6
118 (p8) shr r22=r22,HPAGE_SHIFT-PAGE_SHIFT
121 cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5?
122 shr.u r18=r22,PGDIR_SHIFT // get bits 33-63 of the faulting address
124 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
125 srlz.d // ensure "rsm psr.dt" has taken effect
126 (p6) movl r19=__pa(swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
127 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
128 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
130 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
131 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
132 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
133 shr.u r18=r22,PMD_SHIFT // shift L2 index into position
135 ld8 r17=[r17] // fetch the L1 entry (may be 0)
137 (p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
138 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
140 (p7) ld8 r20=[r17] // fetch the L2 entry (may be 0)
141 shr.u r19=r22,PAGE_SHIFT // shift L3 index into position
143 (p7) cmp.eq.or.andcm p6,p7=r20,r0 // was L2 entry NULL?
144 dep r21=r19,r20,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
146 (p7) ld8 r18=[r21] // read the L3 PTE
147 mov r19=cr.isr // cr.isr bit 0 tells us if this is an insn miss
149 (p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
150 mov r22=cr.iha // get the VHPT address that caused the TLB miss
151 ;; // avoid RAW on p7
152 (p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss?
153 dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address
155 (p10) itc.i r18 // insert the instruction TLB entry
156 (p11) itc.d r18 // insert the data TLB entry
157 (p6) br.cond.spnt.many page_fault // handle bad address/page not present (page fault)
160 #ifdef CONFIG_HUGETLB_PAGE
161 (p8) mov cr.itir=r25 // change to default page-size for VHPT
165 * Now compute and insert the TLB entry for the virtual page table. We never
166 * execute in a page table page so there is no need to set the exception deferral
169 adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23
175 * Re-check L2 and L3 pagetable. If they changed, we may have received a ptc.g
176 * between reading the pagetable and the "itc". If so, flush the entry we
177 * inserted and retry.
179 ld8 r25=[r21] // read L3 PTE again
180 ld8 r26=[r17] // read L2 entry again
182 cmp.ne p6,p7=r26,r20 // did L2 entry change
183 mov r27=PAGE_SHIFT<<2
185 (p6) ptc.l r22,r27 // purge PTE page translation
186 (p7) cmp.ne.or.andcm p6,p7=r25,r18 // did L3 PTE change
188 (p6) ptc.l r16,r27 // purge translation
191 mov pr=r31,-1 // restore predicate registers
196 /////////////////////////////////////////////////////////////////////////////////////////
197 // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
201 * The ITLB handler accesses the L3 PTE via the virtually mapped linear
202 * page table. If a nested TLB miss occurs, we switch into physical
203 * mode, walk the page table, and then re-execute the L3 PTE read
204 * and go on normally after that.
206 mov r16=cr.ifa // get virtual address
207 mov r29=b0 // save b0
208 mov r31=pr // save predicates
210 mov r17=cr.iha // get virtual address of L3 PTE
211 movl r30=1f // load nested fault continuation point
213 1: ld8 r18=[r17] // read L3 PTE
216 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
217 (p6) br.cond.spnt page_fault
222 ld8 r19=[r17] // read L3 PTE again and see if same
223 mov r20=PAGE_SHIFT<<2 // setup page size for purge
234 /////////////////////////////////////////////////////////////////////////////////////////
235 // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
239 * The DTLB handler accesses the L3 PTE via the virtually mapped linear
240 * page table. If a nested TLB miss occurs, we switch into physical
241 * mode, walk the page table, and then re-execute the L3 PTE read
242 * and go on normally after that.
244 mov r16=cr.ifa // get virtual address
245 mov r29=b0 // save b0
246 mov r31=pr // save predicates
248 mov r17=cr.iha // get virtual address of L3 PTE
249 movl r30=1f // load nested fault continuation point
251 1: ld8 r18=[r17] // read L3 PTE
254 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
255 (p6) br.cond.spnt page_fault
260 ld8 r19=[r17] // read L3 PTE again and see if same
261 mov r20=PAGE_SHIFT<<2 // setup page size for purge
272 /////////////////////////////////////////////////////////////////////////////////////////
273 // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
276 mov r16=cr.ifa // get address that caused the TLB miss
279 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
282 #ifdef CONFIG_DISABLE_VHPT
283 shr.u r22=r16,61 // get the region number into r21
285 cmp.gt p8,p0=6,r22 // user mode
290 (p8) mov r29=b0 // save b0
291 (p8) br.cond.dptk .itlb_fault
293 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
294 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
295 shr.u r18=r16,57 // move address bit 61 to bit 4
297 andcm r18=0x10,r18 // bit 4=~address-bit(61)
298 cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
299 or r19=r17,r19 // insert PTE control bits into r19
301 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
302 (p8) br.cond.spnt page_fault
304 itc.i r19 // insert the TLB entry
310 /////////////////////////////////////////////////////////////////////////////////////////
311 // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
314 mov r16=cr.ifa // get address that caused the TLB miss
317 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
321 #ifdef CONFIG_DISABLE_VHPT
322 shr.u r22=r16,61 // get the region number into r21
324 cmp.gt p8,p0=6,r22 // access to region 0-5
329 (p8) mov r29=b0 // save b0
330 (p8) br.cond.dptk dtlb_fault
332 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
333 and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field
334 tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on?
335 shr.u r18=r16,57 // move address bit 61 to bit 4
336 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
337 tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on?
339 andcm r18=0x10,r18 // bit 4=~address-bit(61)
341 (p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
342 (p8) br.cond.spnt page_fault
344 dep r21=-1,r21,IA64_PSR_ED_BIT,1
345 or r19=r19,r17 // insert PTE control bits into r19
347 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
350 (p7) itc.d r19 // insert the TLB entry
355 //-----------------------------------------------------------------------------------
356 // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address)
363 alloc r15=ar.pfs,0,0,3,0
366 adds r3=8,r2 // set up second base pointer
368 ssm psr.ic | PSR_DEFAULT_BITS
370 srlz.i // guarantee that interruption collectin is on
372 (p15) ssm psr.i // restore psr.i
373 movl r14=ia64_leave_kernel
378 adds out2=16,r12 // out2 = pointer to pt_regs
379 br.call.sptk.many b6=ia64_do_page_fault // ignore return address
383 /////////////////////////////////////////////////////////////////////////////////////////
384 // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
385 ENTRY(nested_dtlb_miss)
387 * In the absence of kernel bugs, we get here when the virtually mapped linear
388 * page table is accessed non-speculatively (e.g., in the Dirty-bit, Instruction
389 * Access-bit, or Data Access-bit faults). If the DTLB entry for the virtual page
390 * table is missing, a nested TLB miss fault is triggered and control is
391 * transferred to this point. When this happens, we lookup the pte for the
392 * faulting address by walking the page table in physical mode and return to the
393 * continuation point passed in register r30 (or call page_fault if the address is
396 * Input: r16: faulting address
398 * r30: continuation address
401 * Output: r17: physical address of L3 PTE of faulting address
403 * r30: continuation address
406 * Clobbered: b0, r18, r19, r21, psr.dt (cleared)
408 rsm psr.dt // switch to using physical data addressing
409 mov r19=IA64_KR(PT_BASE) // get the page table base address
410 shl r21=r16,3 // shift bit 60 into sign bit
412 shr.u r17=r16,61 // get the region number into r17
414 cmp.eq p6,p7=5,r17 // is faulting address in region 5?
415 shr.u r18=r16,PGDIR_SHIFT // get bits 33-63 of faulting address
417 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
419 (p6) movl r19=__pa(swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
420 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
421 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
423 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
424 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
425 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
426 shr.u r18=r16,PMD_SHIFT // shift L2 index into position
428 ld8 r17=[r17] // fetch the L1 entry (may be 0)
430 (p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
431 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
433 (p7) ld8 r17=[r17] // fetch the L2 entry (may be 0)
434 shr.u r19=r16,PAGE_SHIFT // shift L3 index into position
436 (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L2 entry NULL?
437 dep r17=r19,r17,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
438 (p6) br.cond.spnt page_fault
440 br.sptk.many b0 // return to continuation point
441 END(nested_dtlb_miss)
444 /////////////////////////////////////////////////////////////////////////////////////////
445 // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
452 /////////////////////////////////////////////////////////////////////////////////////////
453 // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
460 /////////////////////////////////////////////////////////////////////////////////////////
461 // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
465 * What we do here is to simply turn on the dirty bit in the PTE. We need to
466 * update both the page-table and the TLB entry. To efficiently access the PTE,
467 * we address it through the virtual page table. Most likely, the TLB entry for
468 * the relevant virtual page table page is still present in the TLB so we can
469 * normally do this without additional TLB misses. In case the necessary virtual
470 * page table TLB entry isn't present, we take a nested TLB miss hit where we look
471 * up the physical address of the L3 PTE and then continue at label 1 below.
473 mov r16=cr.ifa // get the address that caused the fault
474 movl r30=1f // load continuation point in case of nested fault
476 thash r17=r16 // compute virtual address of L3 PTE
477 mov r29=b0 // save b0 in case of nested fault
478 mov r31=pr // save pr
480 mov r28=ar.ccv // save ar.ccv
483 ;; // avoid RAW on r18
484 mov ar.ccv=r18 // set compare value for cmpxchg
485 or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
487 cmpxchg8.acq r26=[r17],r25,ar.ccv
488 mov r24=PAGE_SHIFT<<2
492 (p6) itc.d r25 // install updated PTE
494 ld8 r18=[r17] // read PTE again
496 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
499 mov b0=r29 // restore b0
504 ;; // avoid RAW on r18
505 or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
506 mov b0=r29 // restore b0
508 st8 [r17]=r18 // store back updated PTE
509 itc.d r18 // install updated PTE
511 mov pr=r31,-1 // restore pr
516 /////////////////////////////////////////////////////////////////////////////////////////
517 // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
520 // Like Entry 8, except for instruction access
521 mov r16=cr.ifa // get the address that caused the fault
522 movl r30=1f // load continuation point in case of nested fault
523 mov r31=pr // save predicates
524 #ifdef CONFIG_ITANIUM
526 * Erratum 10 (IFA may contain incorrect address) has "NoFix" status.
531 tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set?
533 (p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa
534 #endif /* CONFIG_ITANIUM */
536 thash r17=r16 // compute virtual address of L3 PTE
537 mov r29=b0 // save b0 in case of nested fault)
539 mov r28=ar.ccv // save ar.ccv
543 mov ar.ccv=r18 // set compare value for cmpxchg
544 or r25=_PAGE_A,r18 // set the accessed bit
546 cmpxchg8.acq r26=[r17],r25,ar.ccv
547 mov r24=PAGE_SHIFT<<2
551 (p6) itc.i r25 // install updated PTE
553 ld8 r18=[r17] // read PTE again
555 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
558 mov b0=r29 // restore b0
560 #else /* !CONFIG_SMP */
564 or r18=_PAGE_A,r18 // set the accessed bit
565 mov b0=r29 // restore b0
567 st8 [r17]=r18 // store back updated PTE
568 itc.i r18 // install updated PTE
569 #endif /* !CONFIG_SMP */
575 /////////////////////////////////////////////////////////////////////////////////////////
576 // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
579 // Like Entry 8, except for data access
580 mov r16=cr.ifa // get the address that caused the fault
581 movl r30=1f // load continuation point in case of nested fault
583 thash r17=r16 // compute virtual address of L3 PTE
585 mov r29=b0 // save b0 in case of nested fault)
587 mov r28=ar.ccv // save ar.ccv
590 ;; // avoid RAW on r18
591 mov ar.ccv=r18 // set compare value for cmpxchg
592 or r25=_PAGE_A,r18 // set the dirty bit
594 cmpxchg8.acq r26=[r17],r25,ar.ccv
595 mov r24=PAGE_SHIFT<<2
599 (p6) itc.d r25 // install updated PTE
601 ld8 r18=[r17] // read PTE again
603 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
610 ;; // avoid RAW on r18
611 or r18=_PAGE_A,r18 // set the accessed bit
613 st8 [r17]=r18 // store back updated PTE
614 itc.d r18 // install updated PTE
616 mov b0=r29 // restore b0
622 /////////////////////////////////////////////////////////////////////////////////////////
623 // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
627 mov r17=__IA64_BREAK_SYSCALL
628 mov r31=pr // prepare to save predicates
630 cmp.eq p0,p7=r16,r17 // is this a system call? (p7 <- false, if so)
631 (p7) br.cond.spnt non_syscall
633 SAVE_MIN // uses r31; defines r2:
635 ssm psr.ic | PSR_DEFAULT_BITS
637 srlz.i // guarantee that interruption collection is on
638 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
640 (p15) ssm psr.i // restore psr.i
641 adds r8=(IA64_PT_REGS_R8_OFFSET-IA64_PT_REGS_R16_OFFSET),r2
643 stf8 [r8]=f1 // ensure pt_regs.r8 != 0 (see handle_syscall_error)
644 adds r3=8,r2 // set up second base pointer for SAVE_REST
647 br.call.sptk.many rp=demine_args // clear NaT bits in (potential) syscall args
650 adds r15=-1024,r15 // r15 contains the syscall number---subtract 1024
652 cmp.geu p6,p7=r3,r15 // (syscall > 0 && syscall <= 1024+255) ?
653 movl r16=sys_call_table
655 (p6) shladd r16=r15,3,r16
656 movl r15=ia64_ret_from_syscall
657 (p7) adds r16=(__NR_ni_syscall-1024)*8,r16 // force __NR_ni_syscall
659 ld8 r16=[r16] // load address of syscall entry point
660 mov rp=r15 // set the real return addr
664 // arrange things so we skip over break instruction when returning:
666 adds r16=16,sp // get pointer to cr_ipsr
667 adds r17=24,sp // get pointer to cr_iip
668 add r2=TI_FLAGS+IA64_TASK_SIZE,r13
670 ld8 r18=[r16] // fetch cr_ipsr
671 ld4 r2=[r2] // r2 = current_thread_info()->flags
673 ld8 r19=[r17] // fetch cr_iip
674 extr.u r20=r18,41,2 // extract ei field
676 cmp.eq p6,p7=2,r20 // isr.ei==2?
677 adds r19=16,r19 // compute address of next bundle
679 (p6) mov r20=0 // clear ei to 0
680 (p7) adds r20=1,r20 // increment ei to next slot
682 (p6) st8 [r17]=r19 // store new cr.iip if cr.isr.ei wrapped around
683 dep r18=r20,r18,41,2 // insert new ei into cr.isr
684 tbit.z p8,p0=r2,TIF_SYSCALL_TRACE
686 st8 [r16]=r18 // store new value for cr.isr
688 (p8) br.call.sptk.many b6=b6 // ignore this return addr
689 br.cond.sptk ia64_trace_syscall
693 ENTRY_MIN_ALIGN(demine_args)
694 alloc r2=ar.pfs,8,0,0,0
711 tnat.nz p8,p0=r15 // demining r15 is not a must, but it is safer
723 /////////////////////////////////////////////////////////////////////////////////////////
724 // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
727 mov r31=pr // prepare to save predicates
730 SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3
731 ssm psr.ic | PSR_DEFAULT_BITS
733 adds r3=8,r2 // set up second base pointer for SAVE_REST
734 srlz.i // ensure everybody knows psr.ic is back on
738 alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
739 mov out0=cr.ivr // pass cr.ivr as first arg
740 add out1=16,sp // pass pointer to pt_regs as second arg
742 srlz.d // make sure we see the effect of cr.ivr
743 movl r14=ia64_leave_kernel
746 br.call.sptk.many b6=ia64_handle_irq
750 /////////////////////////////////////////////////////////////////////////////////////////
751 // 0x3400 Entry 13 (size 64 bundles) Reserved
756 /////////////////////////////////////////////////////////////////////////////////////////
757 // 0x3800 Entry 14 (size 64 bundles) Reserved
762 /////////////////////////////////////////////////////////////////////////////////////////
763 // 0x3c00 Entry 15 (size 64 bundles) Reserved
768 * Squatting in this space ...
770 * This special case dispatcher for illegal operation faults allows preserved
771 * registers to be modified through a callback function (asm only) that is handed
772 * back from the fault handler in r8. Up to three arguments can be passed to the
773 * callback function by returning an aggregate with the callback as its first
774 * element, followed by the arguments.
776 ENTRY(dispatch_illegal_op_fault)
778 ssm psr.ic | PSR_DEFAULT_BITS
780 srlz.i // guarantee that interruption collection is on
782 (p15) ssm psr.i // restore psr.i
783 adds r3=8,r2 // set up second base pointer for SAVE_REST
785 alloc r14=ar.pfs,0,0,1,0 // must be first in insn group
790 br.call.sptk.many rp=ia64_illegal_op_fault
792 alloc r14=ar.pfs,0,0,3,0 // must be first in insn group
796 movl r15=ia64_leave_kernel
802 (p6) br.call.dpnt.many b6=b6 // call returns to ia64_leave_kernel
803 br.sptk.many ia64_leave_kernel
804 END(dispatch_illegal_op_fault)
807 /////////////////////////////////////////////////////////////////////////////////////////
808 // 0x4000 Entry 16 (size 64 bundles) Reserved
812 #ifdef CONFIG_IA32_SUPPORT
815 * There is no particular reason for this code to be here, other than that
816 * there happens to be space here that would go unused otherwise. If this
817 * fault ever gets "unreserved", simply moved the following code to a more
821 // IA32 interrupt entry point
823 ENTRY(dispatch_to_ia32_handler)
827 ssm psr.ic | PSR_DEFAULT_BITS
829 srlz.i // guarantee that interruption collection is on
832 adds r3=8,r2 // Base pointer for SAVE_REST
837 shr r14=r14,16 // Get interrupt number
840 (p6) br.call.dpnt.many b6=non_ia32_syscall
842 adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp // 16 byte hole per SW conventions
843 adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp
845 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
846 st8 [r15]=r8 // save original EAX in r1 (IA32 procs don't use the GP)
848 alloc r15=ar.pfs,0,0,6,0 // must first in an insn group
850 ld4 r8=[r14],8 // r8 == eax (syscall number)
851 mov r15=250 // number of entries in ia32 system call table
853 cmp.ltu.unc p6,p7=r8,r15
854 ld4 out1=[r14],8 // r9 == ecx
856 ld4 out2=[r14],8 // r10 == edx
858 ld4 out0=[r14] // r11 == ebx
859 adds r14=(IA64_PT_REGS_R8_OFFSET-(8*3)) + 16,sp
861 ld4 out5=[r14],8 // r13 == ebp
863 ld4 out3=[r14],8 // r14 == esi
864 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
866 ld4 out4=[r14] // r15 == edi
867 movl r16=ia32_syscall_table
869 (p6) shladd r16=r8,3,r16 // force ni_syscall if not valid syscall number
870 ld4 r2=[r2] // r2 = current_thread_info()->flags
873 tbit.z p8,p0=r2,TIF_SYSCALL_TRACE
876 movl r15=ia32_ret_from_syscall
879 (p8) br.call.sptk.many b6=b6
880 br.cond.sptk ia32_trace_syscall
883 alloc r15=ar.pfs,0,0,2,0
884 mov out0=r14 // interrupt #
885 add out1=16,sp // pointer to pt_regs
886 ;; // avoid WAW on CFM
887 br.call.sptk.many rp=ia32_bad_interrupt
888 .ret1: movl r15=ia64_leave_kernel
892 END(dispatch_to_ia32_handler)
894 #endif /* CONFIG_IA32_SUPPORT */
897 /////////////////////////////////////////////////////////////////////////////////////////
898 // 0x4400 Entry 17 (size 64 bundles) Reserved
905 // There is no particular reason for this code to be here, other than that
906 // there happens to be space here that would go unused otherwise. If this
907 // fault ever gets "unreserved", simply moved the following code to a more
910 alloc r14=ar.pfs,0,0,2,0
913 adds r3=8,r2 // set up second base pointer for SAVE_REST
915 ssm psr.ic | PSR_DEFAULT_BITS
917 srlz.i // guarantee that interruption collection is on
919 (p15) ssm psr.i // restore psr.i
920 movl r15=ia64_leave_kernel
925 br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr
929 /////////////////////////////////////////////////////////////////////////////////////////
930 // 0x4800 Entry 18 (size 64 bundles) Reserved
935 * There is no particular reason for this code to be here, other than that
936 * there happens to be space here that would go unused otherwise. If this
937 * fault ever gets "unreserved", simply moved the following code to a more
941 ENTRY(dispatch_unaligned_handler)
944 alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!)
948 ssm psr.ic | PSR_DEFAULT_BITS
950 srlz.i // guarantee that interruption collection is on
952 (p15) ssm psr.i // restore psr.i
953 adds r3=8,r2 // set up second base pointer
956 movl r14=ia64_leave_kernel
959 br.sptk.many ia64_prepare_handle_unaligned
960 END(dispatch_unaligned_handler)
963 /////////////////////////////////////////////////////////////////////////////////////////
964 // 0x4c00 Entry 19 (size 64 bundles) Reserved
969 * There is no particular reason for this code to be here, other than that
970 * there happens to be space here that would go unused otherwise. If this
971 * fault ever gets "unreserved", simply moved the following code to a more
975 ENTRY(dispatch_to_fault_handler)
979 * r19: fault vector number (e.g., 24 for General Exception)
980 * r31: contains saved predicates (pr)
982 SAVE_MIN_WITH_COVER_R19
983 alloc r14=ar.pfs,0,0,5,0
990 ssm psr.ic | PSR_DEFAULT_BITS
992 srlz.i // guarantee that interruption collection is on
994 (p15) ssm psr.i // restore psr.i
995 adds r3=8,r2 // set up second base pointer for SAVE_REST
998 movl r14=ia64_leave_kernel
1001 br.call.sptk.many b6=ia64_fault
1002 END(dispatch_to_fault_handler)
1005 // --- End of long entries, Beginning of short entries
1008 .org ia64_ivt+0x5000
1009 /////////////////////////////////////////////////////////////////////////////////////////
1010 // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
1011 ENTRY(page_not_present)
1016 * The Linux page fault handler doesn't expect non-present pages to be in
1017 * the TLB. Flush the existing entry now, so we meet that expectation.
1019 mov r17=PAGE_SHIFT<<2
1025 br.sptk.many page_fault
1026 END(page_not_present)
1028 .org ia64_ivt+0x5100
1029 /////////////////////////////////////////////////////////////////////////////////////////
1030 // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
1031 ENTRY(key_permission)
1038 br.sptk.many page_fault
1041 .org ia64_ivt+0x5200
1042 /////////////////////////////////////////////////////////////////////////////////////////
1043 // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
1044 ENTRY(iaccess_rights)
1051 br.sptk.many page_fault
1054 .org ia64_ivt+0x5300
1055 /////////////////////////////////////////////////////////////////////////////////////////
1056 // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
1057 ENTRY(daccess_rights)
1064 br.sptk.many page_fault
1067 .org ia64_ivt+0x5400
1068 /////////////////////////////////////////////////////////////////////////////////////////
1069 // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
1070 ENTRY(general_exception)
1076 (p6) br.sptk.many dispatch_illegal_op_fault
1078 mov r19=24 // fault number
1079 br.sptk.many dispatch_to_fault_handler
1080 END(general_exception)
1082 .org ia64_ivt+0x5500
1083 /////////////////////////////////////////////////////////////////////////////////////////
1084 // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
1085 ENTRY(disabled_fp_reg)
1087 rsm psr.dfh // ensure we can access fph
1092 br.sptk.many dispatch_to_fault_handler
1093 END(disabled_fp_reg)
1095 .org ia64_ivt+0x5600
1096 /////////////////////////////////////////////////////////////////////////////////////////
1097 // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
1098 ENTRY(nat_consumption)
1101 END(nat_consumption)
1103 .org ia64_ivt+0x5700
1104 /////////////////////////////////////////////////////////////////////////////////////////
1105 // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
1106 ENTRY(speculation_vector)
1109 * A [f]chk.[as] instruction needs to take the branch to the recovery code but
1110 * this part of the architecture is not implemented in hardware on some CPUs, such
1111 * as Itanium. Thus, in general we need to emulate the behavior. IIM contains
1112 * the relative target (not yet sign extended). So after sign extending it we
1113 * simply add it to IIP. We also need to reset the EI field of the IPSR to zero,
1114 * i.e., the slot to restart into.
1116 * cr.imm contains zero_ext(imm21)
1121 shl r18=r18,43 // put sign bit in position (43=64-21)
1125 shr r18=r18,39 // sign extend (39=43-4)
1128 add r17=r17,r18 // now add the offset
1131 dep r16=0,r16,41,2 // clear EI
1138 END(speculation_vector)
1140 .org ia64_ivt+0x5800
1141 /////////////////////////////////////////////////////////////////////////////////////////
1142 // 0x5800 Entry 28 (size 16 bundles) Reserved
1146 .org ia64_ivt+0x5900
1147 /////////////////////////////////////////////////////////////////////////////////////////
1148 // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
1154 .org ia64_ivt+0x5a00
1155 /////////////////////////////////////////////////////////////////////////////////////////
1156 // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
1157 ENTRY(unaligned_access)
1160 mov r31=pr // prepare to save predicates
1162 br.sptk.many dispatch_unaligned_handler
1163 END(unaligned_access)
1165 .org ia64_ivt+0x5b00
1166 /////////////////////////////////////////////////////////////////////////////////////////
1167 // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
1168 ENTRY(unsupported_data_reference)
1171 END(unsupported_data_reference)
1173 .org ia64_ivt+0x5c00
1174 /////////////////////////////////////////////////////////////////////////////////////////
1175 // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
1176 ENTRY(floating_point_fault)
1179 END(floating_point_fault)
1181 .org ia64_ivt+0x5d00
1182 /////////////////////////////////////////////////////////////////////////////////////////
1183 // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
1184 ENTRY(floating_point_trap)
1187 END(floating_point_trap)
1189 .org ia64_ivt+0x5e00
1190 /////////////////////////////////////////////////////////////////////////////////////////
1191 // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
1192 ENTRY(lower_privilege_trap)
1195 END(lower_privilege_trap)
1197 .org ia64_ivt+0x5f00
1198 /////////////////////////////////////////////////////////////////////////////////////////
1199 // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
1200 ENTRY(taken_branch_trap)
1203 END(taken_branch_trap)
1205 .org ia64_ivt+0x6000
1206 /////////////////////////////////////////////////////////////////////////////////////////
1207 // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
1208 ENTRY(single_step_trap)
1211 END(single_step_trap)
1213 .org ia64_ivt+0x6100
1214 /////////////////////////////////////////////////////////////////////////////////////////
1215 // 0x6100 Entry 37 (size 16 bundles) Reserved
1219 .org ia64_ivt+0x6200
1220 /////////////////////////////////////////////////////////////////////////////////////////
1221 // 0x6200 Entry 38 (size 16 bundles) Reserved
1225 .org ia64_ivt+0x6300
1226 /////////////////////////////////////////////////////////////////////////////////////////
1227 // 0x6300 Entry 39 (size 16 bundles) Reserved
1231 .org ia64_ivt+0x6400
1232 /////////////////////////////////////////////////////////////////////////////////////////
1233 // 0x6400 Entry 40 (size 16 bundles) Reserved
1237 .org ia64_ivt+0x6500
1238 /////////////////////////////////////////////////////////////////////////////////////////
1239 // 0x6500 Entry 41 (size 16 bundles) Reserved
1243 .org ia64_ivt+0x6600
1244 /////////////////////////////////////////////////////////////////////////////////////////
1245 // 0x6600 Entry 42 (size 16 bundles) Reserved
1249 .org ia64_ivt+0x6700
1250 /////////////////////////////////////////////////////////////////////////////////////////
1251 // 0x6700 Entry 43 (size 16 bundles) Reserved
1255 .org ia64_ivt+0x6800
1256 /////////////////////////////////////////////////////////////////////////////////////////
1257 // 0x6800 Entry 44 (size 16 bundles) Reserved
1261 .org ia64_ivt+0x6900
1262 /////////////////////////////////////////////////////////////////////////////////////////
1263 // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
1264 ENTRY(ia32_exception)
1269 .org ia64_ivt+0x6a00
1270 /////////////////////////////////////////////////////////////////////////////////////////
1271 // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
1272 ENTRY(ia32_intercept)
1274 #ifdef CONFIG_IA32_SUPPORT
1278 extr.u r17=r16,16,8 // get ISR.code
1280 mov r19=cr.iim // old eflag value
1283 (p6) br.cond.spnt 1f // not a system flag fault
1286 extr.u r17=r16,18,1 // get the eflags.ac bit
1289 (p6) br.cond.spnt 1f // eflags.ac bit didn't change
1291 mov pr=r31,-1 // restore predicate registers
1295 #endif // CONFIG_IA32_SUPPORT
1299 .org ia64_ivt+0x6b00
1300 /////////////////////////////////////////////////////////////////////////////////////////
1301 // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74)
1302 ENTRY(ia32_interrupt)
1304 #ifdef CONFIG_IA32_SUPPORT
1306 br.sptk.many dispatch_to_ia32_handler
1312 .org ia64_ivt+0x6c00
1313 /////////////////////////////////////////////////////////////////////////////////////////
1314 // 0x6c00 Entry 48 (size 16 bundles) Reserved
1318 .org ia64_ivt+0x6d00
1319 /////////////////////////////////////////////////////////////////////////////////////////
1320 // 0x6d00 Entry 49 (size 16 bundles) Reserved
1324 .org ia64_ivt+0x6e00
1325 /////////////////////////////////////////////////////////////////////////////////////////
1326 // 0x6e00 Entry 50 (size 16 bundles) Reserved
1330 .org ia64_ivt+0x6f00
1331 /////////////////////////////////////////////////////////////////////////////////////////
1332 // 0x6f00 Entry 51 (size 16 bundles) Reserved
1336 .org ia64_ivt+0x7000
1337 /////////////////////////////////////////////////////////////////////////////////////////
1338 // 0x7000 Entry 52 (size 16 bundles) Reserved
1342 .org ia64_ivt+0x7100
1343 /////////////////////////////////////////////////////////////////////////////////////////
1344 // 0x7100 Entry 53 (size 16 bundles) Reserved
1348 .org ia64_ivt+0x7200
1349 /////////////////////////////////////////////////////////////////////////////////////////
1350 // 0x7200 Entry 54 (size 16 bundles) Reserved
1354 .org ia64_ivt+0x7300
1355 /////////////////////////////////////////////////////////////////////////////////////////
1356 // 0x7300 Entry 55 (size 16 bundles) Reserved
1360 .org ia64_ivt+0x7400
1361 /////////////////////////////////////////////////////////////////////////////////////////
1362 // 0x7400 Entry 56 (size 16 bundles) Reserved
1366 .org ia64_ivt+0x7500
1367 /////////////////////////////////////////////////////////////////////////////////////////
1368 // 0x7500 Entry 57 (size 16 bundles) Reserved
1372 .org ia64_ivt+0x7600
1373 /////////////////////////////////////////////////////////////////////////////////////////
1374 // 0x7600 Entry 58 (size 16 bundles) Reserved
1378 .org ia64_ivt+0x7700
1379 /////////////////////////////////////////////////////////////////////////////////////////
1380 // 0x7700 Entry 59 (size 16 bundles) Reserved
1384 .org ia64_ivt+0x7800
1385 /////////////////////////////////////////////////////////////////////////////////////////
1386 // 0x7800 Entry 60 (size 16 bundles) Reserved
1390 .org ia64_ivt+0x7900
1391 /////////////////////////////////////////////////////////////////////////////////////////
1392 // 0x7900 Entry 61 (size 16 bundles) Reserved
1396 .org ia64_ivt+0x7a00
1397 /////////////////////////////////////////////////////////////////////////////////////////
1398 // 0x7a00 Entry 62 (size 16 bundles) Reserved
1402 .org ia64_ivt+0x7b00
1403 /////////////////////////////////////////////////////////////////////////////////////////
1404 // 0x7b00 Entry 63 (size 16 bundles) Reserved
1408 .org ia64_ivt+0x7c00
1409 /////////////////////////////////////////////////////////////////////////////////////////
1410 // 0x7c00 Entry 64 (size 16 bundles) Reserved
1414 .org ia64_ivt+0x7d00
1415 /////////////////////////////////////////////////////////////////////////////////////////
1416 // 0x7d00 Entry 65 (size 16 bundles) Reserved
1420 .org ia64_ivt+0x7e00
1421 /////////////////////////////////////////////////////////////////////////////////////////
1422 // 0x7e00 Entry 66 (size 16 bundles) Reserved
1426 .org ia64_ivt+0x7f00
1427 /////////////////////////////////////////////////////////////////////////////////////////
1428 // 0x7f00 Entry 67 (size 16 bundles) Reserved