2 * This file is subject to the terms and conditions of the GNU General
3 * Public License. See the file "COPYING" in the main directory of
4 * this archive for more details.
6 * Copyright (C) 1997, 2001-2003 Silicon Graphics, Inc. All rights reserved.
10 #ifndef _ASM_SN_PCI_PCIBA_H
11 #define _ASM_SN_PCI_PCIBA_H
13 #include <linux/ioctl.h>
14 #include <linux/types.h>
15 #include <linux/pci.h>
17 /* for application compatibility with IRIX (why do I bother?) */
20 typedef u_int8_t uint8_t;
21 typedef u_int16_t uint16_t;
22 typedef u_int32_t uint32_t;
25 #define PCI_CFG_VENDOR_ID PCI_VENDOR_ID
26 #define PCI_CFG_COMMAND PCI_COMMAND
27 #define PCI_CFG_REV_ID PCI_REVISION_ID
28 #define PCI_CFG_HEADER_TYPE PCI_HEADER_TYPE
29 #define PCI_CFG_BASE_ADDR(n) PCI_BASE_ADDRESS_##n
32 /* /hw/.../pci/[slot]/config accepts ioctls to read
33 * and write specific registers as follows:
35 * "t" is the native type (char, short, uint32, uint64)
36 * to read from CFG space; results will be arranged in
37 * byte significance (ie. first byte from PCI is lowest
38 * or last byte in result).
40 * "r" is the byte offset in PCI CFG space of the first
41 * byte of the register (it's least significant byte,
42 * in the little-endian PCI numbering). This can actually
43 * be as much as 16 bits wide, and is intended to match
44 * the layout of a "Type 1 Configuration Space" address:
45 * the register number in the low eight bits, then three
46 * bits for the function number and five bits for the
49 #define PCIIOCCFGRD(t,r) _IOR(0,(r),t)
50 #define PCIIOCCFGWR(t,r) _IOW(0,(r),t)
52 /* Some common config register access commands.
53 * Use these as examples of how to construct
54 * values for other registers you want to access.
57 /* PCIIOCGETID: arg is ptr to 32-bit int,
58 * returns the 32-bit ID value with VENDOR
59 * in the bottom 16 bits and DEVICE in the top.
61 #define PCIIOCGETID PCIIOCCFGRD(uint32_t,PCI_CFG_VENDOR_ID)
63 /* PCIIOCSETCMD: arg is ptr to a 16-bit short,
64 * which will be written to the CMD register.
66 #define PCIIOCSETCMD PCIIOCCFGWR(uint16_t,PCI_CFG_COMMAND)
68 /* PCIIOCGETREV: arg is ptr to an 8-bit char,
69 * which will get the 8-bit revision number.
71 #define PCIIOCGETREV PCIIOCCFGRD(uint8_t,PCI_CFG_REV_ID)
73 /* PCIIOCGETHTYPE: arg is ptr to an 8-bit char,
74 * which will get the 8-bit header type.
76 #define PCIIOCGETHTYPE PCIIOCCFGRD(uint8_t,PCI_CFG_HEADER_TYPE)
78 /* PCIIOCGETBASE(n): arg is ptr to a 32-bit int,
79 * which will get the value of the BASE<n> register.
82 /* FIXME chadt: this doesn't tell me whether or not this will work
83 with non-constant 'n.' */
84 #define PCIIOCGETBASE(n) PCIIOCCFGRD(uint32_t,PCI_CFG_BASE_ADDR(n))
87 /* /hw/.../pci/[slot]/dma accepts ioctls to allocate
88 * and free physical memory for use in user-triggered
91 #define PCIIOCDMAALLOC _IOWR(0,1,uint64_t)
92 #define PCIIOCDMAFREE _IOW(0,1,uint64_t)
94 /* pio cache-mode ioctl defines. current only uncached accelerated */
95 #define PCIBA_CACHE_MODE_SET 1
96 #define PCIBA_CACHE_MODE_CLEAR 2
98 #define PCIBA_UNCACHED_ACCEL PIOMAP_UNC_ACC
101 /* The parameter for PCIIOCDMAALLOC needs to contain
102 * both the size of the request and the flag values
103 * to be used in setting up the DMA.
106 FIXME chadt: gonna have to revisit this: what flags would an IRIXer like to
109 * Any flags normally useful in pciio_dmamap
110 * or pciio_dmatrans function calls can6 be used here. */
111 #define PCIIOCDMAALLOC_REQUEST_PACK(flags,size) \
112 ((((uint64_t)(flags))<<32)| \
113 (((uint64_t)(size))&0xFFFFFFFF))
117 extern int pciba_init(void);
121 #endif /* _ASM_SN_PCI_PCIBA_H */