3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (c) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved.
9 #ifndef _ASM_SN_PCI_PCI_DEFS_H
10 #define _ASM_SN_PCI_PCI_DEFS_H
12 #include <linux/config.h>
14 /* defines for the PCI bus architecture */
16 /* Bit layout of address fields for Type-1
17 * Configuration Space cycles.
19 #define PCI_TYPE0_SLOT_MASK 0xFFFFF800
20 #define PCI_TYPE0_FUNC_MASK 0x00000700
21 #define PCI_TYPE0_REG_MASK 0x000000FF
23 #define PCI_TYPE0_SLOT_SHFT 11
24 #define PCI_TYPE0_FUNC_SHFT 8
25 #define PCI_TYPE0_REG_SHFT 0
27 #define PCI_TYPE0_FUNC(a) (((a) & PCI_TYPE0_FUNC_MASK) >> PCI_TYPE0_FUNC_SHFT)
28 #define PCI_TYPE0_REG(a) (((a) & PCI_TYPE0_REG_MASK) >> PCI_TYPE0_REG_SHFT)
30 #define PCI_TYPE0(s,f,r) ((((1<<(s)) << PCI_TYPE0_SLOT_SHFT) & PCI_TYPE0_SLOT_MASK) |\
31 (((f) << PCI_TYPE0_FUNC_SHFT) & PCI_TYPE0_FUNC_MASK) |\
32 (((r) << PCI_TYPE0_REG_SHFT) & PCI_TYPE0_REG_MASK))
34 /* Bit layout of address fields for Type-1
35 * Configuration Space cycles.
36 * NOTE: I'm including the byte offset within
37 * the 32-bit word as part of the register
38 * number as an extension of the layout in
41 #define PCI_TYPE1_BUS_MASK 0x00FF0000
42 #define PCI_TYPE1_SLOT_MASK 0x0000F800
43 #define PCI_TYPE1_FUNC_MASK 0x00000700
44 #define PCI_TYPE1_REG_MASK 0x000000FF
46 #define PCI_TYPE1_BUS_SHFT 16
47 #define PCI_TYPE1_SLOT_SHFT 11
48 #define PCI_TYPE1_FUNC_SHFT 8
49 #define PCI_TYPE1_REG_SHFT 0
51 #define PCI_TYPE1_BUS(a) (((a) & PCI_TYPE1_BUS_MASK) >> PCI_TYPE1_BUS_SHFT)
52 #define PCI_TYPE1_SLOT(a) (((a) & PCI_TYPE1_SLOT_MASK) >> PCI_TYPE1_SLOT_SHFT)
53 #define PCI_TYPE1_FUNC(a) (((a) & PCI_TYPE1_FUNC_MASK) >> PCI_TYPE1_FUNC_SHFT)
54 #define PCI_TYPE1_REG(a) (((a) & PCI_TYPE1_REG_MASK) >> PCI_TYPE1_REG_SHFT)
56 #define PCI_TYPE1(b,s,f,r) ((((b) << PCI_TYPE1_BUS_SHFT) & PCI_TYPE1_BUS_MASK) |\
57 (((s) << PCI_TYPE1_SLOT_SHFT) & PCI_TYPE1_SLOT_MASK) |\
58 (((f) << PCI_TYPE1_FUNC_SHFT) & PCI_TYPE1_FUNC_MASK) |\
59 (((r) << PCI_TYPE1_REG_SHFT) & PCI_TYPE1_REG_MASK))
61 /* Byte offsets of registers in CFG space
63 #define PCI_CFG_VENDOR_ID 0x00 /* Vendor ID (2 bytes) */
64 #define PCI_CFG_DEVICE_ID 0x02 /* Device ID (2 bytes) */
66 #define PCI_CFG_COMMAND 0x04 /* Command (2 bytes) */
67 #define PCI_CFG_STATUS 0x06 /* Status (2 bytes) */
69 /* NOTE: if you are using a C "switch" statement to
70 * differentiate between the Config space registers, be
71 * aware that PCI_CFG_CLASS_CODE and PCI_CFG_PROG_IF
72 * are the same offset.
74 #define PCI_CFG_REV_ID 0x08 /* Revision Id (1 byte) */
75 #define PCI_CFG_CLASS_CODE 0x09 /* Class Code (3 bytes) */
76 #define PCI_CFG_PROG_IF 0x09 /* Prog Interface (1 byte) */
77 #define PCI_CFG_SUB_CLASS 0x0A /* Sub Class (1 byte) */
78 #define PCI_CFG_BASE_CLASS 0x0B /* Base Class (1 byte) */
80 #define PCI_CFG_CACHE_LINE 0x0C /* Cache line size (1 byte) */
81 #define PCI_CFG_LATENCY_TIMER 0x0D /* Latency Timer (1 byte) */
82 #define PCI_CFG_HEADER_TYPE 0x0E /* Header Type (1 byte) */
83 #define PCI_CFG_BIST 0x0F /* Built In Self Test */
85 #define PCI_CFG_BASE_ADDR_0 0x10 /* Base Address (4 bytes) */
86 #define PCI_CFG_BASE_ADDR_1 0x14 /* Base Address (4 bytes) */
87 #define PCI_CFG_BASE_ADDR_2 0x18 /* Base Address (4 bytes) */
88 #define PCI_CFG_BASE_ADDR_3 0x1C /* Base Address (4 bytes) */
89 #define PCI_CFG_BASE_ADDR_4 0x20 /* Base Address (4 bytes) */
90 #define PCI_CFG_BASE_ADDR_5 0x24 /* Base Address (4 bytes) */
92 #define PCI_CFG_BASE_ADDR_OFF 0x04 /* Base Address Offset (1..5)*/
93 #define PCI_CFG_BASE_ADDR(n) (PCI_CFG_BASE_ADDR_0 + (n)*PCI_CFG_BASE_ADDR_OFF)
94 #define PCI_CFG_BASE_ADDRS 6 /* up to this many BASE regs */
96 #define PCI_CFG_CARDBUS_CIS 0x28 /* Cardbus CIS Pointer (4B) */
98 #define PCI_CFG_SUBSYS_VEND_ID 0x2C /* Subsystem Vendor ID (2B) */
99 #define PCI_CFG_SUBSYS_ID 0x2E /* Subsystem ID */
101 #define PCI_EXPANSION_ROM 0x30 /* Expansion Rom Base (4B) */
102 #define PCI_CAPABILITIES_PTR 0x34 /* Capabilities Pointer */
104 #define PCI_INTR_LINE 0x3C /* Interrupt Line (1B) */
105 #define PCI_INTR_PIN 0x3D /* Interrupt Pin (1B) */
107 #define PCI_CFG_VEND_SPECIFIC 0x40 /* first vendor specific reg */
109 /* layout for Type 0x01 headers */
111 #define PCI_CFG_PPB_BUS_PRI 0x18 /* immediate upstream bus # */
112 #define PCI_CFG_PPB_BUS_SEC 0x19 /* immediate downstream bus # */
113 #define PCI_CFG_PPB_BUS_SUB 0x1A /* last downstream bus # */
114 #define PCI_CFG_PPB_SEC_LAT 0x1B /* latency timer for SEC bus */
115 #define PCI_CFG_PPB_IOBASE 0x1C /* IO Base Addr bits 12..15 */
116 #define PCI_CFG_PPB_IOLIM 0x1D /* IO Limit Addr bits 12..15 */
117 #define PCI_CFG_PPB_SEC_STAT 0x1E /* Secondary Status */
118 #define PCI_CFG_PPB_MEMBASE 0x20 /* MEM Base Addr bits 16..31 */
119 #define PCI_CFG_PPB_MEMLIM 0x22 /* MEM Limit Addr bits 16..31 */
120 #define PCI_CFG_PPB_MEMPFBASE 0x24 /* PfMEM Base Addr bits 16..31 */
121 #define PCI_CFG_PPB_MEMPFLIM 0x26 /* PfMEM Limit Addr bits 16..31 */
122 #define PCI_CFG_PPB_MEMPFBASEHI 0x28 /* PfMEM Base Addr bits 32..63 */
123 #define PCI_CFG_PPB_MEMPFLIMHI 0x2C /* PfMEM Limit Addr bits 32..63 */
124 #define PCI_CFG_PPB_IOBASEHI 0x30 /* IO Base Addr bits 16..31 */
125 #define PCI_CFG_PPB_IOLIMHI 0x32 /* IO Limit Addr bits 16..31 */
126 #define PCI_CFG_PPB_SUB_VENDOR 0x34 /* Subsystem Vendor ID */
127 #define PCI_CFG_PPB_SUB_DEVICE 0x36 /* Subsystem Device ID */
128 #define PCI_CFG_PPB_ROM_BASE 0x38 /* ROM base address */
129 #define PCI_CFG_PPB_INT_LINE 0x3C /* Interrupt Line */
130 #define PCI_CFG_PPB_INT_PIN 0x3D /* Interrupt Pin */
131 #define PCI_CFG_PPB_BRIDGE_CTRL 0x3E /* Bridge Control */
132 /* XXX- these might be DEC 21152 specific */
133 #define PCI_CFG_PPB_CHIP_CTRL 0x40
134 #define PCI_CFG_PPB_DIAG_CTRL 0x41
135 #define PCI_CFG_PPB_ARB_CTRL 0x42
136 #define PCI_CFG_PPB_SERR_DISABLE 0x64
137 #define PCI_CFG_PPB_CLK2_CTRL 0x68
138 #define PCI_CFG_PPB_SERR_STATUS 0x6A
140 /* Command Register layout (0x04) */
141 #define PCI_CMD_IO_SPACE 0x001 /* I/O Space device */
142 #define PCI_CMD_MEM_SPACE 0x002 /* Memory Space */
143 #define PCI_CMD_BUS_MASTER 0x004 /* Bus Master */
144 #define PCI_CMD_SPEC_CYCLES 0x008 /* Special Cycles */
145 #define PCI_CMD_MEMW_INV_ENAB 0x010 /* Memory Write Inv Enable */
146 #define PCI_CMD_VGA_PALETTE_SNP 0x020 /* VGA Palette Snoop */
147 #define PCI_CMD_PAR_ERR_RESP 0x040 /* Parity Error Response */
148 #define PCI_CMD_WAIT_CYCLE_CTL 0x080 /* Wait Cycle Control */
149 #define PCI_CMD_SERR_ENABLE 0x100 /* SERR# Enable */
150 #define PCI_CMD_F_BK_BK_ENABLE 0x200 /* Fast Back-to-Back Enable */
152 /* Status Register Layout (0x06) */
153 #define PCI_STAT_PAR_ERR_DET 0x8000 /* Detected Parity Error */
154 #define PCI_STAT_SYS_ERR 0x4000 /* Signaled System Error */
155 #define PCI_STAT_RCVD_MSTR_ABT 0x2000 /* Received Master Abort */
156 #define PCI_STAT_RCVD_TGT_ABT 0x1000 /* Received Target Abort */
157 #define PCI_STAT_SGNL_TGT_ABT 0x0800 /* Signaled Target Abort */
159 #define PCI_STAT_DEVSEL_TIMING 0x0600 /* DEVSEL Timing Mask */
160 #define DEVSEL_TIMING(_x) (((_x) >> 9) & 3) /* devsel tim macro */
161 #define DEVSEL_FAST 0 /* Fast timing */
162 #define DEVSEL_MEDIUM 1 /* Medium timing */
163 #define DEVSEL_SLOW 2 /* Slow timing */
165 #define PCI_STAT_DATA_PAR_ERR 0x0100 /* Data Parity Err Detected */
166 #define PCI_STAT_F_BK_BK_CAP 0x0080 /* Fast Back-to-Back Capable */
167 #define PCI_STAT_UDF_SUPP 0x0040 /* UDF Supported */
168 #define PCI_STAT_66MHZ_CAP 0x0020 /* 66 MHz Capable */
169 #define PCI_STAT_CAP_LIST 0x0010 /* Capabilities List */
171 /* BIST Register Layout (0x0F) */
172 #define PCI_BIST_BIST_CAP 0x80 /* BIST Capable */
173 #define PCI_BIST_START_BIST 0x40 /* Start BIST */
174 #define PCI_BIST_CMPLTION_MASK 0x0F /* COMPLETION MASK */
175 #define PCI_BIST_CMPL_OK 0x00 /* 0 value is completion OK */
177 /* Base Address Register 0x10 */
178 #define PCI_BA_IO_CODEMASK 0x3 /* bottom 2 bits encode I/O BAR type */
179 #define PCI_BA_IO_SPACE 0x1 /* I/O Space Marker */
181 #define PCI_BA_MEM_CODEMASK 0xf /* bottom 4 bits encode MEM BAR type */
182 #define PCI_BA_MEM_LOCATION 0x6 /* 2 bits for location avail */
183 #define PCI_BA_MEM_32BIT 0x0 /* Anywhere in 32bit space */
184 #define PCI_BA_MEM_1MEG 0x2 /* Locate below 1 Meg */
185 #define PCI_BA_MEM_64BIT 0x4 /* Anywhere in 64bit space */
186 #define PCI_BA_PREFETCH 0x8 /* Prefetchable, no side effect */
188 #define PCI_BA_ROM_CODEMASK 0x1 /* bottom bit control expansion ROM enable */
189 #define PCI_BA_ROM_ENABLE 0x1 /* enable expansion ROM */
191 /* Bridge Control Register 0x3e */
192 #define PCI_BCTRL_DTO_SERR 0x0800 /* Discard Timer timeout generates SERR on primary bus */
193 #define PCI_BCTRL_DTO 0x0400 /* Discard Timer timeout status */
194 #define PCI_BCTRL_DTO_SEC 0x0200 /* Secondary Discard Timer: 0 => 2^15 PCI clock cycles, 1 => 2^10 */
195 #define PCI_BCTRL_DTO_PRI 0x0100 /* Primary Discard Timer: 0 => 2^15 PCI clock cycles, 1 => 2^10 */
196 #define PCI_BCTRL_F_BK_BK_ENABLE 0x0080 /* Enable Fast Back-to-Back on secondary bus */
197 #define PCI_BCTRL_RESET_SEC 0x0040 /* Reset Secondary bus */
198 #define PCI_BCTRL_MSTR_ABT_MODE 0x0020 /* Master Abort Mode: 0 => do not report Master-Aborts */
199 #define PCI_BCTRL_VGA_AF_ENABLE 0x0008 /* Enable VGA Address Forwarding */
200 #define PCI_BCTRL_ISA_AF_ENABLE 0x0004 /* Enable ISA Address Forwarding */
201 #define PCI_BCTRL_SERR_ENABLE 0x0002 /* Enable forwarding of SERR from secondary bus to primary bus */
202 #define PCI_BCTRL_PAR_ERR_RESP 0x0001 /* Enable Parity Error Response reporting on secondary interface */
205 * PCI 2.2 introduces the concept of ``capability lists.'' Capability lists
206 * provide a flexible mechanism for a device or bridge to advertise one or
207 * more standardized capabilities such as the presense of a power management
208 * interface, etc. The presense of a capability list is indicated by
209 * PCI_STAT_CAP_LIST being non-zero in the PCI_CFG_STATUS register. If
210 * PCI_STAT_CAP_LIST is set, then PCI_CFG_CAP_PTR is a ``pointer'' into the
211 * device-specific portion of the configuration header where the first
212 * capability block is stored. This ``pointer'' is a single byte which
213 * contains an offset from the beginning of the configuration header. The
214 * bottom two bits of the pointer are reserved and should be masked off to
215 * determine the offset. Each capability block contains a capability ID, a
216 * ``pointer'' to the next capability (another offset where a zero terminates
217 * the list) and capability-specific data. Each capability block starts with
218 * the capability ID and the ``next capability pointer.'' All data following
219 * this are capability-dependent.
221 #define PCI_CAP_ID 0x00 /* Capability ID (1B) */
222 #define PCI_CAP_PTR 0x01 /* Capability ``pointer'' (1B) */
224 /* PCI Capability IDs */
225 #define PCI_CAP_PM 0x01 /* PCI Power Management */
226 #define PCI_CAP_AGP 0x02 /* Accelerated Graphics Port */
227 #define PCI_CAP_VPD 0x03 /* Vital Product Data (VPD) */
228 #define PCI_CAP_SID 0x04 /* Slot Identification */
229 #define PCI_CAP_MSI 0x05 /* Message Signaled Intr */
230 #define PCI_CAP_HS 0x06 /* CompactPCI Hot Swap */
231 #define PCI_CAP_PCIX 0x07 /* PCI-X */
232 #define PCI_CAP_ID_HT 0x08 /* HyperTransport */
235 /* PIO interface macros */
237 #ifndef IOC3_EMULATION
239 #define PCI_INB(x) (*((volatile char*)x))
240 #define PCI_INH(x) (*((volatile short*)x))
241 #define PCI_INW(x) (*((volatile int*)x))
242 #define PCI_OUTB(x,y) (*((volatile char*)x) = y)
243 #define PCI_OUTH(x,y) (*((volatile short*)x) = y)
244 #define PCI_OUTW(x,y) (*((volatile int*)x) = y)
248 extern uint pci_read(void * address, int type);
249 extern void pci_write(void * address, int data, int type);
255 #define PCI_INB(x) pci_read((void *)(x),BYTE)
256 #define PCI_INH(x) pci_read((void *)(x),HALF)
257 #define PCI_INW(x) pci_read((void *)(x),WORD)
258 #define PCI_OUTB(x,y) pci_write((void *)(x),(y),BYTE)
259 #define PCI_OUTH(x,y) pci_write((void *)(x),(y),HALF)
260 #define PCI_OUTW(x,y) pci_write((void *)(x),(y),WORD)
262 #endif /* !IOC3_EMULATION */
263 /* effects on reads, merges */
266 * Definition of address layouts for PCI Config mechanism #1
267 * XXX- These largely duplicate PCI_TYPE1 constants at the top
268 * of the file; the two groups should probably be combined.
271 #define CFG1_ADDR_REGISTER_MASK 0x000000fc
272 #define CFG1_ADDR_FUNCTION_MASK 0x00000700
273 #define CFG1_ADDR_DEVICE_MASK 0x0000f800
274 #define CFG1_ADDR_BUS_MASK 0x00ff0000
276 #define CFG1_REGISTER_SHIFT 2
277 #define CFG1_FUNCTION_SHIFT 8
278 #define CFG1_DEVICE_SHIFT 11
279 #define CFG1_BUS_SHIFT 16
281 #ifdef CONFIG_SGI_IP32
282 /* Definitions related to IP32 PCI Bridge policy
283 * XXX- should probaly be moved to a mace-specific header
285 #define PCI_CONFIG_BITS 0xfe0085ff
286 #define PCI_CONTROL_MRMRA_ENABLE 0x00000800
287 #define PCI_FIRST_IO_ADDR 0x1000
288 #define PCI_IO_MAP_INCR 0x1000
289 #endif /* CONFIG_SGI_IP32 */
294 #define PCI_CFG_CLASS_PRE20 0x00
295 #define PCI_CFG_CLASS_STORAGE 0x01
296 #define PCI_CFG_CLASS_NETWORK 0x02
297 #define PCI_CFG_CLASS_DISPLAY 0x03
298 #define PCI_CFG_CLASS_MMEDIA 0x04
299 #define PCI_CFG_CLASS_MEMORY 0x05
300 #define PCI_CFG_CLASS_BRIDGE 0x06
301 #define PCI_CFG_CLASS_COMM 0x07
302 #define PCI_CFG_CLASS_BASE 0x08
303 #define PCI_CFG_CLASS_INPUT 0x09
304 #define PCI_CFG_CLASS_DOCK 0x0A
305 #define PCI_CFG_CLASS_PROC 0x0B
306 #define PCI_CFG_CLASS_SERIALBUS 0x0C
307 #define PCI_CFG_CLASS_OTHER 0xFF
310 * Important Subclasses
312 #define PCI_CFG_SUBCLASS_BRIDGE_HOST 0x00
313 #define PCI_CFG_SUBCLASS_BRIDGE_ISA 0x01
314 #define PCI_CFG_SUBCLASS_BRIDGE_EISA 0x02
315 #define PCI_CFG_SUBCLASS_BRIDGE_MC 0x03
316 #define PCI_CFG_SUBCLASS_BRIDGE_PCI 0x04
317 #define PCI_CFG_SUBCLASS_BRIDGE_PCMCIA 0x05
318 #define PCI_CFG_SUBCLASS_BRIDGE_NUBUS 0x06
319 #define PCI_CFG_SUBCLASS_BRIDGE_CARDBUS 0x07
320 #define PCI_CFG_SUBCLASS_BRIDGE_OTHER 0x80
327 * PCI config space definition
329 typedef volatile struct pci_cfg_s {
344 uint16_t subsys_vendor_id;
345 uint16_t subsys_dev_id;
355 * PCI Type 1 config space definition for PCI to PCI Bridges (PPBs)
357 typedef volatile struct pci_cfg1_s {
382 uint32_t pmem_base_upper;
383 uint32_t pmem_limit_upper;
384 uint16_t io_base_upper;
385 uint16_t io_limit_upper;
390 uint16_t ppb_control;
397 typedef volatile struct cap_pcix_cmd_reg_s {
398 uint16_t data_parity_enable: 1,
399 enable_relaxed_order: 1,
403 } cap_pcix_cmd_reg_t;
405 typedef volatile struct cap_pcix_stat_reg_s {
406 uint32_t func_num: 3,
411 split_complt_discard: 1,
412 unexpect_split_complt: 1,
419 } cap_pcix_stat_reg_t;
421 typedef volatile struct cap_pcix_type0_s {
423 uchar_t pcix_cap_nxt;
424 cap_pcix_cmd_reg_t pcix_type0_command;
425 cap_pcix_stat_reg_t pcix_type0_status;
431 * PCI config space definition
433 typedef volatile struct pci_cfg_s {
448 uint16_t subsys_dev_id;
449 uint16_t subsys_vendor_id;
459 * PCI Type 1 config space definition for PCI to PCI Bridges (PPBs)
461 typedef volatile struct pci_cfg1_s {
486 uint32_t pmem_limit_upper;
487 uint32_t pmem_base_upper;
488 uint16_t io_limit_upper;
489 uint16_t io_base_upper;
492 uint16_t ppb_control;
502 typedef volatile struct cap_pcix_cmd_reg_s {
503 uint16_t reserved1: 9,
506 enable_relaxed_order: 1,
507 data_parity_enable: 1;
508 } cap_pcix_cmd_reg_t;
510 typedef volatile struct cap_pcix_stat_reg_s {
511 uint32_t reserved1: 2,
517 unexpect_split_complt: 1,
518 split_complt_discard: 1,
524 } cap_pcix_stat_reg_t;
526 typedef volatile struct cap_pcix_type0_s {
527 cap_pcix_cmd_reg_t pcix_type0_command;
528 uchar_t pcix_cap_nxt;
530 cap_pcix_stat_reg_t pcix_type0_status;
534 #endif /* __ASSEMBLY__ */
535 #endif /* _ASM_SN_PCI_PCI_DEFS_H */