3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (c) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved.
9 #ifndef _ASM_SN_PCI_BRIDGE_H
10 #define _ASM_SN_PCI_BRIDGE_H
14 * bridge.h - header file for bridge chip and bridge portion of xbridge chip
16 * Also including offsets for unique PIC registers.
17 * The PIC asic is a follow-on to Xbridge and most of its registers are
18 * identical to those of Xbridge. PIC is different than Xbridge in that
19 * it will accept 64 bit register access and that, in some cases, data
20 * is kept in bits 63:32. PIC registers that are identical to Xbridge
21 * may be accessed identically to the Xbridge registers, allowing for lots
22 * of code reuse. Here are the access rules as described in the PIC
25 * o Read a word on a DW boundary returns D31:00 of reg.
26 * o Read a DW on a DW boundary returns D63:00 of reg.
27 * o Write a word on a DW boundary loads D31:00 of reg.
28 * o Write a DW on a DW boundary loads D63:00 of reg.
29 * o No support for word boundary access that is not double word
32 * So we can reuse a lot of bridge_s for PIC. In bridge_s are included
33 * #define tags and unions for 64 bit access to PIC registers.
34 * For a detailed PIC register layout see pic.h.
37 #include <linux/config.h>
38 #include <asm/sn/xtalk/xwidget.h>
39 #include <asm/sn/pci/pic.h>
41 extern int io_get_sh_swapper(nasid_t);
42 #define BRIDGE_REG_GET32(reg) \
43 __swab32( *(volatile uint32_t *) (((uint64_t)reg)^4) )
45 #define BRIDGE_REG_SET32(reg) \
46 *(volatile uint32_t *) (((uint64_t)reg)^4)
51 #define IOPFNSHIFT 12 /* 4K per mapped page */
53 #define IOPFNSHIFT 14 /* 16K per mapped page */
56 #define IOPGSIZE (1 << IOPFNSHIFT)
57 #define IOPG(x) ((x) >> IOPFNSHIFT)
58 #define IOPGOFF(x) ((x) & (IOPGSIZE-1))
60 /* Bridge RAM sizes */
62 #define BRIDGE_INTERNAL_ATES 128
63 #define XBRIDGE_INTERNAL_ATES 1024
65 #define BRIDGE_ATE_RAM_SIZE (BRIDGE_INTERNAL_ATES<<3) /* 1kB ATE */
66 #define XBRIDGE_ATE_RAM_SIZE (XBRIDGE_INTERNAL_ATES<<3) /* 8kB ATE */
68 #define PIC_WR_REQ_BUFSIZE 256
70 #define BRIDGE_CONFIG_BASE 0x20000 /* start of bridge's */
71 /* map to each device's */
73 #define BRIDGE_CONFIG1_BASE 0x28000 /* type 1 device config space */
74 #define BRIDGE_CONFIG_END 0x30000
75 #define BRIDGE_CONFIG_SLOT_SIZE 0x1000 /* each map == 4k */
77 #define BRIDGE_SSRAM_512K 0x00080000 /* 512kB */
78 #define BRIDGE_SSRAM_128K 0x00020000 /* 128kB */
79 #define BRIDGE_SSRAM_64K 0x00010000 /* 64kB */
80 #define BRIDGE_SSRAM_0K 0x00000000 /* 0kB */
82 /* ========================================================================
93 * All accesses to bridge hardware registers must be done
94 * using 32-bit loads and stores.
96 typedef uint32_t bridgereg_t;
98 typedef uint64_t bridge_ate_t;
100 /* pointers to bridge ATEs
101 * are always "pointer to volatile"
103 typedef volatile bridge_ate_t *bridge_ate_p;
106 * It is generally preferred that hardware registers on the bridge
107 * are located from C code via this structure.
109 * Generated from Bridge spec dated 04oct95
114 * pic_widget_cfg_s is a local definition of widget_cfg_t but with
115 * a union of 64bit & 32bit registers, since PIC has 64bit widget
116 * registers but BRIDGE and XBRIDGE have 32bit. PIC registers that
117 * have valid bits (ie. not just reserved) in the upper 32bits are
118 * defined as a union so we can access them as 64bit for PIC and
119 * as 32bit for BRIDGE and XBRIDGE.
121 typedef volatile struct pic_widget_cfg_s {
122 bridgereg_t _b_wid_id; /* 0x000004 */
123 bridgereg_t _pad_000000;
126 picreg_t _p_wid_stat; /* 0x000008 */
128 bridgereg_t _b_wid_stat; /* 0x00000C */
129 bridgereg_t _b_pad_000008;
132 #define __p_wid_stat_64 u_wid_stat._p_wid_stat
133 #define __b_wid_stat u_wid_stat._b._b_wid_stat
135 bridgereg_t _b_wid_err_upper; /* 0x000014 */
136 bridgereg_t _pad_000010;
139 picreg_t _p_wid_err_lower; /* 0x000018 */
141 bridgereg_t _b_wid_err_lower; /* 0x00001C */
142 bridgereg_t _b_pad_000018;
145 #define __p_wid_err_64 u_wid_err_lower._p_wid_err_lower
146 #define __b_wid_err_lower u_wid_err_lower._b._b_wid_err_lower
149 picreg_t _p_wid_control; /* 0x000020 */
151 bridgereg_t _b_wid_control; /* 0x000024 */
152 bridgereg_t _b_pad_000020;
155 #define __p_wid_control_64 u_wid_control._p_wid_control
156 #define __b_wid_control u_wid_control._b._b_wid_control
158 bridgereg_t _b_wid_req_timeout; /* 0x00002C */
159 bridgereg_t _pad_000028;
161 bridgereg_t _b_wid_int_upper; /* 0x000034 */
162 bridgereg_t _pad_000030;
165 picreg_t _p_wid_int_lower; /* 0x000038 */
167 bridgereg_t _b_wid_int_lower; /* 0x00003C */
168 bridgereg_t _b_pad_000038;
171 #define __p_wid_int_64 u_wid_int_lower._p_wid_int_lower
172 #define __b_wid_int_lower u_wid_int_lower._b._b_wid_int_lower
174 bridgereg_t _b_wid_err_cmdword; /* 0x000044 */
175 bridgereg_t _pad_000040;
177 bridgereg_t _b_wid_llp; /* 0x00004C */
178 bridgereg_t _pad_000048;
180 bridgereg_t _b_wid_tflush; /* 0x000054 */
181 bridgereg_t _pad_000050;
185 * BRIDGE, XBRIDGE, PIC register definitions. NOTE: Prior to PIC, registers
186 * were a 32bit quantity and double word aligned (and only accessible as a
187 * 32bit word. PIC registers are 64bits and accessible as words or double
188 * words. PIC registers that have valid bits (ie. not just reserved) in the
189 * upper 32bits are defined as a union of one 64bit picreg_t and two 32bit
190 * bridgereg_t so we can access them both ways.
192 * It is generally preferred that hardware registers on the bridge are
193 * located from C code via this structure.
195 * Generated from Bridge spec dated 04oct95
198 typedef volatile struct bridge_s {
200 /* 0x000000-0x00FFFF -- Local Registers */
202 /* 0x000000-0x000057 -- Standard Widget Configuration */
204 widget_cfg_t xtalk_widget_def; /* 0x000000 */
205 pic_widget_cfg_t local_widget_def; /* 0x000000 */
208 /* 32bit widget register access via the widget_cfg_t */
209 #define b_widget u_wid.xtalk_widget_def
211 /* 32bit widget register access via the pic_widget_cfg_t */
212 #define b_wid_id u_wid.local_widget_def._b_wid_id
213 #define b_wid_stat u_wid.local_widget_def.__b_wid_stat
214 #define b_wid_err_upper u_wid.local_widget_def._b_wid_err_upper
215 #define b_wid_err_lower u_wid.local_widget_def.__b_wid_err_lower
216 #define b_wid_control u_wid.local_widget_def.__b_wid_control
217 #define b_wid_req_timeout u_wid.local_widget_def._b_wid_req_timeout
218 #define b_wid_int_upper u_wid.local_widget_def._b_wid_int_upper
219 #define b_wid_int_lower u_wid.local_widget_def.__b_wid_int_lower
220 #define b_wid_err_cmdword u_wid.local_widget_def._b_wid_err_cmdword
221 #define b_wid_llp u_wid.local_widget_def._b_wid_llp
222 #define b_wid_tflush u_wid.local_widget_def._b_wid_tflush
224 /* 64bit widget register access via the pic_widget_cfg_t */
225 #define p_wid_stat_64 u_wid.local_widget_def.__p_wid_stat_64
226 #define p_wid_err_64 u_wid.local_widget_def.__p_wid_err_64
227 #define p_wid_control_64 u_wid.local_widget_def.__p_wid_control_64
228 #define p_wid_int_64 u_wid.local_widget_def.__p_wid_int_64
230 /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
231 bridgereg_t b_wid_aux_err; /* 0x00005C */
232 bridgereg_t _pad_000058;
234 bridgereg_t b_wid_resp_upper; /* 0x000064 */
235 bridgereg_t _pad_000060;
238 picreg_t _p_wid_resp_lower; /* 0x000068 */
240 bridgereg_t _b_wid_resp_lower; /* 0x00006C */
241 bridgereg_t _b_pad_000068;
244 #define p_wid_resp_64 u_wid_resp_lower._p_wid_resp_lower
245 #define b_wid_resp_lower u_wid_resp_lower._b._b_wid_resp_lower
247 bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */
248 bridgereg_t _pad_000070;
251 picreg_t _p_addr_lkerr; /* 0x000078 */
253 bridgereg_t _b_pad_00007C;
254 bridgereg_t _b_pad_000078;
257 #define p_addr_lkerr_64 u_addr_lkerr._p_addr_lkerr
259 /* 0x000080-0x00008F -- PMU */
260 bridgereg_t b_dir_map; /* 0x000084 */
261 bridgereg_t _pad_000080;
263 bridgereg_t _pad_00008C;
264 bridgereg_t _pad_000088;
266 /* 0x000090-0x00009F -- SSRAM */
267 bridgereg_t b_ram_perr_or_map_fault;/* 0x000094 */
268 bridgereg_t _pad_000090;
269 #define b_ram_perr b_ram_perr_or_map_fault /* Bridge */
270 #define b_map_fault b_ram_perr_or_map_fault /* Xbridge & PIC */
272 bridgereg_t _pad_00009C;
273 bridgereg_t _pad_000098;
275 /* 0x0000A0-0x0000AF -- Arbitration */
276 bridgereg_t b_arb; /* 0x0000A4 */
277 bridgereg_t _pad_0000A0;
279 bridgereg_t _pad_0000AC;
280 bridgereg_t _pad_0000A8;
282 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
284 picreg_t _p_ate_parity_err; /* 0x0000B0 */
286 bridgereg_t _b_nic; /* 0x0000B4 */
287 bridgereg_t _b_pad_0000B0;
289 } u_ate_parity_err_or_nic;
290 #define p_ate_parity_err_64 u_ate_parity_err_or_nic._p_ate_parity_err
291 #define b_nic u_ate_parity_err_or_nic._b._b_nic
293 bridgereg_t _pad_0000BC;
294 bridgereg_t _pad_0000B8;
296 /* 0x0000C0-0x0000FF -- PCI/GIO */
297 bridgereg_t b_bus_timeout; /* 0x0000C4 */
298 bridgereg_t _pad_0000C0;
299 #define b_pci_bus_timeout b_bus_timeout
301 bridgereg_t b_pci_cfg; /* 0x0000CC */
302 bridgereg_t _pad_0000C8;
304 bridgereg_t b_pci_err_upper; /* 0x0000D4 */
305 bridgereg_t _pad_0000D0;
306 #define b_gio_err_upper b_pci_err_upper
309 picreg_t _p_pci_err_lower; /* 0x0000D8 */
311 bridgereg_t _b_pci_err_lower; /* 0x0000DC */
312 bridgereg_t _b_pad_0000D8;
315 #define p_pci_err_64 u_pci_err_lower._p_pci_err_lower
316 #define b_pci_err_lower u_pci_err_lower._b._b_pci_err_lower
317 #define b_gio_err_lower b_pci_err_lower
319 bridgereg_t _pad_0000E0[8];
321 /* 0x000100-0x0001FF -- Interrupt */
323 picreg_t _p_int_status; /* 0x000100 */
325 bridgereg_t _b_int_status; /* 0x000104 */
326 bridgereg_t _b_pad_000100;
329 #define p_int_status_64 u_int_status._p_int_status
330 #define b_int_status u_int_status._b._b_int_status
333 picreg_t _p_int_enable; /* 0x000108 */
335 bridgereg_t _b_int_enable; /* 0x00010C */
336 bridgereg_t _b_pad_000108;
339 #define p_int_enable_64 u_int_enable._p_int_enable
340 #define b_int_enable u_int_enable._b._b_int_enable
343 picreg_t _p_int_rst_stat; /* 0x000110 */
345 bridgereg_t _b_int_rst_stat; /* 0x000114 */
346 bridgereg_t _b_pad_000110;
349 #define p_int_rst_stat_64 u_int_rst_stat._p_int_rst_stat
350 #define b_int_rst_stat u_int_rst_stat._b._b_int_rst_stat
352 bridgereg_t b_int_mode; /* 0x00011C */
353 bridgereg_t _pad_000118;
355 bridgereg_t b_int_device; /* 0x000124 */
356 bridgereg_t _pad_000120;
358 bridgereg_t b_int_host_err; /* 0x00012C */
359 bridgereg_t _pad_000128;
362 picreg_t _p_int_addr[8]; /* 0x0001{30,,,68} */
364 bridgereg_t addr; /* 0x0001{34,,,6C} */
368 #define p_int_addr_64 u_int_addr._p_int_addr
369 #define b_int_addr u_int_addr._b
372 picreg_t _p_err_int_view; /* 0x000170 */
374 bridgereg_t _b_err_int_view; /* 0x000174 */
375 bridgereg_t _b_pad_000170;
378 #define p_err_int_view_64 u_err_int_view._p_err_int_view
379 #define b_err_int_view u_err_int_view._b._b_err_int_view
382 picreg_t _p_mult_int; /* 0x000178 */
384 bridgereg_t _b_mult_int; /* 0x00017C */
385 bridgereg_t _b_pad_000178;
388 #define p_mult_int_64 u_mult_int._p_mult_int
389 #define b_mult_int u_mult_int._b._b_mult_int
392 bridgereg_t intr; /* 0x0001{84,,,BC} */
397 bridgereg_t intr; /* 0x0001{C4,,,FC} */
401 /* 0x000200-0x0003FF -- Device */
403 bridgereg_t reg; /* 0x0002{04,,,3C} */
408 bridgereg_t reg; /* 0x0002{44,,,7C} */
413 bridgereg_t reg; /* 0x0002{84,,,8C} */
416 #define b_even_resp b_rrb_map[0].reg /* 0x000284 */
417 #define b_odd_resp b_rrb_map[1].reg /* 0x00028C */
419 bridgereg_t b_resp_status; /* 0x000294 */
420 bridgereg_t _pad_000290;
422 bridgereg_t b_resp_clear; /* 0x00029C */
423 bridgereg_t _pad_000298;
425 bridgereg_t _pad_0002A0[24];
427 /* Xbridge/PIC only */
430 picreg_t lower; /* 0x0003{08,,,F8} */
431 picreg_t upper; /* 0x0003{00,,,F0} */
434 bridgereg_t upper; /* 0x0003{04,,,F4} */
436 bridgereg_t lower; /* 0x0003{0C,,,FC} */
440 #define p_buf_addr_match_64 u_buf_addr_match._p
441 #define b_buf_addr_match u_buf_addr_match._b
443 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
445 bridgereg_t flush_w_touch; /* 0x000{404,,,5C4} */
447 bridgereg_t flush_wo_touch; /* 0x000{40C,,,5CC} */
449 bridgereg_t inflight; /* 0x000{414,,,5D4} */
451 bridgereg_t prefetch; /* 0x000{41C,,,5DC} */
453 bridgereg_t total_pci_retry; /* 0x000{424,,,5E4} */
455 bridgereg_t max_pci_retry; /* 0x000{42C,,,5EC} */
457 bridgereg_t max_latency; /* 0x000{434,,,5F4} */
459 bridgereg_t clear_all; /* 0x000{43C,,,5FC} */
464 * "PCI/X registers that are specific to PIC". See pic.h.
467 /* 0x000600-0x0009FF -- PCI/X registers */
468 picreg_t p_pcix_bus_err_addr_64; /* 0x000600 */
469 picreg_t p_pcix_bus_err_attr_64; /* 0x000608 */
470 picreg_t p_pcix_bus_err_data_64; /* 0x000610 */
471 picreg_t p_pcix_pio_split_addr_64; /* 0x000618 */
472 picreg_t p_pcix_pio_split_attr_64; /* 0x000620 */
473 picreg_t p_pcix_dma_req_err_attr_64; /* 0x000628 */
474 picreg_t p_pcix_dma_req_err_addr_64; /* 0x000630 */
475 picreg_t p_pcix_timeout_64; /* 0x000638 */
477 picreg_t _pad_000600[120];
479 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
481 picreg_t p_buf_attr; /* 0X000{A08,,,AF8} */
482 picreg_t p_buf_addr; /* 0x000{A00,,,AF0} */
483 } p_pcix_read_buf_64[16];
486 picreg_t p_buf_attr; /* 0x000{B08,,,BE8} */
487 picreg_t p_buf_addr; /* 0x000{B00,,,BE0} */
488 picreg_t __pad1; /* 0x000{B18,,,BF8} */
489 picreg_t p_buf_valid; /* 0x000{B10,,,BF0} */
490 } p_pcix_write_buf_64[8];
493 * end "PCI/X registers that are specific to PIC"
496 char _pad_000c00[0x010000 - 0x000c00];
498 /* 0x010000-0x011fff -- Internal Address Translation Entry RAM */
500 * Xbridge and PIC have 1024 internal ATE's and the Bridge has 128.
501 * Make enough room for the Xbridge/PIC ATE's and depend on runtime
502 * checks to limit access to bridge ATE's.
504 * In [X]bridge the internal ATE Ram is writen as double words only,
505 * but due to internal design issues it is read back as single words.
507 * b_int_ate_ram[index].hi.rd << 32 | xb_int_ate_ram_lo[index].rd
510 bridge_ate_t wr; /* write-only */ /* 0x01{0000,,,1FF8} */
512 bridgereg_t rd; /* read-only */ /* 0x01{0004,,,1FFC} */
515 } b_int_ate_ram[XBRIDGE_INTERNAL_ATES];
516 #define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd
518 /* 0x012000-0x013fff -- Internal Address Translation Entry RAM LOW */
520 bridgereg_t rd; /* read-only */ /* 0x01{2004,,,3FFC} */
522 } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES];
524 char _pad_014000[0x18000 - 0x014000];
526 /* 0x18000-0x197F8 -- PIC Write Request Ram */
527 /* 0x18000 - 0x187F8 */
528 picreg_t p_wr_req_lower[PIC_WR_REQ_BUFSIZE];
529 /* 0x18800 - 0x18FF8 */
530 picreg_t p_wr_req_upper[PIC_WR_REQ_BUFSIZE];
531 /* 0x19000 - 0x197F8 */
532 picreg_t p_wr_req_parity[PIC_WR_REQ_BUFSIZE];
534 char _pad_019800[0x20000 - 0x019800];
536 /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
537 union { /* make all access sizes available. */
538 uchar_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
539 uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
540 uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
541 uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
543 uchar_t c[0x100 / 1];
544 uint16_t s[0x100 / 2];
545 uint32_t l[0x100 / 4];
546 uint64_t d[0x100 / 8];
548 } b_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */
550 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
551 union { /* make all access sizes available. */
552 uchar_t c[0x1000 / 1];
553 uint16_t s[0x1000 / 2];
554 uint32_t l[0x1000 / 4];
555 uint64_t d[0x1000 / 8];
557 uchar_t c[0x100 / 1];
558 uint16_t s[0x100 / 2];
559 uint32_t l[0x100 / 4];
560 uint64_t d[0x100 / 8];
562 } b_type1_cfg; /* 0x028000-0x029000 */
564 char _pad_029000[0x007000]; /* 0x029000-0x030000 */
566 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
572 } b_pci_iack; /* 0x030000-0x030007 */
574 uchar_t _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */
576 /* 0x080000-0x0FFFFF -- External Address Translation Entry RAM */
577 bridge_ate_t b_ext_ate_ram[0x10000];
579 /* 0x100000-0x1FFFFF -- Reserved */
580 char _pad_100000[0x200000-0x100000];
582 /* 0x200000-0xBFFFFF -- PCI/GIO Device Spaces */
583 union { /* make all access sizes available. */
584 uchar_t c[0x100000 / 1];
585 uint16_t s[0x100000 / 2];
586 uint32_t l[0x100000 / 4];
587 uint64_t d[0x100000 / 8];
590 /* b_devio macro is a bit strange; it reflects the
591 * fact that the Bridge ASIC provides 2M for the
592 * first two DevIO windows and 1M for the other six.
594 #define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)]
596 /* 0xC00000-0xFFFFFF -- External Flash Proms 1,0 */
597 union { /* make all access sizes available. */
598 uchar_t c[0x400000 / 1]; /* read-only */
599 uint16_t s[0x400000 / 2]; /* read-write */
600 uint32_t l[0x400000 / 4]; /* read-only */
601 uint64_t d[0x400000 / 8]; /* read-only */
605 #define berr_field berr_un.berr_st
606 #endif /* __ASSEMBLY__ */
609 * The values of these macros can and should be crosschecked
610 * regularly against the offsets of the like-named fields
611 * within the "bridge_t" structure above.
614 /* Byte offset macros for Bridge internal registers */
616 #define BRIDGE_WID_ID WIDGET_ID
617 #define BRIDGE_WID_STAT WIDGET_STATUS
618 #define BRIDGE_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR
619 #define BRIDGE_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR
620 #define BRIDGE_WID_CONTROL WIDGET_CONTROL
621 #define BRIDGE_WID_REQ_TIMEOUT WIDGET_REQ_TIMEOUT
622 #define BRIDGE_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR
623 #define BRIDGE_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR
624 #define BRIDGE_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD
625 #define BRIDGE_WID_LLP WIDGET_LLP_CFG
626 #define BRIDGE_WID_TFLUSH WIDGET_TFLUSH
628 #define BRIDGE_WID_AUX_ERR 0x00005C /* Aux Error Command Word */
629 #define BRIDGE_WID_RESP_UPPER 0x000064 /* Response Buf Upper Addr */
630 #define BRIDGE_WID_RESP_LOWER 0x00006C /* Response Buf Lower Addr */
631 #define BRIDGE_WID_TST_PIN_CTRL 0x000074 /* Test pin control */
633 #define BRIDGE_DIR_MAP 0x000084 /* Direct Map reg */
635 /* Bridge has SSRAM Parity Error and Xbridge has Map Fault here */
636 #define BRIDGE_RAM_PERR 0x000094 /* SSRAM Parity Error */
637 #define BRIDGE_MAP_FAULT 0x000094 /* Map Fault */
639 #define BRIDGE_ARB 0x0000A4 /* Arbitration Priority reg */
641 #define BRIDGE_NIC 0x0000B4 /* Number In A Can */
643 #define BRIDGE_BUS_TIMEOUT 0x0000C4 /* Bus Timeout Register */
644 #define BRIDGE_PCI_BUS_TIMEOUT BRIDGE_BUS_TIMEOUT
645 #define BRIDGE_PCI_CFG 0x0000CC /* PCI Type 1 Config reg */
646 #define BRIDGE_PCI_ERR_UPPER 0x0000D4 /* PCI error Upper Addr */
647 #define BRIDGE_PCI_ERR_LOWER 0x0000DC /* PCI error Lower Addr */
649 #define BRIDGE_INT_STATUS 0x000104 /* Interrupt Status */
650 #define BRIDGE_INT_ENABLE 0x00010C /* Interrupt Enables */
651 #define BRIDGE_INT_RST_STAT 0x000114 /* Reset Intr Status */
652 #define BRIDGE_INT_MODE 0x00011C /* Interrupt Mode */
653 #define BRIDGE_INT_DEVICE 0x000124 /* Interrupt Device */
654 #define BRIDGE_INT_HOST_ERR 0x00012C /* Host Error Field */
656 #define BRIDGE_INT_ADDR0 0x000134 /* Host Address Reg */
657 #define BRIDGE_INT_ADDR_OFF 0x000008 /* Host Addr offset (1..7) */
658 #define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
660 #define BRIDGE_INT_VIEW 0x000174 /* Interrupt view */
661 #define BRIDGE_MULTIPLE_INT 0x00017c /* Multiple interrupt occurred */
663 #define BRIDGE_FORCE_ALWAYS0 0x000184 /* Force an interrupt (always)*/
664 #define BRIDGE_FORCE_ALWAYS_OFF 0x000008 /* Force Always offset */
665 #define BRIDGE_FORCE_ALWAYS(x) (BRIDGE_FORCE_ALWAYS0+(x)*BRIDGE_FORCE_ALWAYS_OFF)
667 #define BRIDGE_FORCE_PIN0 0x0001c4 /* Force an interrupt */
668 #define BRIDGE_FORCE_PIN_OFF 0x000008 /* Force Pin offset */
669 #define BRIDGE_FORCE_PIN(x) (BRIDGE_FORCE_PIN0+(x)*BRIDGE_FORCE_PIN_OFF)
671 #define BRIDGE_DEVICE0 0x000204 /* Device 0 */
672 #define BRIDGE_DEVICE_OFF 0x000008 /* Device offset (1..7) */
673 #define BRIDGE_DEVICE(x) (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
675 #define BRIDGE_WR_REQ_BUF0 0x000244 /* Write Request Buffer 0 */
676 #define BRIDGE_WR_REQ_BUF_OFF 0x000008 /* Buffer Offset (1..7) */
677 #define BRIDGE_WR_REQ_BUF(x) (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
679 #define BRIDGE_EVEN_RESP 0x000284 /* Even Device Response Buf */
680 #define BRIDGE_ODD_RESP 0x00028C /* Odd Device Response Buf */
682 #define BRIDGE_RESP_STATUS 0x000294 /* Read Response Status reg */
683 #define BRIDGE_RESP_CLEAR 0x00029C /* Read Response Clear reg */
685 #define BRIDGE_BUF_ADDR_UPPER0 0x000304
686 #define BRIDGE_BUF_ADDR_UPPER_OFF 0x000010 /* PCI Buffer Upper Offset */
687 #define BRIDGE_BUF_ADDR_UPPER(x) (BRIDGE_BUF_ADDR_UPPER0+(x)*BRIDGE_BUF_ADDR_UPPER_OFF)
689 #define BRIDGE_BUF_ADDR_LOWER0 0x00030c
690 #define BRIDGE_BUF_ADDR_LOWER_OFF 0x000010 /* PCI Buffer Upper Offset */
691 #define BRIDGE_BUF_ADDR_LOWER(x) (BRIDGE_BUF_ADDR_LOWER0+(x)*BRIDGE_BUF_ADDR_LOWER_OFF)
694 * Performance Monitor Registers.
696 * The Performance registers are those registers which are associated with
697 * monitoring the performance of PCI generated reads to the host environ
698 * ment. Because of the size of the register file only the even registers
702 #define BRIDGE_BUF_OFF 0x40
703 #define BRIDGE_BUF_NEXT(base, off) (base+((off)*BRIDGE_BUF_OFF))
706 * Buffer (x) Flush Count with Data Touch Register.
708 * This counter is incremented each time the corresponding response buffer
709 * is flushed after at least a single data element in the buffer is used.
710 * A word write to this address clears the count.
713 #define BRIDGE_BUF_0_FLUSH_TOUCH 0x000404
714 #define BRIDGE_BUF_2_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 1)
715 #define BRIDGE_BUF_4_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 2)
716 #define BRIDGE_BUF_6_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 3)
717 #define BRIDGE_BUF_8_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 4)
718 #define BRIDGE_BUF_10_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 5)
719 #define BRIDGE_BUF_12_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 6)
720 #define BRIDGE_BUF_14_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 7)
723 * Buffer (x) Flush Count w/o Data Touch Register
725 * This counter is incremented each time the corresponding response buffer
726 * is flushed without any data element in the buffer being used. A word
727 * write to this address clears the count.
731 #define BRIDGE_BUF_0_FLUSH_NOTOUCH 0x00040c
732 #define BRIDGE_BUF_2_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 1)
733 #define BRIDGE_BUF_4_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 2)
734 #define BRIDGE_BUF_6_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 3)
735 #define BRIDGE_BUF_8_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 4)
736 #define BRIDGE_BUF_10_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 5)
737 #define BRIDGE_BUF_12_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 6)
738 #define BRIDGE_BUF_14_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 7)
741 * Buffer (x) Request in Flight Count Register
743 * This counter is incremented on each bus clock while the request is in
744 * flight. A word write to this address clears the count.
747 #define BRIDGE_BUF_0_INFLIGHT 0x000414
748 #define BRIDGE_BUF_2_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 1)
749 #define BRIDGE_BUF_4_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 2)
750 #define BRIDGE_BUF_6_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 3)
751 #define BRIDGE_BUF_8_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 4)
752 #define BRIDGE_BUF_10_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 5)
753 #define BRIDGE_BUF_12_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 6)
754 #define BRIDGE_BUF_14_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 7)
757 * Buffer (x) Prefetch Request Count Register
759 * This counter is incremented each time the request using this buffer was
760 * generated from the prefetcher. A word write to this address clears the
764 #define BRIDGE_BUF_0_PREFETCH 0x00041C
765 #define BRIDGE_BUF_2_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 1)
766 #define BRIDGE_BUF_4_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 2)
767 #define BRIDGE_BUF_6_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 3)
768 #define BRIDGE_BUF_8_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 4)
769 #define BRIDGE_BUF_10_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 5)
770 #define BRIDGE_BUF_12_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 6)
771 #define BRIDGE_BUF_14_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 7)
774 * Buffer (x) Total PCI Retry Count Register
776 * This counter is incremented each time a PCI bus retry occurs and the ad
777 * dress matches the tag for the selected buffer. The buffer must also has
778 * this request in-flight. A word write to this address clears the count.
781 #define BRIDGE_BUF_0_PCI_RETRY 0x000424
782 #define BRIDGE_BUF_2_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 1)
783 #define BRIDGE_BUF_4_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 2)
784 #define BRIDGE_BUF_6_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 3)
785 #define BRIDGE_BUF_8_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 4)
786 #define BRIDGE_BUF_10_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 5)
787 #define BRIDGE_BUF_12_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 6)
788 #define BRIDGE_BUF_14_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 7)
791 * Buffer (x) Max PCI Retry Count Register
793 * This counter is contains the maximum retry count for a single request
794 * which was in-flight for this buffer. A word write to this address
798 #define BRIDGE_BUF_0_MAX_PCI_RETRY 0x00042C
799 #define BRIDGE_BUF_2_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 1)
800 #define BRIDGE_BUF_4_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 2)
801 #define BRIDGE_BUF_6_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 3)
802 #define BRIDGE_BUF_8_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 4)
803 #define BRIDGE_BUF_10_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 5)
804 #define BRIDGE_BUF_12_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 6)
805 #define BRIDGE_BUF_14_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 7)
808 * Buffer (x) Max Latency Count Register
810 * This counter is contains the maximum count (in bus clocks) for a single
811 * request which was in-flight for this buffer. A word write to this
812 * address clears the count.
815 #define BRIDGE_BUF_0_MAX_LATENCY 0x000434
816 #define BRIDGE_BUF_2_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 1)
817 #define BRIDGE_BUF_4_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 2)
818 #define BRIDGE_BUF_6_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 3)
819 #define BRIDGE_BUF_8_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 4)
820 #define BRIDGE_BUF_10_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 5)
821 #define BRIDGE_BUF_12_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 6)
822 #define BRIDGE_BUF_14_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 7)
825 * Buffer (x) Clear All Register
827 * Any access to this register clears all the count values for the (x)
831 #define BRIDGE_BUF_0_CLEAR_ALL 0x00043C
832 #define BRIDGE_BUF_2_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 1)
833 #define BRIDGE_BUF_4_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 2)
834 #define BRIDGE_BUF_6_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 3)
835 #define BRIDGE_BUF_8_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 4)
836 #define BRIDGE_BUF_10_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 5)
837 #define BRIDGE_BUF_12_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 6)
838 #define BRIDGE_BUF_14_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 7)
840 /* end of Performance Monitor Registers */
842 /* Byte offset macros for Bridge I/O space.
844 * NOTE: Where applicable please use the PCIBR_xxx or PCIBRIDGE_xxx
845 * macros (below) as they will handle [X]Bridge and PIC. For example,
846 * PCIBRIDGE_TYPE0_CFG_DEV0() vs BRIDGE_TYPE0_CFG_DEV0
849 #define BRIDGE_ATE_RAM 0x00010000 /* Internal Addr Xlat Ram */
851 #define BRIDGE_TYPE0_CFG_DEV0 0x00020000 /* Type 0 Cfg, Device 0 */
852 #define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000 /* Type 0 Cfg Slot Offset (1..7) */
853 #define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */
854 #define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+\
855 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
856 #define BRIDGE_TYPE0_CFG_DEVF(s,f) (BRIDGE_TYPE0_CFG_DEV0+\
857 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
858 (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
860 #define BRIDGE_TYPE1_CFG 0x00028000 /* Type 1 Cfg space */
862 #define BRIDGE_PCI_IACK 0x00030000 /* PCI Interrupt Ack */
863 #define BRIDGE_EXT_SSRAM 0x00080000 /* Extern SSRAM (ATE) */
865 /* Byte offset macros for Bridge device IO spaces */
867 #define BRIDGE_DEV_CNT 8 /* Up to 8 devices per bridge */
868 #define BRIDGE_DEVIO0 0x00200000 /* Device IO 0 Addr */
869 #define BRIDGE_DEVIO1 0x00400000 /* Device IO 1 Addr */
870 #define BRIDGE_DEVIO2 0x00600000 /* Device IO 2 Addr */
871 #define BRIDGE_DEVIO_OFF 0x00100000 /* Device IO Offset (3..7) */
873 #define BRIDGE_DEVIO_2MB 0x00200000 /* Device IO Offset (0..1) */
874 #define BRIDGE_DEVIO_1MB 0x00100000 /* Device IO Offset (2..7) */
878 #define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
881 * The device space macros for PIC are more complicated because the PIC has
882 * two PCI/X bridges under the same widget. For PIC bus 0, the addresses are
883 * basically the same as for the [X]Bridge. For PIC bus 1, the addresses are
884 * offset by 0x800000. Here are two sets of macros. They are
885 * "PCIBRIDGE_xxx" that return the address based on the supplied bus number
886 * and also equivalent "PCIBR_xxx" macros that may be used with a
887 * pcibr_soft_s structure. Both should work with all bridges.
889 #define PIC_BUS1_OFFSET 0x800000
891 #define PCIBRIDGE_TYPE0_CFG_DEV0(busnum) \
892 ((busnum) ? BRIDGE_TYPE0_CFG_DEV0 + PIC_BUS1_OFFSET : \
893 BRIDGE_TYPE0_CFG_DEV0)
894 #define PCIBRIDGE_TYPE1_CFG(busnum) \
895 ((busnum) ? BRIDGE_TYPE1_CFG + PIC_BUS1_OFFSET : BRIDGE_TYPE1_CFG)
896 #define PCIBRIDGE_TYPE0_CFG_DEV(busnum, s) \
897 (PCIBRIDGE_TYPE0_CFG_DEV0(busnum)+\
898 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
899 #define PCIBRIDGE_TYPE0_CFG_DEVF(busnum, s, f) \
900 (PCIBRIDGE_TYPE0_CFG_DEV0(busnum)+\
901 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
902 (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
903 #define PCIBRIDGE_DEVIO0(busnum) ((busnum) ? \
904 (BRIDGE_DEVIO0 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO0)
905 #define PCIBRIDGE_DEVIO1(busnum) ((busnum) ? \
906 (BRIDGE_DEVIO1 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO1)
907 #define PCIBRIDGE_DEVIO2(busnum) ((busnum) ? \
908 (BRIDGE_DEVIO2 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO2)
909 #define PCIBRIDGE_DEVIO(busnum, x) \
910 ((x)<=1 ? PCIBRIDGE_DEVIO0(busnum)+(x)*BRIDGE_DEVIO_2MB : \
911 PCIBRIDGE_DEVIO2(busnum)+((x)-2)*BRIDGE_DEVIO_1MB)
913 #define PCIBR_BRIDGE_DEVIO0(ps) PCIBRIDGE_DEVIO0((ps)->bs_busnum)
914 #define PCIBR_BRIDGE_DEVIO1(ps) PCIBRIDGE_DEVIO1((ps)->bs_busnum)
915 #define PCIBR_BRIDGE_DEVIO2(ps) PCIBRIDGE_DEVIO2((ps)->bs_busnum)
916 #define PCIBR_BRIDGE_DEVIO(ps, s) PCIBRIDGE_DEVIO((ps)->bs_busnum, s)
918 #define PCIBR_TYPE1_CFG(ps) PCIBRIDGE_TYPE1_CFG((ps)->bs_busnum)
919 #define PCIBR_BUS_TYPE0_CFG_DEV0(ps) PCIBR_TYPE0_CFG_DEV(ps, 0)
920 #define PCIBR_TYPE0_CFG_DEV(ps, s) \
921 ((IS_PIC_SOFT(ps)) ? PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s+1) : \
922 PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s))
923 #define PCIBR_BUS_TYPE0_CFG_DEVF(ps,s,f) \
924 ((IS_PIC_SOFT(ps)) ? PCIBRIDGE_TYPE0_CFG_DEVF((ps)->bs_busnum,(s+1),f) : \
925 PCIBRIDGE_TYPE0_CFG_DEVF((ps)->bs_busnum,s,f))
927 #endif /* LANGUAGE_C */
929 #define BRIDGE_EXTERNAL_FLASH 0x00C00000 /* External Flash PROMS */
931 /* ========================================================================
932 * Bridge register bit field definitions
935 /* Widget part number of bridge */
936 #define BRIDGE_WIDGET_PART_NUM 0xc002
937 #define XBRIDGE_WIDGET_PART_NUM 0xd002
939 /* Manufacturer of bridge */
940 #define BRIDGE_WIDGET_MFGR_NUM 0x036
941 #define XBRIDGE_WIDGET_MFGR_NUM 0x024
943 /* Revision numbers for known [X]Bridge revisions */
944 #define BRIDGE_REV_A 0x1
945 #define BRIDGE_REV_B 0x2
946 #define BRIDGE_REV_C 0x3
947 #define BRIDGE_REV_D 0x4
948 #define XBRIDGE_REV_A 0x1
949 #define XBRIDGE_REV_B 0x2
951 /* macros to determine bridge type. 'wid' == widget identification */
952 #define IS_BRIDGE(wid) (XWIDGET_PART_NUM(wid) == BRIDGE_WIDGET_PART_NUM && \
953 XWIDGET_MFG_NUM(wid) == BRIDGE_WIDGET_MFGR_NUM)
954 #define IS_XBRIDGE(wid) (XWIDGET_PART_NUM(wid) == XBRIDGE_WIDGET_PART_NUM && \
955 XWIDGET_MFG_NUM(wid) == XBRIDGE_WIDGET_MFGR_NUM)
956 #define IS_PIC_BUS0(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS0 && \
957 XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM)
958 #define IS_PIC_BUS1(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS1 && \
959 XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM)
960 #define IS_PIC_BRIDGE(wid) (IS_PIC_BUS0(wid) || IS_PIC_BUS1(wid))
962 /* Part + Rev numbers allows distinction and acscending sequence */
963 #define BRIDGE_PART_REV_A (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_A)
964 #define BRIDGE_PART_REV_B (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_B)
965 #define BRIDGE_PART_REV_C (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_C)
966 #define BRIDGE_PART_REV_D (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_D)
967 #define XBRIDGE_PART_REV_A (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_A)
968 #define XBRIDGE_PART_REV_B (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_B)
970 /* Bridge widget status register bits definition */
971 #define PIC_STAT_PCIX_SPEED (0x3ull << 34)
972 #define PIC_STAT_PCIX_ACTIVE (0x1ull << 33)
973 #define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24)
974 #define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16)
975 #define BRIDGE_STAT_FLASH_SELECT (0x1 << 6)
976 #define BRIDGE_STAT_PCI_GIO_N (0x1 << 5)
977 #define BRIDGE_STAT_PENDING (0x1F << 0)
979 /* Bridge widget control register bits definition */
980 #define PIC_CTRL_NO_SNOOP (0x1ull << 62)
981 #define PIC_CTRL_RELAX_ORDER (0x1ull << 61)
982 #define PIC_CTRL_BUS_NUM(x) ((unsigned long long)(x) << 48)
983 #define PIC_CTRL_BUS_NUM_MASK (PIC_CTRL_BUS_NUM(0xff))
984 #define PIC_CTRL_DEV_NUM(x) ((unsigned long long)(x) << 43)
985 #define PIC_CTRL_DEV_NUM_MASK (PIC_CTRL_DEV_NUM(0x1f))
986 #define PIC_CTRL_FUN_NUM(x) ((unsigned long long)(x) << 40)
987 #define PIC_CTRL_FUN_NUM_MASK (PIC_CTRL_FUN_NUM(0x7))
988 #define PIC_CTRL_PAR_EN_REQ (0x1ull << 29)
989 #define PIC_CTRL_PAR_EN_RESP (0x1ull << 30)
990 #define PIC_CTRL_PAR_EN_ATE (0x1ull << 31)
991 #define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31) /* bridge only */
992 #define BRIDGE_CTRL_EN_CLK50 (0x1 << 30)
993 #define BRIDGE_CTRL_EN_CLK40 (0x1 << 29)
994 #define BRIDGE_CTRL_EN_CLK33 (0x1 << 28)
995 #define BRIDGE_CTRL_RST(n) ((n) << 24)
996 #define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF))
997 #define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x)))
998 #define BRIDGE_CTRL_IO_SWAP (0x1 << 23)
999 #define BRIDGE_CTRL_MEM_SWAP (0x1 << 22)
1000 #define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21)
1001 #define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20)
1002 #define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19)
1003 #define BRIDGE_CTRL_SSRAM_SIZE(n) ((n) << 17)
1004 #define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3))
1005 #define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3))
1006 #define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2))
1007 #define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1))
1008 #define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0))
1009 #define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16)
1010 #define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12)
1011 #define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
1012 #define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11)
1013 #define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10)
1014 #define BRIDGE_CTRL_SYS_END (0x1 << 9)
1015 #define BRIDGE_CTRL_PCI_SPEED (0x3 << 4)
1017 #define BRIDGE_CTRL_BUS_SPEED(n) ((n) << 4)
1018 #define BRIDGE_CTRL_BUS_SPEED_MASK (BRIDGE_CTRL_BUS_SPEED(0x3))
1019 #define BRIDGE_CTRL_BUS_SPEED_33 0x00
1020 #define BRIDGE_CTRL_BUS_SPEED_66 0x10
1021 #define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4)
1022 #define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f))
1023 #define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0)
1024 #define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf))
1026 /* Bridge Response buffer Error Upper Register bit fields definition */
1027 #define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
1028 #define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
1029 #define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
1030 #define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
1031 #define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xFFFF)
1033 #define BRIDGE_RESP_ERRUPPR_BUFNUM(x) \
1034 (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \
1035 BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
1037 #define BRIDGE_RESP_ERRUPPR_DEVICE(x) \
1038 (((x) & BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \
1039 BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
1041 /* Bridge direct mapping register bits definition */
1042 #define BRIDGE_DIRMAP_W_ID_SHFT 20
1043 #define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
1044 #define BRIDGE_DIRMAP_RMF_64 (0x1 << 18)
1045 #define BRIDGE_DIRMAP_ADD512 (0x1 << 17)
1046 #define BRIDGE_DIRMAP_OFF (0x1ffff << 0)
1047 #define BRIDGE_DIRMAP_OFF_ADDRSHFT (31) /* lsbit of DIRMAP_OFF is xtalk address bit 31 */
1049 /* Bridge Arbitration register bits definition */
1050 #define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16)
1051 #define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3)
1052 #define BRIDGE_ARB_REQ_WAIT_EN(x) ((x) << 8)
1053 #define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff)
1054 #define BRIDGE_ARB_FREEZE_GNT (1 << 6)
1055 #define BRIDGE_ARB_HPRI_RING_B2 (1 << 5)
1056 #define BRIDGE_ARB_HPRI_RING_B1 (1 << 4)
1057 #define BRIDGE_ARB_HPRI_RING_B0 (1 << 3)
1058 #define BRIDGE_ARB_LPRI_RING_B2 (1 << 2)
1059 #define BRIDGE_ARB_LPRI_RING_B1 (1 << 1)
1060 #define BRIDGE_ARB_LPRI_RING_B0 (1 << 0)
1062 /* Bridge Bus time-out register bits definition */
1063 #define BRIDGE_BUS_PCI_RETRY_HLD(x) ((x) << 16)
1064 #define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
1065 #define BRIDGE_BUS_GIO_TIMEOUT (1 << 12)
1066 #define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0)
1067 #define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
1069 /* Bridge interrupt status register bits definition */
1070 #define PIC_ISR_PCIX_SPLIT_MSG_PE (0x1ull << 45)
1071 #define PIC_ISR_PCIX_SPLIT_EMSG (0x1ull << 44)
1072 #define PIC_ISR_PCIX_SPLIT_TO (0x1ull << 43)
1073 #define PIC_ISR_PCIX_UNEX_COMP (0x1ull << 42)
1074 #define PIC_ISR_INT_RAM_PERR (0x1ull << 41)
1075 #define PIC_ISR_PCIX_ARB_ERR (0x1ull << 40)
1076 #define PIC_ISR_PCIX_REQ_TOUT (0x1ull << 39)
1077 #define PIC_ISR_PCIX_TABORT (0x1ull << 38)
1078 #define PIC_ISR_PCIX_PERR (0x1ull << 37)
1079 #define PIC_ISR_PCIX_SERR (0x1ull << 36)
1080 #define PIC_ISR_PCIX_MRETRY (0x1ull << 35)
1081 #define PIC_ISR_PCIX_MTOUT (0x1ull << 34)
1082 #define PIC_ISR_PCIX_DA_PARITY (0x1ull << 33)
1083 #define PIC_ISR_PCIX_AD_PARITY (0x1ull << 32)
1084 #define BRIDGE_ISR_MULTI_ERR (0x1u << 31) /* bridge only */
1085 #define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30) /* bridge only */
1086 #define BRIDGE_ISR_PAGE_FAULT (0x1 << 30) /* xbridge only */
1087 #define BRIDGE_ISR_UNEXP_RESP (0x1 << 29)
1088 #define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28)
1089 #define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27)
1090 #define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26)
1091 #define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25)
1092 #define BRIDGE_ISR_INVLD_ADDR (0x1 << 24)
1093 #define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23)
1094 #define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22)
1095 #define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21)
1096 #define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20)
1097 #define BRIDGE_ISR_LLP_RCTY (0x1 << 19)
1098 #define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18)
1099 #define BRIDGE_ISR_LLP_TCTY (0x1 << 17)
1100 #define BRIDGE_ISR_SSRAM_PERR (0x1 << 16)
1101 #define BRIDGE_ISR_PCI_ABORT (0x1 << 15)
1102 #define BRIDGE_ISR_PCI_PARITY (0x1 << 14)
1103 #define BRIDGE_ISR_PCI_SERR (0x1 << 13)
1104 #define BRIDGE_ISR_PCI_PERR (0x1 << 12)
1105 #define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11)
1106 #define BRIDGE_ISR_GIO_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
1107 #define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10)
1108 #define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9)
1109 #define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8)
1110 #define BRIDGE_ISR_INT_MSK (0xff << 0)
1111 #define BRIDGE_ISR_INT(x) (0x1 << (x))
1113 #define BRIDGE_ISR_LINK_ERROR \
1114 (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR| \
1115 BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY| \
1116 BRIDGE_ISR_LLP_TCTY)
1118 #define BRIDGE_ISR_PCIBUS_PIOERR \
1119 (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT| \
1120 PIC_ISR_PCIX_MTOUT|PIC_ISR_PCIX_TABORT)
1122 #define BRIDGE_ISR_PCIBUS_ERROR \
1123 (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR| \
1124 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT| \
1125 BRIDGE_ISR_PCI_PARITY|PIC_ISR_PCIX_PERR| \
1126 PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_MRETRY| \
1127 PIC_ISR_PCIX_AD_PARITY|PIC_ISR_PCIX_DA_PARITY| \
1128 PIC_ISR_PCIX_REQ_TOUT|PIC_ISR_PCIX_UNEX_COMP| \
1129 PIC_ISR_PCIX_SPLIT_TO|PIC_ISR_PCIX_SPLIT_EMSG| \
1130 PIC_ISR_PCIX_SPLIT_MSG_PE)
1132 #define BRIDGE_ISR_XTALK_ERROR \
1133 (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\
1134 BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR| \
1135 BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR| \
1136 BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT| \
1137 BRIDGE_ISR_UNEXP_RESP)
1139 #define BRIDGE_ISR_ERRORS \
1140 (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| \
1141 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \
1142 BRIDGE_ISR_PMU_ESIZE_FAULT|PIC_ISR_INT_RAM_PERR)
1145 * List of Errors which are fatal and kill the sytem
1147 #define BRIDGE_ISR_ERROR_FATAL \
1148 ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\
1149 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY| \
1150 PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_AD_PARITY| \
1151 PIC_ISR_PCIX_DA_PARITY| \
1152 PIC_ISR_INT_RAM_PERR|PIC_ISR_PCIX_SPLIT_MSG_PE )
1154 #define BRIDGE_ISR_ERROR_DUMP \
1155 (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT| \
1156 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \
1157 PIC_ISR_PCIX_ARB_ERR|PIC_ISR_INT_RAM_PERR)
1159 /* Bridge interrupt enable register bits definition */
1160 #define PIC_IMR_PCIX_SPLIT_MSG_PE PIC_ISR_PCIX_SPLIT_MSG_PE
1161 #define PIC_IMR_PCIX_SPLIT_EMSG PIC_ISR_PCIX_SPLIT_EMSG
1162 #define PIC_IMR_PCIX_SPLIT_TO PIC_ISR_PCIX_SPLIT_TO
1163 #define PIC_IMR_PCIX_UNEX_COMP PIC_ISR_PCIX_UNEX_COMP
1164 #define PIC_IMR_INT_RAM_PERR PIC_ISR_INT_RAM_PERR
1165 #define PIC_IMR_PCIX_ARB_ERR PIC_ISR_PCIX_ARB_ERR
1166 #define PIC_IMR_PCIX_REQ_TOUR PIC_ISR_PCIX_REQ_TOUT
1167 #define PIC_IMR_PCIX_TABORT PIC_ISR_PCIX_TABORT
1168 #define PIC_IMR_PCIX_PERR PIC_ISR_PCIX_PERR
1169 #define PIC_IMR_PCIX_SERR PIC_ISR_PCIX_SERR
1170 #define PIC_IMR_PCIX_MRETRY PIC_ISR_PCIX_MRETRY
1171 #define PIC_IMR_PCIX_MTOUT PIC_ISR_PCIX_MTOUT
1172 #define PIC_IMR_PCIX_DA_PARITY PIC_ISR_PCIX_DA_PARITY
1173 #define PIC_IMR_PCIX_AD_PARITY PIC_ISR_PCIX_AD_PARITY
1174 #define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP
1175 #define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT
1176 #define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT
1177 #define BRIDGE_IMR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT
1178 #define BRIDGE_IMR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR
1179 #define BRIDGE_IMR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR
1180 #define BRIDGE_IMR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR
1181 #define BRIDGE_IMR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP
1182 #define BRIDGE_IMR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW
1183 #define BRIDGE_IMR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR
1184 #define BRIDGE_IMR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR
1185 #define BRIDGE_IMR_LLP_RCTY BRIDGE_ISR_LLP_RCTY
1186 #define BRIDGE_IMR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY
1187 #define BRIDGE_IMR_LLP_TCTY BRIDGE_ISR_LLP_TCTY
1188 #define BRIDGE_IMR_SSRAM_PERR BRIDGE_ISR_SSRAM_PERR
1189 #define BRIDGE_IMR_PCI_ABORT BRIDGE_ISR_PCI_ABORT
1190 #define BRIDGE_IMR_PCI_PARITY BRIDGE_ISR_PCI_PARITY
1191 #define BRIDGE_IMR_PCI_SERR BRIDGE_ISR_PCI_SERR
1192 #define BRIDGE_IMR_PCI_PERR BRIDGE_ISR_PCI_PERR
1193 #define BRIDGE_IMR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
1194 #define BRIDGE_IMR_GIO_MST_TIMEOUT BRIDGE_ISR_GIO_MST_TIMEOUT
1195 #define BRIDGE_IMR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT
1196 #define BRIDGE_IMR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT
1197 #define BRIDGE_IMR_GIO_B_ENBL_ERR BRIDGE_ISR_GIO_B_ENBL_ERR
1198 #define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK
1199 #define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x)
1202 * Bridge interrupt reset register bits definition. Note, PIC can
1203 * reset indiviual error interrupts, BRIDGE & XBRIDGE can only do
1206 #define PIC_IRR_PCIX_SPLIT_MSG_PE PIC_ISR_PCIX_SPLIT_MSG_PE
1207 #define PIC_IRR_PCIX_SPLIT_EMSG PIC_ISR_PCIX_SPLIT_EMSG
1208 #define PIC_IRR_PCIX_SPLIT_TO PIC_ISR_PCIX_SPLIT_TO
1209 #define PIC_IRR_PCIX_UNEX_COMP PIC_ISR_PCIX_UNEX_COMP
1210 #define PIC_IRR_INT_RAM_PERR PIC_ISR_INT_RAM_PERR
1211 #define PIC_IRR_PCIX_ARB_ERR PIC_ISR_PCIX_ARB_ERR
1212 #define PIC_IRR_PCIX_REQ_TOUT PIC_ISR_PCIX_REQ_TOUT
1213 #define PIC_IRR_PCIX_TABORT PIC_ISR_PCIX_TABORT
1214 #define PIC_IRR_PCIX_PERR PIC_ISR_PCIX_PERR
1215 #define PIC_IRR_PCIX_SERR PIC_ISR_PCIX_SERR
1216 #define PIC_IRR_PCIX_MRETRY PIC_ISR_PCIX_MRETRY
1217 #define PIC_IRR_PCIX_MTOUT PIC_ISR_PCIX_MTOUT
1218 #define PIC_IRR_PCIX_DA_PARITY PIC_ISR_PCIX_DA_PARITY
1219 #define PIC_IRR_PCIX_AD_PARITY PIC_ISR_PCIX_AD_PARITY
1220 #define PIC_IRR_PAGE_FAULT BRIDGE_ISR_PAGE_FAULT
1221 #define PIC_IRR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP
1222 #define PIC_IRR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT
1223 #define PIC_IRR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT
1224 #define PIC_IRR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR
1225 #define PIC_IRR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR
1226 #define PIC_IRR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR
1227 #define PIC_IRR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP
1228 #define PIC_IRR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW
1229 #define PIC_IRR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR
1230 #define PIC_IRR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR
1231 #define PIC_IRR_LLP_RCTY BRIDGE_ISR_LLP_RCTY
1232 #define PIC_IRR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY
1233 #define PIC_IRR_LLP_TCTY BRIDGE_ISR_LLP_TCTY
1234 #define PIC_IRR_PCI_ABORT BRIDGE_ISR_PCI_ABORT
1235 #define PIC_IRR_PCI_PARITY BRIDGE_ISR_PCI_PARITY
1236 #define PIC_IRR_PCI_SERR BRIDGE_ISR_PCI_SERR
1237 #define PIC_IRR_PCI_PERR BRIDGE_ISR_PCI_PERR
1238 #define PIC_IRR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
1239 #define PIC_IRR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT
1240 #define PIC_IRR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT
1241 #define BRIDGE_IRR_MULTI_CLR (0x1 << 6)
1242 #define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5)
1243 #define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4)
1244 #define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3)
1245 #define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2)
1246 #define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1)
1247 #define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0)
1248 #define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0)
1249 #define BRIDGE_IRR_ALL_CLR 0x7f
1251 #define BRIDGE_IRR_CRP_GRP (BRIDGE_ISR_UNEXP_RESP | \
1252 BRIDGE_ISR_XREQ_FIFO_OFLOW)
1253 #define BRIDGE_IRR_RESP_BUF_GRP (BRIDGE_ISR_BAD_XRESP_PKT | \
1254 BRIDGE_ISR_RESP_XTLK_ERR | \
1255 BRIDGE_ISR_XREAD_REQ_TIMEOUT)
1256 #define BRIDGE_IRR_REQ_DSP_GRP (BRIDGE_ISR_UNSUPPORTED_XOP | \
1257 BRIDGE_ISR_BAD_XREQ_PKT | \
1258 BRIDGE_ISR_REQ_XTLK_ERR | \
1259 BRIDGE_ISR_INVLD_ADDR)
1260 #define BRIDGE_IRR_LLP_GRP (BRIDGE_ISR_LLP_REC_SNERR | \
1261 BRIDGE_ISR_LLP_REC_CBERR | \
1262 BRIDGE_ISR_LLP_RCTY | \
1263 BRIDGE_ISR_LLP_TX_RETRY | \
1264 BRIDGE_ISR_LLP_TCTY)
1265 #define BRIDGE_IRR_SSRAM_GRP (BRIDGE_ISR_SSRAM_PERR | \
1266 BRIDGE_ISR_PMU_ESIZE_FAULT)
1267 #define BRIDGE_IRR_PCI_GRP (BRIDGE_ISR_PCI_ABORT | \
1268 BRIDGE_ISR_PCI_PARITY | \
1269 BRIDGE_ISR_PCI_SERR | \
1270 BRIDGE_ISR_PCI_PERR | \
1271 BRIDGE_ISR_PCI_MST_TIMEOUT | \
1272 BRIDGE_ISR_PCI_RETRY_CNT)
1274 #define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | \
1275 BRIDGE_ISR_GIO_MST_TIMEOUT)
1277 #define PIC_IRR_RAM_GRP PIC_ISR_INT_RAM_PERR
1279 #define PIC_PCIX_GRP_CLR (PIC_IRR_PCIX_AD_PARITY | \
1280 PIC_IRR_PCIX_DA_PARITY | \
1281 PIC_IRR_PCIX_MTOUT | \
1282 PIC_IRR_PCIX_MRETRY | \
1283 PIC_IRR_PCIX_SERR | \
1284 PIC_IRR_PCIX_PERR | \
1285 PIC_IRR_PCIX_TABORT | \
1286 PIC_ISR_PCIX_REQ_TOUT | \
1287 PIC_ISR_PCIX_UNEX_COMP | \
1288 PIC_ISR_PCIX_SPLIT_TO | \
1289 PIC_ISR_PCIX_SPLIT_EMSG | \
1290 PIC_ISR_PCIX_SPLIT_MSG_PE)
1292 /* Bridge INT_DEV register bits definition */
1293 #define BRIDGE_INT_DEV_SHFT(n) ((n)*3)
1294 #define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n))
1295 #define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
1297 /* Bridge interrupt(x) register bits definition */
1298 #define BRIDGE_INT_ADDR_HOST 0x0003FF00
1299 #define BRIDGE_INT_ADDR_FLD 0x000000FF
1301 /* PIC interrupt(x) register bits definition */
1302 #define PIC_INT_ADDR_FLD 0x00FF000000000000
1303 #define PIC_INT_ADDR_HOST 0x0000FFFFFFFFFFFF
1305 #define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000
1306 #define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000
1307 #define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff
1309 #define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff
1311 /* Bridge device(x) register bits definition */
1312 #define BRIDGE_DEV_ERR_LOCK_EN (1ull << 28)
1313 #define BRIDGE_DEV_PAGE_CHK_DIS (1ull << 27)
1314 #define BRIDGE_DEV_FORCE_PCI_PAR (1ull << 26)
1315 #define BRIDGE_DEV_VIRTUAL_EN (1ull << 25)
1316 #define BRIDGE_DEV_PMU_WRGA_EN (1ull << 24)
1317 #define BRIDGE_DEV_DIR_WRGA_EN (1ull << 23)
1318 #define BRIDGE_DEV_DEV_SIZE (1ull << 22)
1319 #define BRIDGE_DEV_RT (1ull << 21)
1320 #define BRIDGE_DEV_SWAP_PMU (1ull << 20)
1321 #define BRIDGE_DEV_SWAP_DIR (1ull << 19)
1322 #define BRIDGE_DEV_PREF (1ull << 18)
1323 #define BRIDGE_DEV_PRECISE (1ull << 17)
1324 #define BRIDGE_DEV_COH (1ull << 16)
1325 #define BRIDGE_DEV_BARRIER (1ull << 15)
1326 #define BRIDGE_DEV_GBR (1ull << 14)
1327 #define BRIDGE_DEV_DEV_SWAP (1ull << 13)
1328 #define BRIDGE_DEV_DEV_IO_MEM (1ull << 12)
1329 #define BRIDGE_DEV_OFF_MASK 0x00000fff
1330 #define BRIDGE_DEV_OFF_ADDR_SHFT 20
1332 #define XBRIDGE_DEV_PMU_BITS BRIDGE_DEV_PMU_WRGA_EN
1333 #define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN | \
1334 BRIDGE_DEV_SWAP_PMU)
1335 #define BRIDGE_DEV_D32_BITS (BRIDGE_DEV_DIR_WRGA_EN | \
1336 BRIDGE_DEV_SWAP_DIR | \
1338 BRIDGE_DEV_PRECISE | \
1341 #define XBRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | \
1344 #define BRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | \
1345 BRIDGE_DEV_SWAP_DIR | \
1349 /* Bridge Error Upper register bit field definition */
1350 #define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20) /* Device was master */
1351 #define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19) /* Virtual Req value */
1352 #define BRIDGE_ERRUPPR_DEVNUM_SHFT (16)
1353 #define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
1354 #define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
1355 #define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF)
1357 /* Bridge interrupt mode register bits definition */
1358 #define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x))
1360 /* this should be written to the xbow's link_control(x) register */
1361 #define BRIDGE_CREDIT 3
1363 /* RRB assignment register */
1364 #define BRIDGE_RRB_EN 0x8 /* after shifting down */
1365 #define BRIDGE_RRB_DEV 0x7 /* after shifting down */
1366 #define BRIDGE_RRB_VDEV 0x4 /* after shifting down, 2 virtual channels */
1367 #define BRIDGE_RRB_PDEV 0x3 /* after shifting down, 8 devices */
1369 #define PIC_RRB_EN 0x8 /* after shifting down */
1370 #define PIC_RRB_DEV 0x7 /* after shifting down */
1371 #define PIC_RRB_VDEV 0x6 /* after shifting down, 4 virtual channels */
1372 #define PIC_RRB_PDEV 0x1 /* after shifting down, 4 devices */
1374 /* RRB status register */
1375 #define BRIDGE_RRB_VALID(r) (0x00010000<<(r))
1376 #define BRIDGE_RRB_INUSE(r) (0x00000001<<(r))
1378 /* RRB clear register */
1379 #define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r))
1381 /* Defines for the virtual channels so we don't hardcode 0-3 within code */
1382 #define VCHAN0 0 /* virtual channel 0 (ie. the "normal" channel) */
1383 #define VCHAN1 1 /* virtual channel 1 */
1384 #define VCHAN2 2 /* virtual channel 2 - PIC only */
1385 #define VCHAN3 3 /* virtual channel 3 - PIC only */
1387 /* PIC: PCI-X Read Buffer Attribute Register (RBAR) */
1388 #define NUM_RBAR 16 /* number of RBAR registers */
1390 /* xbox system controller declarations */
1391 #define XBOX_BRIDGE_WID 8
1392 #define FLASH_PROM1_BASE 0xE00000 /* To read the xbox sysctlr status */
1393 #define XBOX_RPS_EXISTS 1 << 6 /* RPS bit in status register */
1394 #define XBOX_RPS_FAIL 1 << 4 /* RPS status bit in register */
1396 /* ========================================================================
1399 * Macros for Xtalk to Bridge bus (PCI/GIO) PIO
1400 * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings
1402 /* XTALK addresses that map into Bridge Bus addr space */
1403 #define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L
1404 #define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL
1405 #define BRIDGE_PIO64_XTALK_ALIAS_BASE 0x000080000000L
1406 #define BRIDGE_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL
1407 #define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L
1408 #define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL
1410 /* Ranges of PCI bus space that can be accessed via PIO from xtalk */
1411 #define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000 /* 1G PCI memory space */
1412 #define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff
1413 #define BRIDGE_MIN_PIO_ADDR_IO 0x00000000 /* 4G PCI IO space */
1414 #define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff
1416 /* XTALK addresses that map into PCI addresses */
1417 #define BRIDGE_PCI_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
1418 #define BRIDGE_PCI_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT
1419 #define BRIDGE_PCI_MEM64_BASE BRIDGE_PIO64_XTALK_ALIAS_BASE
1420 #define BRIDGE_PCI_MEM64_LIMIT BRIDGE_PIO64_XTALK_ALIAS_LIMIT
1421 #define BRIDGE_PCI_IO_BASE BRIDGE_PCIIO_XTALK_ALIAS_BASE
1422 #define BRIDGE_PCI_IO_LIMIT BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
1425 * Macros for Xtalk to Bridge bus (PCI) PIO
1426 * refer to section 5.2.1 Figure 4 of the "PCI Interface Chip (PIC) Volume II
1427 * Programmer's Reference" (Revision 0.8 as of this writing).
1429 * These are PIC bridge specific. A separate set of macros was defined
1430 * because PIC deviates from Bridge/Xbridge by not supporting a big-window
1431 * alias for PCI I/O space, and also redefines XTALK addresses
1432 * 0x0000C0000000L and 0x000100000000L to be PCI MEM aliases for the second
1436 /* XTALK addresses that map into PIC Bridge Bus addr space */
1437 #define PICBRIDGE0_PIO32_XTALK_ALIAS_BASE 0x000040000000L
1438 #define PICBRIDGE0_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL
1439 #define PICBRIDGE0_PIO64_XTALK_ALIAS_BASE 0x000080000000L
1440 #define PICBRIDGE0_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL
1441 #define PICBRIDGE1_PIO32_XTALK_ALIAS_BASE 0x0000C0000000L
1442 #define PICBRIDGE1_PIO32_XTALK_ALIAS_LIMIT 0x0000FFFFFFFFL
1443 #define PICBRIDGE1_PIO64_XTALK_ALIAS_BASE 0x000100000000L
1444 #define PICBRIDGE1_PIO64_XTALK_ALIAS_LIMIT 0x00013FFFFFFFL
1446 /* XTALK addresses that map into PCI addresses */
1447 #define PICBRIDGE0_PCI_MEM32_BASE PICBRIDGE0_PIO32_XTALK_ALIAS_BASE
1448 #define PICBRIDGE0_PCI_MEM32_LIMIT PICBRIDGE0_PIO32_XTALK_ALIAS_LIMIT
1449 #define PICBRIDGE0_PCI_MEM64_BASE PICBRIDGE0_PIO64_XTALK_ALIAS_BASE
1450 #define PICBRIDGE0_PCI_MEM64_LIMIT PICBRIDGE0_PIO64_XTALK_ALIAS_LIMIT
1451 #define PICBRIDGE1_PCI_MEM32_BASE PICBRIDGE1_PIO32_XTALK_ALIAS_BASE
1452 #define PICBRIDGE1_PCI_MEM32_LIMIT PICBRIDGE1_PIO32_XTALK_ALIAS_LIMIT
1453 #define PICBRIDGE1_PCI_MEM64_BASE PICBRIDGE1_PIO64_XTALK_ALIAS_BASE
1454 #define PICBRIDGE1_PCI_MEM64_LIMIT PICBRIDGE1_PIO64_XTALK_ALIAS_LIMIT
1457 * Macros for Bridge bus (PCI/GIO) to Xtalk DMA
1459 /* Bridge Bus DMA addresses */
1460 #define BRIDGE_LOCAL_BASE 0
1461 #define BRIDGE_DMA_MAPPED_BASE 0x40000000
1462 #define BRIDGE_DMA_MAPPED_SIZE 0x40000000 /* 1G Bytes */
1463 #define BRIDGE_DMA_DIRECT_BASE 0x80000000
1464 #define BRIDGE_DMA_DIRECT_SIZE 0x80000000 /* 2G Bytes */
1466 #define PCI32_LOCAL_BASE BRIDGE_LOCAL_BASE
1468 /* PCI addresses of regions decoded by Bridge for DMA */
1469 #define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE
1470 #define PCI32_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE
1472 #ifndef __ASSEMBLY__
1474 #define IS_PCI32_LOCAL(x) ((uint64_t)(x) < PCI32_MAPPED_BASE)
1475 #define IS_PCI32_MAPPED(x) ((uint64_t)(x) < PCI32_DIRECT_BASE && \
1476 (uint64_t)(x) >= PCI32_MAPPED_BASE)
1477 #define IS_PCI32_DIRECT(x) ((uint64_t)(x) >= PCI32_MAPPED_BASE)
1478 #define IS_PCI64(x) ((uint64_t)(x) >= PCI64_BASE)
1479 #endif /* __ASSEMBLY__ */
1482 * The GIO address space.
1484 /* Xtalk to GIO PIO */
1485 #define BRIDGE_GIO_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
1486 #define BRIDGE_GIO_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT
1488 #define GIO_LOCAL_BASE BRIDGE_LOCAL_BASE
1490 /* GIO addresses of regions decoded by Bridge for DMA */
1491 #define GIO_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE
1492 #define GIO_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE
1494 #ifndef __ASSEMBLY__
1496 #define IS_GIO_LOCAL(x) ((uint64_t)(x) < GIO_MAPPED_BASE)
1497 #define IS_GIO_MAPPED(x) ((uint64_t)(x) < GIO_DIRECT_BASE && \
1498 (uint64_t)(x) >= GIO_MAPPED_BASE)
1499 #define IS_GIO_DIRECT(x) ((uint64_t)(x) >= GIO_MAPPED_BASE)
1500 #endif /* __ASSEMBLY__ */
1502 /* PCI to xtalk mapping */
1504 /* given a DIR_OFF value and a pci/gio 32 bits direct address, determine
1505 * which xtalk address is accessed
1507 #define BRIDGE_DIRECT_32_SEG_SIZE BRIDGE_DMA_DIRECT_SIZE
1508 #define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr) \
1509 ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE + \
1510 ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
1512 /* 64-bit address attribute masks */
1513 #define PCI64_ATTR_TARG_MASK 0xf000000000000000
1514 #define PCI64_ATTR_TARG_SHFT 60
1515 #define PCI64_ATTR_PREF (1ull << 59)
1516 #define PCI64_ATTR_PREC (1ull << 58)
1517 #define PCI64_ATTR_VIRTUAL (1ull << 57)
1518 #define PCI64_ATTR_BAR (1ull << 56)
1519 #define PCI64_ATTR_SWAP (1ull << 55)
1520 #define PCI64_ATTR_RMF_MASK 0x00ff000000000000
1521 #define PCI64_ATTR_RMF_SHFT 48
1523 #ifndef __ASSEMBLY__
1524 /* Address translation entry for mapped pci32 accesses */
1525 typedef union ate_u {
1527 struct xb_ate_s { /* xbridge */
1531 uint64_t reserved:2;
1534 uint64_t prefetch:1;
1536 uint64_t coherent:1;
1539 struct ate_s { /* bridge */
1543 uint64_t reserved:3;
1545 uint64_t prefetch:1;
1547 uint64_t coherent:1;
1551 #endif /* __ASSEMBLY__ */
1553 #define ATE_V (1 << 0)
1554 #define ATE_CO (1 << 1)
1555 #define ATE_PREC (1 << 2)
1556 #define ATE_PREF (1 << 3)
1557 #define ATE_BAR (1 << 4)
1558 #define ATE_SWAP (1 << 5)
1560 #define ATE_PFNSHIFT 12
1561 #define ATE_TIDSHIFT 8
1562 #define ATE_RMFSHIFT 48
1564 #define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \
1565 ((xid)<<ATE_TIDSHIFT) | \
1569 * for xbridge, bit 29 of the pci address is the swap bit */
1570 #define ATE_SWAPSHIFT 29
1571 #define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT))
1572 #define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT))
1574 /* extern declarations */
1576 #ifndef __ASSEMBLY__
1578 /* ========================================================================
1581 #ifdef MACROFIELD_LINE
1583 * This table forms a relation between the byte offset macros normally
1584 * used for ASM coding and the calculated byte offsets of the fields
1585 * in the C structure.
1587 * See bridge_check.c and bridge_html.c for further details.
1589 #ifndef MACROFIELD_LINE_BITFIELD
1590 #define MACROFIELD_LINE_BITFIELD(m) /* ignored */
1593 struct macrofield_s bridge_macrofield[] =
1596 MACROFIELD_LINE(BRIDGE_WID_ID, b_wid_id)
1597 MACROFIELD_LINE_BITFIELD(WIDGET_REV_NUM)
1598 MACROFIELD_LINE_BITFIELD(WIDGET_PART_NUM)
1599 MACROFIELD_LINE_BITFIELD(WIDGET_MFG_NUM)
1600 MACROFIELD_LINE(BRIDGE_WID_STAT, b_wid_stat)
1601 MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_REC_CNT)
1602 MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_TX_CNT)
1603 MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_FLASH_SELECT)
1604 MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PCI_GIO_N)
1605 MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PENDING)
1606 MACROFIELD_LINE(BRIDGE_WID_ERR_UPPER, b_wid_err_upper)
1607 MACROFIELD_LINE(BRIDGE_WID_ERR_LOWER, b_wid_err_lower)
1608 MACROFIELD_LINE(BRIDGE_WID_CONTROL, b_wid_control)
1609 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_FLASH_WR_EN)
1610 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK50)
1611 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK40)
1612 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK33)
1613 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_RST_MASK)
1614 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_IO_SWAP)
1615 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MEM_SWAP)
1616 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_PAGE_SIZE)
1617 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_BAD)
1618 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_EN)
1619 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SSRAM_SIZE_MASK)
1620 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_F_BAD_PKT)
1621 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_LLP_XBAR_CRD_MASK)
1622 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_RLLP_CNT)
1623 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_TLLP_CNT)
1624 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SYS_END)
1625 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MAX_TRANS_MASK)
1626 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_WIDGET_ID_MASK)
1627 MACROFIELD_LINE(BRIDGE_WID_REQ_TIMEOUT, b_wid_req_timeout)
1628 MACROFIELD_LINE(BRIDGE_WID_INT_UPPER, b_wid_int_upper)
1629 MACROFIELD_LINE_BITFIELD(WIDGET_INT_VECTOR)
1630 MACROFIELD_LINE_BITFIELD(WIDGET_TARGET_ID)
1631 MACROFIELD_LINE_BITFIELD(WIDGET_UPP_ADDR)
1632 MACROFIELD_LINE(BRIDGE_WID_INT_LOWER, b_wid_int_lower)
1633 MACROFIELD_LINE(BRIDGE_WID_ERR_CMDWORD, b_wid_err_cmdword)
1634 MACROFIELD_LINE_BITFIELD(WIDGET_DIDN)
1635 MACROFIELD_LINE_BITFIELD(WIDGET_SIDN)
1636 MACROFIELD_LINE_BITFIELD(WIDGET_PACTYP)
1637 MACROFIELD_LINE_BITFIELD(WIDGET_TNUM)
1638 MACROFIELD_LINE_BITFIELD(WIDGET_COHERENT)
1639 MACROFIELD_LINE_BITFIELD(WIDGET_DS)
1640 MACROFIELD_LINE_BITFIELD(WIDGET_GBR)
1641 MACROFIELD_LINE_BITFIELD(WIDGET_VBPM)
1642 MACROFIELD_LINE_BITFIELD(WIDGET_ERROR)
1643 MACROFIELD_LINE_BITFIELD(WIDGET_BARRIER)
1644 MACROFIELD_LINE(BRIDGE_WID_LLP, b_wid_llp)
1645 MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXRETRY)
1646 MACROFIELD_LINE_BITFIELD(WIDGET_LLP_NULLTIMEOUT)
1647 MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXBURST)
1648 MACROFIELD_LINE(BRIDGE_WID_TFLUSH, b_wid_tflush)
1649 MACROFIELD_LINE(BRIDGE_WID_AUX_ERR, b_wid_aux_err)
1650 MACROFIELD_LINE(BRIDGE_WID_RESP_UPPER, b_wid_resp_upper)
1651 MACROFIELD_LINE(BRIDGE_WID_RESP_LOWER, b_wid_resp_lower)
1652 MACROFIELD_LINE(BRIDGE_WID_TST_PIN_CTRL, b_wid_tst_pin_ctrl)
1653 MACROFIELD_LINE(BRIDGE_DIR_MAP, b_dir_map)
1654 MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_W_ID)
1655 MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_RMF_64)
1656 MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_ADD512)
1657 MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_OFF)
1658 MACROFIELD_LINE(BRIDGE_RAM_PERR, b_ram_perr)
1659 MACROFIELD_LINE(BRIDGE_ARB, b_arb)
1660 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_TICK_MASK)
1661 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_EN_MASK)
1662 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_FREEZE_GNT)
1663 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B2)
1664 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B1)
1665 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B0)
1666 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B2)
1667 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B1)
1668 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B0)
1669 MACROFIELD_LINE(BRIDGE_NIC, b_nic)
1670 MACROFIELD_LINE(BRIDGE_PCI_BUS_TIMEOUT, b_pci_bus_timeout)
1671 MACROFIELD_LINE(BRIDGE_PCI_CFG, b_pci_cfg)
1672 MACROFIELD_LINE(BRIDGE_PCI_ERR_UPPER, b_pci_err_upper)
1673 MACROFIELD_LINE(BRIDGE_PCI_ERR_LOWER, b_pci_err_lower)
1674 MACROFIELD_LINE(BRIDGE_INT_STATUS, b_int_status)
1675 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_MULTI_ERR)
1676 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PMU_ESIZE_FAULT)
1677 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_UNEXP_RESP)
1678 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_BAD_XRESP_PKT)
1679 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_BAD_XREQ_PKT)
1680 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_RESP_XTLK_ERR)
1681 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_REQ_XTLK_ERR)
1682 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_INVLD_ADDR)
1683 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_UNSUPPORTED_XOP)
1684 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_XREQ_FIFO_OFLOW)
1685 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_REC_SNERR)
1686 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_REC_CBERR)
1687 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_RCTY)
1688 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_TX_RETRY)
1689 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_TCTY)
1690 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_SSRAM_PERR)
1691 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_ABORT)
1692 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_PARITY)
1693 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_SERR)
1694 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_PERR)
1695 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_MST_TIMEOUT)
1696 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_RETRY_CNT)
1697 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_XREAD_REQ_TIMEOUT)
1698 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_GIO_B_ENBL_ERR)
1699 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_INT_MSK)
1700 MACROFIELD_LINE(BRIDGE_INT_ENABLE, b_int_enable)
1701 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_UNEXP_RESP)
1702 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PMU_ESIZE_FAULT)
1703 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_BAD_XRESP_PKT)
1704 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_BAD_XREQ_PKT)
1705 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_RESP_XTLK_ERR)
1706 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_REQ_XTLK_ERR)
1707 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_INVLD_ADDR)
1708 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_UNSUPPORTED_XOP)
1709 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_XREQ_FIFO_OFLOW)
1710 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_REC_SNERR)
1711 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_REC_CBERR)
1712 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_RCTY)
1713 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_TX_RETRY)
1714 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_TCTY)
1715 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_SSRAM_PERR)
1716 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_ABORT)
1717 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_PARITY)
1718 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_SERR)
1719 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_PERR)
1720 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_MST_TIMEOUT)
1721 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_RETRY_CNT)
1722 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_XREAD_REQ_TIMEOUT)
1723 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_GIO_B_ENBL_ERR)
1724 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_INT_MSK)
1725 MACROFIELD_LINE(BRIDGE_INT_RST_STAT, b_int_rst_stat)
1726 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_ALL_CLR)
1727 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_MULTI_CLR)
1728 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_CRP_GRP_CLR)
1729 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_RESP_BUF_GRP_CLR)
1730 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_REQ_DSP_GRP_CLR)
1731 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_LLP_GRP_CLR)
1732 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_SSRAM_GRP_CLR)
1733 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_PCI_GRP_CLR)
1734 MACROFIELD_LINE(BRIDGE_INT_MODE, b_int_mode)
1735 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(7))
1736 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(6))
1737 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(5))
1738 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(4))
1739 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(3))
1740 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(2))
1741 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(1))
1742 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(0))
1743 MACROFIELD_LINE(BRIDGE_INT_DEVICE, b_int_device)
1744 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(7))
1745 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(6))
1746 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(5))
1747 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(4))
1748 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(3))
1749 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(2))
1750 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(1))
1751 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(0))
1752 MACROFIELD_LINE(BRIDGE_INT_HOST_ERR, b_int_host_err)
1753 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_ADDR_HOST)
1754 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_ADDR_FLD)
1755 MACROFIELD_LINE(BRIDGE_INT_ADDR0, b_int_addr[0].addr)
1756 MACROFIELD_LINE(BRIDGE_INT_ADDR(0), b_int_addr[0].addr)
1757 MACROFIELD_LINE(BRIDGE_INT_ADDR(1), b_int_addr[1].addr)
1758 MACROFIELD_LINE(BRIDGE_INT_ADDR(2), b_int_addr[2].addr)
1759 MACROFIELD_LINE(BRIDGE_INT_ADDR(3), b_int_addr[3].addr)
1760 MACROFIELD_LINE(BRIDGE_INT_ADDR(4), b_int_addr[4].addr)
1761 MACROFIELD_LINE(BRIDGE_INT_ADDR(5), b_int_addr[5].addr)
1762 MACROFIELD_LINE(BRIDGE_INT_ADDR(6), b_int_addr[6].addr)
1763 MACROFIELD_LINE(BRIDGE_INT_ADDR(7), b_int_addr[7].addr)
1764 MACROFIELD_LINE(BRIDGE_DEVICE0, b_device[0].reg)
1765 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_ERR_LOCK_EN)
1766 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PAGE_CHK_DIS)
1767 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_FORCE_PCI_PAR)
1768 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_VIRTUAL_EN)
1769 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PMU_WRGA_EN)
1770 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DIR_WRGA_EN)
1771 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_SIZE)
1772 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_RT)
1773 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_SWAP_PMU)
1774 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_SWAP_DIR)
1775 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PREF)
1776 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PRECISE)
1777 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_COH)
1778 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_BARRIER)
1779 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_GBR)
1780 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_SWAP)
1781 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_IO_MEM)
1782 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_OFF_MASK)
1783 MACROFIELD_LINE(BRIDGE_DEVICE(0), b_device[0].reg)
1784 MACROFIELD_LINE(BRIDGE_DEVICE(1), b_device[1].reg)
1785 MACROFIELD_LINE(BRIDGE_DEVICE(2), b_device[2].reg)
1786 MACROFIELD_LINE(BRIDGE_DEVICE(3), b_device[3].reg)
1787 MACROFIELD_LINE(BRIDGE_DEVICE(4), b_device[4].reg)
1788 MACROFIELD_LINE(BRIDGE_DEVICE(5), b_device[5].reg)
1789 MACROFIELD_LINE(BRIDGE_DEVICE(6), b_device[6].reg)
1790 MACROFIELD_LINE(BRIDGE_DEVICE(7), b_device[7].reg)
1791 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF0, b_wr_req_buf[0].reg)
1792 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(0), b_wr_req_buf[0].reg)
1793 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(1), b_wr_req_buf[1].reg)
1794 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(2), b_wr_req_buf[2].reg)
1795 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(3), b_wr_req_buf[3].reg)
1796 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(4), b_wr_req_buf[4].reg)
1797 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(5), b_wr_req_buf[5].reg)
1798 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(6), b_wr_req_buf[6].reg)
1799 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(7), b_wr_req_buf[7].reg)
1800 MACROFIELD_LINE(BRIDGE_EVEN_RESP, b_even_resp)
1801 MACROFIELD_LINE(BRIDGE_ODD_RESP, b_odd_resp)
1802 MACROFIELD_LINE(BRIDGE_RESP_STATUS, b_resp_status)
1803 MACROFIELD_LINE(BRIDGE_RESP_CLEAR, b_resp_clear)
1804 MACROFIELD_LINE(BRIDGE_ATE_RAM, b_int_ate_ram)
1805 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV0, b_type0_cfg_dev[0])
1807 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(0), b_type0_cfg_dev[0])
1808 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,0), b_type0_cfg_dev[0].f[0])
1809 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,1), b_type0_cfg_dev[0].f[1])
1810 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,2), b_type0_cfg_dev[0].f[2])
1811 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,3), b_type0_cfg_dev[0].f[3])
1812 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,4), b_type0_cfg_dev[0].f[4])
1813 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,5), b_type0_cfg_dev[0].f[5])
1814 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,6), b_type0_cfg_dev[0].f[6])
1815 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,7), b_type0_cfg_dev[0].f[7])
1816 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(1), b_type0_cfg_dev[1])
1817 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,0), b_type0_cfg_dev[1].f[0])
1818 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,1), b_type0_cfg_dev[1].f[1])
1819 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,2), b_type0_cfg_dev[1].f[2])
1820 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,3), b_type0_cfg_dev[1].f[3])
1821 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,4), b_type0_cfg_dev[1].f[4])
1822 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,5), b_type0_cfg_dev[1].f[5])
1823 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,6), b_type0_cfg_dev[1].f[6])
1824 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,7), b_type0_cfg_dev[1].f[7])
1825 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(2), b_type0_cfg_dev[2])
1826 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,0), b_type0_cfg_dev[2].f[0])
1827 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,1), b_type0_cfg_dev[2].f[1])
1828 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,2), b_type0_cfg_dev[2].f[2])
1829 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,3), b_type0_cfg_dev[2].f[3])
1830 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,4), b_type0_cfg_dev[2].f[4])
1831 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,5), b_type0_cfg_dev[2].f[5])
1832 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,6), b_type0_cfg_dev[2].f[6])
1833 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,7), b_type0_cfg_dev[2].f[7])
1834 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(3), b_type0_cfg_dev[3])
1835 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,0), b_type0_cfg_dev[3].f[0])
1836 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,1), b_type0_cfg_dev[3].f[1])
1837 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,2), b_type0_cfg_dev[3].f[2])
1838 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,3), b_type0_cfg_dev[3].f[3])
1839 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,4), b_type0_cfg_dev[3].f[4])
1840 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,5), b_type0_cfg_dev[3].f[5])
1841 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,6), b_type0_cfg_dev[3].f[6])
1842 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,7), b_type0_cfg_dev[3].f[7])
1843 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(4), b_type0_cfg_dev[4])
1844 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,0), b_type0_cfg_dev[4].f[0])
1845 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,1), b_type0_cfg_dev[4].f[1])
1846 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,2), b_type0_cfg_dev[4].f[2])
1847 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,3), b_type0_cfg_dev[4].f[3])
1848 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,4), b_type0_cfg_dev[4].f[4])
1849 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,5), b_type0_cfg_dev[4].f[5])
1850 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,6), b_type0_cfg_dev[4].f[6])
1851 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,7), b_type0_cfg_dev[4].f[7])
1852 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(5), b_type0_cfg_dev[5])
1853 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,0), b_type0_cfg_dev[5].f[0])
1854 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,1), b_type0_cfg_dev[5].f[1])
1855 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,2), b_type0_cfg_dev[5].f[2])
1856 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,3), b_type0_cfg_dev[5].f[3])
1857 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,4), b_type0_cfg_dev[5].f[4])
1858 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,5), b_type0_cfg_dev[5].f[5])
1859 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,6), b_type0_cfg_dev[5].f[6])
1860 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,7), b_type0_cfg_dev[5].f[7])
1861 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(6), b_type0_cfg_dev[6])
1862 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,0), b_type0_cfg_dev[6].f[0])
1863 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,1), b_type0_cfg_dev[6].f[1])
1864 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,2), b_type0_cfg_dev[6].f[2])
1865 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,3), b_type0_cfg_dev[6].f[3])
1866 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,4), b_type0_cfg_dev[6].f[4])
1867 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,5), b_type0_cfg_dev[6].f[5])
1868 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,6), b_type0_cfg_dev[6].f[6])
1869 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,7), b_type0_cfg_dev[6].f[7])
1870 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(7), b_type0_cfg_dev[7])
1871 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,0), b_type0_cfg_dev[7].f[0])
1872 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,1), b_type0_cfg_dev[7].f[1])
1873 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,2), b_type0_cfg_dev[7].f[2])
1874 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,3), b_type0_cfg_dev[7].f[3])
1875 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,4), b_type0_cfg_dev[7].f[4])
1876 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,5), b_type0_cfg_dev[7].f[5])
1877 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,6), b_type0_cfg_dev[7].f[6])
1878 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,7), b_type0_cfg_dev[7].f[7])
1880 MACROFIELD_LINE(BRIDGE_TYPE1_CFG, b_type1_cfg)
1881 MACROFIELD_LINE(BRIDGE_PCI_IACK, b_pci_iack)
1882 MACROFIELD_LINE(BRIDGE_EXT_SSRAM, b_ext_ate_ram)
1883 MACROFIELD_LINE(BRIDGE_DEVIO0, b_devio(0))
1884 MACROFIELD_LINE(BRIDGE_DEVIO(0), b_devio(0))
1885 MACROFIELD_LINE(BRIDGE_DEVIO(1), b_devio(1))
1886 MACROFIELD_LINE(BRIDGE_DEVIO(2), b_devio(2))
1887 MACROFIELD_LINE(BRIDGE_DEVIO(3), b_devio(3))
1888 MACROFIELD_LINE(BRIDGE_DEVIO(4), b_devio(4))
1889 MACROFIELD_LINE(BRIDGE_DEVIO(5), b_devio(5))
1890 MACROFIELD_LINE(BRIDGE_DEVIO(6), b_devio(6))
1891 MACROFIELD_LINE(BRIDGE_DEVIO(7), b_devio(7))
1892 MACROFIELD_LINE(BRIDGE_EXTERNAL_FLASH, b_external_flash)
1899 #endif /* C or C++ */
1901 #endif /* _ASM_SN_PCI_BRIDGE_H */