2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2000,2002-2003 Silicon Graphics, Inc. All rights reserved.
8 * Routines for PCI DMA mapping. See Documentation/DMA-mapping.txt for
9 * a description of how these routines should be used.
12 #include <linux/config.h>
13 #include <linux/types.h>
15 #include <linux/string.h>
16 #include <linux/pci.h>
17 #include <linux/slab.h>
18 #include <linux/devfs_fs_kernel.h>
19 #include <linux/module.h>
21 #include <asm/delay.h>
23 #include <asm/sn/sgi.h>
24 #include <asm/sn/io.h>
25 #include <asm/sn/invent.h>
26 #include <asm/sn/hcl.h>
27 #include <asm/sn/pci/pcibr.h>
28 #include <asm/sn/pci/pcibr_private.h>
29 #include <asm/sn/driver.h>
30 #include <asm/sn/types.h>
31 #include <asm/sn/alenlist.h>
32 #include <asm/sn/pci/pci_bus_cvlink.h>
33 #include <asm/sn/nag.h>
38 pciio_dmamap_t get_free_pciio_dmamap(vertex_hdl_t);
39 void free_pciio_dmamap(pcibr_dmamap_t);
40 static struct sn_dma_maps_s *find_sn_dma_map(dma_addr_t, unsigned char);
41 void sn_pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction);
46 extern vertex_hdl_t busnum_to_pcibr_vhdl[];
47 extern nasid_t busnum_to_nid[];
48 extern void * busnum_to_atedmamaps[];
51 * get_free_pciio_dmamap - find and allocate an ATE
52 * @pci_bus: PCI bus to get an entry for
54 * Finds and allocates an ATE on the PCI bus specified
58 get_free_pciio_dmamap(vertex_hdl_t pci_bus)
61 struct sn_dma_maps_s *sn_dma_map = NULL;
64 * Darn, we need to get the maps allocated for this bus.
66 for (i = 0; i < MAX_PCI_XWIDGET; i++) {
67 if (busnum_to_pcibr_vhdl[i] == pci_bus) {
68 sn_dma_map = busnum_to_atedmamaps[i];
73 * Now get a free dmamap entry from this list.
75 for (i = 0; i < MAX_ATE_MAPS; i++, sn_dma_map++) {
76 if (!sn_dma_map->dma_addr) {
77 sn_dma_map->dma_addr = -1;
78 return( (pciio_dmamap_t) sn_dma_map );
86 * free_pciio_dmamap - free an ATE
87 * @dma_map: ATE to free
89 * Frees the ATE specified by @dma_map.
92 free_pciio_dmamap(pcibr_dmamap_t dma_map)
94 struct sn_dma_maps_s *sn_dma_map;
96 sn_dma_map = (struct sn_dma_maps_s *) dma_map;
97 sn_dma_map->dma_addr = 0;
101 * find_sn_dma_map - find an ATE associated with @dma_addr and @busnum
102 * @dma_addr: DMA address to look for
103 * @busnum: PCI bus to look on
105 * Finds the ATE associated with @dma_addr and @busnum.
107 static struct sn_dma_maps_s *
108 find_sn_dma_map(dma_addr_t dma_addr, unsigned char busnum)
111 struct sn_dma_maps_s *sn_dma_map = NULL;
114 sn_dma_map = busnum_to_atedmamaps[busnum];
116 for (i = 0; i < MAX_ATE_MAPS; i++, sn_dma_map++) {
117 if (sn_dma_map->dma_addr == dma_addr) {
126 * sn_pci_alloc_consistent - allocate memory for coherent DMA
127 * @hwdev: device to allocate for
128 * @size: size of the region
129 * @dma_handle: DMA (bus) address
131 * pci_alloc_consistent() returns a pointer to a memory region suitable for
132 * coherent DMA traffic to/from a PCI device. On SN platforms, this means
133 * that @dma_handle will have the %PCIIO_DMA_CMD flag set.
135 * This interface is usually used for "command" streams (e.g. the command
136 * queue for a SCSI controller). See Documentation/DMA-mapping.txt for
137 * more information. Note that this routine will always put a 32 bit
138 * DMA address into @dma_handle. This is because most devices
139 * that are capable of 64 bit PCI DMA transactions can't do 64 bit _coherent_
140 * DMAs, and unfortunately this interface has to cater to the LCD. Oh well.
142 * Also known as platform_pci_alloc_consistent() by the IA64 machvec code.
145 sn_pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle)
149 struct sn_device_sysdata *device_sysdata;
150 unsigned long phys_addr;
151 pciio_dmamap_t dma_map = 0;
152 struct sn_dma_maps_s *sn_dma_map;
156 /* We can't easily support < 32 bit devices */
157 if (IS_PCI32L(hwdev))
161 * Get hwgraph vertex for the device
163 device_sysdata = (struct sn_device_sysdata *) hwdev->sysdata;
164 vhdl = device_sysdata->vhdl;
167 * Allocate the memory. FIXME: if we're allocating for
168 * two devices on the same bus, we should at least try to
169 * allocate memory in the same 2 GB window to avoid using
170 * ATEs for the translation. See the comment above about the
171 * 32 bit requirement for this function.
173 if(!(cpuaddr = (void *)__get_free_pages(GFP_ATOMIC, get_order(size))))
176 memset(cpuaddr, 0, size); /* have to zero it out */
178 /* physical addr. of the memory we just got */
179 phys_addr = __pa(cpuaddr);
182 * This will try to use a Direct Map register to do the
183 * 32 bit DMA mapping, but it may not succeed if another
184 * device on the same bus is already mapped with different
185 * attributes or to a different memory region.
187 *dma_handle = pciio_dmatrans_addr(vhdl, NULL, phys_addr, size,
188 ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
192 * It is a 32 bit card and we cannot do direct mapping,
193 * so we try to use an ATE.
195 if (!(*dma_handle)) {
196 dma_map = pciio_dmamap_alloc(vhdl, NULL, size,
197 ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
200 printk(KERN_ERR "sn_pci_alloc_consistent: Unable to "
201 "allocate anymore 32 bit page map entries.\n");
204 *dma_handle = (dma_addr_t) pciio_dmamap_addr(dma_map,phys_addr,
206 sn_dma_map = (struct sn_dma_maps_s *)dma_map;
207 sn_dma_map->dma_addr = *dma_handle;
214 * sn_pci_free_consistent - free memory associated with coherent DMAable region
215 * @hwdev: device to free for
216 * @size: size to free
217 * @vaddr: kernel virtual address to free
218 * @dma_handle: DMA address associated with this region
220 * Frees the memory allocated by pci_alloc_consistent(). Also known
221 * as platform_pci_free_consistent() by the IA64 machvec code.
224 sn_pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle)
226 struct sn_dma_maps_s *sn_dma_map = NULL;
229 * Get the sn_dma_map entry.
231 if (IS_PCI32_MAPPED(dma_handle))
232 sn_dma_map = find_sn_dma_map(dma_handle, hwdev->bus->number);
235 * and free it if necessary...
238 pciio_dmamap_done((pciio_dmamap_t)sn_dma_map);
239 pciio_dmamap_free((pciio_dmamap_t)sn_dma_map);
240 sn_dma_map->dma_addr = (dma_addr_t)NULL;
242 free_pages((unsigned long) vaddr, get_order(size));
246 * sn_pci_map_sg - map a scatter-gather list for DMA
247 * @hwdev: device to map for
248 * @sg: scatterlist to map
249 * @nents: number of entries
250 * @direction: direction of the DMA transaction
252 * Maps each entry of @sg for DMA. Also known as platform_pci_map_sg by the
256 sn_pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction)
261 unsigned long phys_addr;
262 struct sn_device_sysdata *device_sysdata;
263 pciio_dmamap_t dma_map;
264 struct sn_dma_maps_s *sn_dma_map;
265 struct scatterlist *saved_sg = sg;
267 /* can't go anywhere w/o a direction in life */
268 if (direction == PCI_DMA_NONE)
272 * Get the hwgraph vertex for the device
274 device_sysdata = (struct sn_device_sysdata *) hwdev->sysdata;
275 vhdl = device_sysdata->vhdl;
278 * Setup a DMA address for each entry in the
281 for (i = 0; i < nents; i++, sg++) {
282 phys_addr = __pa(sg->dma_address ? sg->dma_address :
283 page_address(sg->page) + sg->offset);
286 * Handle the most common case: 64 bit cards. This
287 * call should always succeed.
289 if (IS_PCIA64(hwdev)) {
290 sg->dma_address = pciio_dmatrans_addr(vhdl, NULL, phys_addr,
292 ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
295 sg->dma_length = sg->length;
300 * Handle 32-63 bit cards via direct mapping
302 if (IS_PCI32G(hwdev)) {
303 sg->dma_address = pciio_dmatrans_addr(vhdl, NULL, phys_addr,
305 ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
307 sg->dma_length = sg->length;
309 * See if we got a direct map entry
311 if (sg->dma_address) {
318 * It is a 32 bit card and we cannot do direct mapping,
321 dma_map = pciio_dmamap_alloc(vhdl, NULL, sg->length,
322 ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
325 printk(KERN_ERR "sn_pci_map_sg: Unable to allocate "
326 "anymore 32 bit page map entries.\n");
328 * We will need to free all previously allocated entries.
331 sn_pci_unmap_sg(hwdev, saved_sg, i, direction);
336 sg->dma_address = pciio_dmamap_addr(dma_map, phys_addr, sg->length);
337 sg->dma_length = sg->length;
338 sn_dma_map = (struct sn_dma_maps_s *)dma_map;
339 sn_dma_map->dma_addr = sg->dma_address;
347 * sn_pci_unmap_sg - unmap a scatter-gather list
348 * @hwdev: device to unmap
349 * @sg: scatterlist to unmap
350 * @nents: number of scatterlist entries
351 * @direction: DMA direction
353 * Unmap a set of streaming mode DMA translations. Again, cpu read rules
354 * concerning calls here are the same as for pci_unmap_single() below. Also
355 * known as sn_pci_unmap_sg() by the IA64 machvec code.
358 sn_pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction)
361 struct sn_dma_maps_s *sn_dma_map;
363 /* can't go anywhere w/o a direction in life */
364 if (direction == PCI_DMA_NONE)
367 for (i = 0; i < nents; i++, sg++){
369 if (IS_PCI32_MAPPED(sg->dma_address)) {
371 sn_dma_map = find_sn_dma_map(sg->dma_address, hwdev->bus->number);
373 pciio_dmamap_done((pciio_dmamap_t)sn_dma_map);
374 pciio_dmamap_free((pciio_dmamap_t)sn_dma_map);
375 sn_dma_map->dma_addr = (dma_addr_t)NULL;
379 sg->dma_address = (dma_addr_t)NULL;
385 * sn_pci_map_single - map a single region for DMA
386 * @hwdev: device to map for
387 * @ptr: kernel virtual address of the region to map
388 * @size: size of the region
389 * @direction: DMA direction
391 * Map the region pointed to by @ptr for DMA and return the
392 * DMA address. Also known as platform_pci_map_single() by
393 * the IA64 machvec code.
395 * We map this to the one step pciio_dmamap_trans interface rather than
396 * the two step pciio_dmamap_alloc/pciio_dmamap_addr because we have
397 * no way of saving the dmamap handle from the alloc to later free
398 * (which is pretty much unacceptable).
400 * TODO: simplify our interface;
401 * get rid of dev_desc and vhdl (seems redundant given a pci_dev);
402 * figure out how to save dmamap handle so can use two step.
405 sn_pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction)
409 unsigned long phys_addr;
410 struct sn_device_sysdata *device_sysdata;
411 pciio_dmamap_t dma_map = NULL;
412 struct sn_dma_maps_s *sn_dma_map;
414 if (direction == PCI_DMA_NONE)
417 /* SN cannot support DMA addresses smaller than 32 bits. */
418 if (IS_PCI32L(hwdev))
422 * find vertex for the device
424 device_sysdata = (struct sn_device_sysdata *)hwdev->sysdata;
425 vhdl = device_sysdata->vhdl;
428 * Call our dmamap interface
431 phys_addr = __pa(ptr);
433 if (IS_PCIA64(hwdev)) {
434 /* This device supports 64 bit DMA addresses. */
435 dma_addr = pciio_dmatrans_addr(vhdl, NULL, phys_addr, size,
436 ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
443 * Devices that support 32 bit to 63 bit DMA addresses get
444 * 32 bit DMA addresses.
446 * First try to get a 32 bit direct map register.
448 if (IS_PCI32G(hwdev)) {
449 dma_addr = pciio_dmatrans_addr(vhdl, NULL, phys_addr, size,
450 ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
457 * It's a 32 bit card and we cannot do direct mapping so
458 * let's use the PMU instead.
461 dma_map = pciio_dmamap_alloc(vhdl, NULL, size,
462 ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
466 printk(KERN_ERR "pci_map_single: Unable to allocate anymore "
467 "32 bit page map entries.\n");
471 dma_addr = (dma_addr_t) pciio_dmamap_addr(dma_map, phys_addr, size);
472 sn_dma_map = (struct sn_dma_maps_s *)dma_map;
473 sn_dma_map->dma_addr = dma_addr;
475 return ((dma_addr_t)dma_addr);
479 * sn_pci_unmap_single - unmap a region used for DMA
480 * @hwdev: device to unmap
481 * @dma_addr: DMA address to unmap
482 * @size: size of region
483 * @direction: DMA direction
485 * Unmaps the region pointed to by @dma_addr. Also known as
486 * platform_pci_unmap_single() by the IA64 machvec code.
489 sn_pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction)
491 struct sn_dma_maps_s *sn_dma_map = NULL;
493 if (direction == PCI_DMA_NONE)
497 * Get the sn_dma_map entry.
499 if (IS_PCI32_MAPPED(dma_addr))
500 sn_dma_map = find_sn_dma_map(dma_addr, hwdev->bus->number);
503 * and free it if necessary...
506 pciio_dmamap_done((pciio_dmamap_t)sn_dma_map);
507 pciio_dmamap_free((pciio_dmamap_t)sn_dma_map);
508 sn_dma_map->dma_addr = (dma_addr_t)NULL;
513 * sn_pci_dma_sync_single - make sure all DMAs have completed
514 * @hwdev: device to sync
515 * @dma_handle: DMA address to sync
516 * @size: size of region
517 * @direction: DMA direction
519 * This routine is supposed to sync the DMA region specified
520 * by @dma_handle into the 'coherence domain'. We do not need to do
521 * anything on our platform.
524 sn_pci_dma_sync_single(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction)
531 * sn_pci_dma_sync_sg - make sure all DMAs have completed
532 * @hwdev: device to sync
533 * @sg: scatterlist to sync
534 * @nents: number of entries in the scatterlist
535 * @direction: DMA direction
537 * This routine is supposed to sync the DMA regions specified
538 * by @sg into the 'coherence domain'. We do not need to do anything
542 sn_pci_dma_sync_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction)
549 * sn_dma_supported - test a DMA mask
550 * @hwdev: device to test
551 * @mask: DMA mask to test
553 * Return whether the given PCI device DMA address mask can be supported
554 * properly. For example, if your device can only drive the low 24-bits
555 * during PCI bus mastering, then you would pass 0x00ffffff as the mask to
556 * this function. Of course, SN only supports devices that have 32 or more
557 * address bits when using the PMU. We could theoretically support <32 bit
558 * cards using direct mapping, but we'll worry about that later--on the off
559 * chance that someone actually wants to use such a card.
562 sn_pci_dma_supported(struct pci_dev *hwdev, u64 mask)
564 if (mask < 0xffffffff)
569 EXPORT_SYMBOL(sn_pci_unmap_single);
570 EXPORT_SYMBOL(sn_pci_map_single);
571 EXPORT_SYMBOL(sn_pci_dma_sync_single);
572 EXPORT_SYMBOL(sn_pci_map_sg);
573 EXPORT_SYMBOL(sn_pci_unmap_sg);
574 EXPORT_SYMBOL(sn_pci_alloc_consistent);
575 EXPORT_SYMBOL(sn_pci_free_consistent);
576 EXPORT_SYMBOL(sn_pci_dma_supported);