2 * Copyright (C) 2010 - 2011 Samsung Electronics Co., Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
14 #include <linux/sched.h>
15 #include <linux/spinlock.h>
16 #include <linux/types.h>
17 #include <linux/videodev2.h>
20 #include <media/media-entity.h>
21 #include <media/videobuf2-core.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-mem2mem.h>
24 #include <media/v4l2-mediabus.h>
25 #include <media/s5p_fimc.h>
27 #include "regs-fimc.h"
29 #define err(fmt, args...) \
30 printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
32 #define dbg(fmt, args...) \
33 pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
35 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
36 #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
37 #define MAX_FIMC_CLOCKS 3
38 #define MODULE_NAME "s5p-fimc"
39 #define FIMC_MAX_DEVS 4
40 #define FIMC_MAX_OUT_BUFS 4
41 #define SCALER_MAX_HRATIO 64
42 #define SCALER_MAX_VRATIO 64
43 #define DMA_MIN_SIZE 8
45 /* indices to the clocks array */
67 #define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)
68 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
70 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
71 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
72 #define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)
82 S5P_FIMC_RGB565 = 0x10,
86 S5P_FIMC_YCBCR420 = 0x20,
91 S5P_FIMC_YCBCR444_LOCAL,
94 #define fimc_fmt_is_rgb(x) ((x) & 0x10)
96 /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
97 #define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
99 /* The embedded image effect selection */
100 #define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS
101 #define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY
102 #define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE
103 #define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE
104 #define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING
105 #define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE
107 /* The hardware context state. */
108 #define FIMC_PARAMS (1 << 0)
109 #define FIMC_SRC_ADDR (1 << 1)
110 #define FIMC_DST_ADDR (1 << 2)
111 #define FIMC_SRC_FMT (1 << 3)
112 #define FIMC_DST_FMT (1 << 4)
113 #define FIMC_CTX_M2M (1 << 5)
114 #define FIMC_CTX_CAP (1 << 6)
115 #define FIMC_CTX_SHUT (1 << 7)
117 /* Image conversion flags */
118 #define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
119 #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
120 #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
121 #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
122 #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
123 #define FIMC_SCAN_MODE_INTERLACED (1 << 2)
125 * YCbCr data dynamic range for RGB-YUV color conversion.
126 * Y/Cb/Cr: (0 ~ 255) */
127 #define FIMC_COLOR_RANGE_WIDE (0 << 3)
128 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
129 #define FIMC_COLOR_RANGE_NARROW (1 << 3)
132 #define FLIP_X_AXIS 1
133 #define FLIP_Y_AXIS 2
134 #define FLIP_XY_AXIS (FLIP_X_AXIS | FLIP_Y_AXIS)
137 * struct fimc_fmt - the driver's internal color format data
138 * @mbus_code: Media Bus pixel code, -1 if not applicable
139 * @name: format description
140 * @fourcc: the fourcc code for this format, 0 if not applicable
141 * @color: the corresponding fimc_color_fmt
142 * @memplanes: number of physically non-contiguous data planes
143 * @colplanes: number of physically contiguous data planes
144 * @depth: per plane driver's private 'number of bits per pixel'
145 * @flags: flags indicating which operation mode format applies to
148 enum v4l2_mbus_pixelcode mbus_code;
154 u8 depth[VIDEO_MAX_PLANES];
156 #define FMT_FLAGS_CAM (1 << 0)
157 #define FMT_FLAGS_M2M (1 << 1)
161 * struct fimc_dma_offset - pixel offset information for DMA
162 * @y_h: y value horizontal offset
163 * @y_v: y value vertical offset
164 * @cb_h: cb value horizontal offset
165 * @cb_v: cb value vertical offset
166 * @cr_h: cr value horizontal offset
167 * @cr_v: cr value vertical offset
169 struct fimc_dma_offset {
179 * struct fimc_effect - color effect information
181 * @pat_cb: cr value when type is "arbitrary"
182 * @pat_cr: cr value when type is "arbitrary"
191 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
192 * @scaleup_h: flag indicating scaling up horizontally
193 * @scaleup_v: flag indicating scaling up vertically
194 * @copy_mode: flag indicating transparent DMA transfer (no scaling
195 * and color format conversion)
196 * @enabled: flag indicating if the scaler is used
197 * @hfactor: horizontal shift factor
198 * @vfactor: vertical shift factor
199 * @pre_hratio: horizontal ratio of the prescaler
200 * @pre_vratio: vertical ratio of the prescaler
201 * @pre_dst_width: the prescaler's destination width
202 * @pre_dst_height: the prescaler's destination height
203 * @main_hratio: the main scaler's horizontal ratio
204 * @main_vratio: the main scaler's vertical ratio
205 * @real_width: source pixel (width - offset)
206 * @real_height: source pixel (height - offset)
209 unsigned int scaleup_h:1;
210 unsigned int scaleup_v:1;
211 unsigned int copy_mode:1;
212 unsigned int enabled:1;
226 * struct fimc_addr - the FIMC physical address set for DMA
227 * @y: luminance plane physical address
228 * @cb: Cb plane physical address
229 * @cr: Cr plane physical address
238 * struct fimc_vid_buffer - the driver's video buffer
239 * @vb: v4l videobuf buffer
240 * @list: linked list structure for buffer queue
241 * @paddr: precalculated physical address set
242 * @index: buffer index for the output DMA engine
244 struct fimc_vid_buffer {
245 struct vb2_buffer vb;
246 struct list_head list;
247 struct fimc_addr paddr;
252 * struct fimc_frame - source/target frame properties
253 * @f_width: image full width (virtual screen size)
254 * @f_height: image full height (virtual screen size)
255 * @o_width: original image width as set by S_FMT
256 * @o_height: original image height as set by S_FMT
257 * @offs_h: image horizontal pixel offset
258 * @offs_v: image vertical pixel offset
259 * @width: image pixel width
260 * @height: image pixel weight
261 * @payload: image size in bytes (w x h x bpp)
262 * @paddr: image frame buffer physical addresses
263 * @dma_offset: DMA offset in bytes
264 * @fmt: fimc color format pointer
275 unsigned long payload[VIDEO_MAX_PLANES];
276 struct fimc_addr paddr;
277 struct fimc_dma_offset dma_offset;
278 struct fimc_fmt *fmt;
282 * struct fimc_m2m_device - v4l2 memory-to-memory device data
283 * @vfd: the video device node for v4l2 m2m mode
284 * @v4l2_dev: v4l2 device for m2m mode
285 * @m2m_dev: v4l2 memory-to-memory device data
286 * @ctx: hardware context data
287 * @refcnt: the reference counter
289 struct fimc_m2m_device {
290 struct video_device *vfd;
291 struct v4l2_device v4l2_dev;
292 struct v4l2_m2m_dev *m2m_dev;
293 struct fimc_ctx *ctx;
298 * struct fimc_vid_cap - camera capture device information
299 * @ctx: hardware context data
300 * @vfd: video device node for camera capture mode
301 * @v4l2_dev: v4l2_device struct to manage subdevs
302 * @sd: pointer to camera sensor subdevice currently in use
303 * @vd_pad: fimc video capture node pad
304 * @fmt: Media Bus format configured at selected image sensor
305 * @pending_buf_q: the pending buffer queue head
306 * @active_buf_q: the queue head of buffers scheduled in hardware
307 * @vbq: the capture am video buffer queue
308 * @active_buf_cnt: number of video buffers scheduled in hardware
309 * @buf_index: index for managing the output DMA buffers
310 * @frame_count: the frame counter for statistics
311 * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
312 * @input_index: input (camera sensor) index
313 * @refcnt: driver's private reference counter
315 struct fimc_vid_cap {
316 struct fimc_ctx *ctx;
317 struct vb2_alloc_ctx *alloc_ctx;
318 struct video_device *vfd;
319 struct v4l2_device v4l2_dev;
320 struct v4l2_subdev *sd;;
321 struct media_pad vd_pad;
322 struct v4l2_mbus_framefmt fmt;
323 struct list_head pending_buf_q;
324 struct list_head active_buf_q;
325 struct vb2_queue vbq;
328 unsigned int frame_count;
329 unsigned int reqbufs_count;
335 * struct fimc_pix_limit - image pixel size limits in various IP configurations
337 * @scaler_en_w: max input pixel width when the scaler is enabled
338 * @scaler_dis_w: max input pixel width when the scaler is disabled
339 * @in_rot_en_h: max input width with the input rotator is on
340 * @in_rot_dis_w: max input width with the input rotator is off
341 * @out_rot_en_w: max output width with the output rotator on
342 * @out_rot_dis_w: max output width with the output rotator off
344 struct fimc_pix_limit {
354 * struct samsung_fimc_variant - camera interface variant information
356 * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
357 * @has_inp_rot: set if has input rotator
358 * @has_out_rot: set if has output rotator
359 * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
360 * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
361 * are present in this IP revision
362 * @pix_limit: pixel size constraints for the scaler
363 * @min_inp_pixsize: minimum input pixel size
364 * @min_out_pixsize: minimum output pixel size
365 * @hor_offs_align: horizontal pixel offset aligment
366 * @out_buf_count: the number of buffers in output DMA sequence
368 struct samsung_fimc_variant {
369 unsigned int pix_hoff:1;
370 unsigned int has_inp_rot:1;
371 unsigned int has_out_rot:1;
372 unsigned int has_cistatus2:1;
373 unsigned int has_mainscaler_ext:1;
374 struct fimc_pix_limit *pix_limit;
382 * struct samsung_fimc_driverdata - per device type driver data for init time.
384 * @variant: the variant information for this driver.
385 * @dev_cnt: number of fimc sub-devices available in SoC
386 * @lclk_frequency: fimc bus clock frequency
388 struct samsung_fimc_driverdata {
389 struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
390 unsigned long lclk_frequency;
397 * struct fimc_dev - abstraction for FIMC entity
398 * @slock: the spinlock protecting this data structure
399 * @lock: the mutex protecting this data structure
400 * @pdev: pointer to the FIMC platform device
401 * @pdata: pointer to the device platform data
402 * @variant: the IP variant information
403 * @id: FIMC device index (0..FIMC_MAX_DEVS)
404 * @num_clocks: the number of clocks managed by this device instance
405 * @clock: clocks required for FIMC operation
406 * @regs: the mapped hardware registers
407 * @regs_res: the resource claimed for IO registers
408 * @irq: FIMC interrupt number
409 * @irq_queue: interrupt handler waitqueue
410 * @m2m: memory-to-memory V4L2 device information
411 * @vid_cap: camera capture device information
412 * @state: flags used to synchronize m2m and capture mode operation
413 * @alloc_ctx: videobuf2 memory allocator context
418 struct platform_device *pdev;
419 struct s5p_platform_fimc *pdata;
420 struct samsung_fimc_variant *variant;
423 struct clk *clock[MAX_FIMC_CLOCKS];
425 struct resource *regs_res;
427 wait_queue_head_t irq_queue;
428 struct fimc_m2m_device m2m;
429 struct fimc_vid_cap vid_cap;
431 struct vb2_alloc_ctx *alloc_ctx;
435 * fimc_ctx - the device context data
436 * @slock: spinlock protecting this data structure
437 * @s_frame: source frame properties
438 * @d_frame: destination frame properties
439 * @out_order_1p: output 1-plane YCBCR order
440 * @out_order_2p: output 2-plane YCBCR order
441 * @in_order_1p input 1-plane YCBCR order
442 * @in_order_2p: input 2-plane YCBCR order
443 * @in_path: input mode (DMA or camera)
444 * @out_path: output mode (DMA or FIFO)
445 * @scaler: image scaler properties
446 * @effect: image effect
447 * @rotation: image clockwise rotation in degrees
448 * @flip: image flip mode
449 * @flags: additional flags for image conversion
450 * @state: flags to keep track of user configuration
451 * @fimc_dev: the FIMC device this context applies to
452 * @m2m_ctx: memory-to-memory device context
456 struct fimc_frame s_frame;
457 struct fimc_frame d_frame;
462 enum fimc_datapath in_path;
463 enum fimc_datapath out_path;
464 struct fimc_scaler scaler;
465 struct fimc_effect effect;
470 struct fimc_dev *fimc_dev;
471 struct v4l2_m2m_ctx *m2m_ctx;
474 static inline bool fimc_capture_active(struct fimc_dev *fimc)
479 spin_lock_irqsave(&fimc->slock, flags);
480 ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
481 fimc->state & (1 << ST_CAPT_PEND));
482 spin_unlock_irqrestore(&fimc->slock, flags);
486 static inline void fimc_ctx_state_lock_set(u32 state, struct fimc_ctx *ctx)
490 spin_lock_irqsave(&ctx->slock, flags);
492 spin_unlock_irqrestore(&ctx->slock, flags);
495 static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
500 spin_lock_irqsave(&ctx->slock, flags);
501 ret = (ctx->state & mask) == mask;
502 spin_unlock_irqrestore(&ctx->slock, flags);
506 static inline int tiled_fmt(struct fimc_fmt *fmt)
508 return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
511 static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
513 u32 cfg = readl(dev->regs + S5P_CIGCTRL);
514 cfg |= S5P_CIGCTRL_IRQ_CLR;
515 writel(cfg, dev->regs + S5P_CIGCTRL);
518 static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
520 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
522 cfg |= S5P_CISCCTRL_SCALERSTART;
524 cfg &= ~S5P_CISCCTRL_SCALERSTART;
525 writel(cfg, dev->regs + S5P_CISCCTRL);
528 static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
530 u32 cfg = readl(dev->regs + S5P_MSCTRL);
532 cfg |= S5P_MSCTRL_ENVID;
534 cfg &= ~S5P_MSCTRL_ENVID;
535 writel(cfg, dev->regs + S5P_MSCTRL);
538 static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
540 u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
541 cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
542 writel(cfg, dev->regs + S5P_CIIMGCPT);
546 * fimc_hw_set_dma_seq - configure output DMA buffer sequence
547 * @mask: each bit corresponds to one of 32 output buffer registers set
548 * 1 to include buffer in the sequence, 0 to disable
550 * This function mask output DMA ring buffers, i.e. it allows to configure
551 * which of the output buffer address registers will be used by the DMA
554 static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)
556 writel(mask, dev->regs + S5P_CIFCNTSEQ);
559 static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
560 enum v4l2_buf_type type)
562 struct fimc_frame *frame;
564 if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
565 if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
566 frame = &ctx->s_frame;
568 return ERR_PTR(-EINVAL);
569 } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
570 frame = &ctx->d_frame;
572 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
573 "Wrong buffer/video queue type (%d)\n", type);
574 return ERR_PTR(-EINVAL);
580 /* Return an index to the buffer actually being written. */
581 static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
585 if (dev->variant->has_cistatus2) {
586 reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F;
587 return reg > 0 ? --reg : reg;
589 reg = readl(dev->regs + S5P_CISTATUS);
590 return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
591 S5P_CISTATUS_FRAMECNT_SHIFT;
595 /* -----------------------------------------------------*/
597 void fimc_hw_reset(struct fimc_dev *fimc);
598 void fimc_hw_set_rotation(struct fimc_ctx *ctx);
599 void fimc_hw_set_target_format(struct fimc_ctx *ctx);
600 void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
601 void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable);
602 void fimc_hw_en_irq(struct fimc_dev *fimc, int enable);
603 void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
604 void fimc_hw_set_mainscaler(struct fimc_ctx *ctx);
605 void fimc_hw_en_capture(struct fimc_ctx *ctx);
606 void fimc_hw_set_effect(struct fimc_ctx *ctx);
607 void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
608 void fimc_hw_set_input_path(struct fimc_ctx *ctx);
609 void fimc_hw_set_output_path(struct fimc_ctx *ctx);
610 void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
611 void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
613 int fimc_hw_set_camera_source(struct fimc_dev *fimc,
614 struct s5p_fimc_isp_info *cam);
615 int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
616 int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
617 struct s5p_fimc_isp_info *cam);
618 int fimc_hw_set_camera_type(struct fimc_dev *fimc,
619 struct s5p_fimc_isp_info *cam);
621 /* -----------------------------------------------------*/
623 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
624 struct v4l2_fmtdesc *f);
625 int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
626 struct v4l2_format *f);
627 int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
628 struct v4l2_format *f);
629 int fimc_vidioc_queryctrl(struct file *file, void *priv,
630 struct v4l2_queryctrl *qc);
631 int fimc_vidioc_g_ctrl(struct file *file, void *priv,
632 struct v4l2_control *ctrl);
634 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr);
635 int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
636 int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
638 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask);
639 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
642 int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot);
643 int fimc_set_scaler_info(struct fimc_ctx *ctx);
644 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
645 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
646 struct fimc_frame *frame, struct fimc_addr *paddr);
647 int fimc_register_m2m_device(struct fimc_dev *fimc);
649 /* -----------------------------------------------------*/
651 int fimc_register_capture_device(struct fimc_dev *fimc);
652 void fimc_unregister_capture_device(struct fimc_dev *fimc);
653 int fimc_sensor_sd_init(struct fimc_dev *fimc, int index);
654 int fimc_vid_cap_buf_queue(struct fimc_dev *fimc,
655 struct fimc_vid_buffer *fimc_vb);
656 int fimc_capture_suspend(struct fimc_dev *fimc);
657 int fimc_capture_resume(struct fimc_dev *fimc);
659 /* Locking: the caller holds fimc->slock */
660 static inline void fimc_activate_capture(struct fimc_ctx *ctx)
662 fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
663 fimc_hw_en_capture(ctx);
666 static inline void fimc_deactivate_capture(struct fimc_dev *fimc)
668 fimc_hw_en_lastirq(fimc, true);
669 fimc_hw_dis_capture(fimc);
670 fimc_hw_enable_scaler(fimc, false);
671 fimc_hw_en_lastirq(fimc, false);
675 * Add buf to the capture active buffers queue.
676 * Locking: Need to be called with fimc_dev::slock held.
678 static inline void active_queue_add(struct fimc_vid_cap *vid_cap,
679 struct fimc_vid_buffer *buf)
681 list_add_tail(&buf->list, &vid_cap->active_buf_q);
682 vid_cap->active_buf_cnt++;
686 * Pop a video buffer from the capture active buffers queue
687 * Locking: Need to be called with fimc_dev::slock held.
689 static inline struct fimc_vid_buffer *
690 active_queue_pop(struct fimc_vid_cap *vid_cap)
692 struct fimc_vid_buffer *buf;
693 buf = list_entry(vid_cap->active_buf_q.next,
694 struct fimc_vid_buffer, list);
695 list_del(&buf->list);
696 vid_cap->active_buf_cnt--;
700 /* Add video buffer to the capture pending buffers queue */
701 static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
702 struct fimc_vid_buffer *buf)
704 list_add_tail(&buf->list, &vid_cap->pending_buf_q);
707 /* Add video buffer to the capture pending buffers queue */
708 static inline struct fimc_vid_buffer *
709 pending_queue_pop(struct fimc_vid_cap *vid_cap)
711 struct fimc_vid_buffer *buf;
712 buf = list_entry(vid_cap->pending_buf_q.next,
713 struct fimc_vid_buffer, list);
714 list_del(&buf->list);
718 #endif /* FIMC_CORE_H_ */