3 drivers/net/pci-skeleton.c
5 Maintained by Jeff Garzik <jgarzik@mandrakesoft.com>
7 Original code came from 8139too.c, which in turns was based
8 originally on Donald Becker's rtl8139.c driver, versions 1.11
9 and older. This driver was originally based on rtl8139.c
10 version 1.07. Header of rtl8139.c version 1.11:
14 Written 1997-2000 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
23 This driver is for boards based on the RTL8129 and RTL8139
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
38 This software may be used and distributed according to the terms
39 of the GNU Public License, incorporated herein by reference.
42 -----------------------------------------------------------------------------
46 I. Board Compatibility
48 This device driver is designed for the RealTek RTL8139 series, the RealTek
49 Fast Ethernet controllers for PCI and CardBus. This chip is used on many
50 low-end boards, sometimes with its markings changed.
53 II. Board-specific settings
55 PCI bus devices are configured by the system at boot time, so no jumpers
56 need to be set on the board. The system BIOS will assign the
57 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
63 The receive unit uses a single linear ring buffer rather than the more
64 common (and more efficient) descriptor-based architecture. Incoming frames
65 are sequentially stored into the Rx region, and the host copies them into
68 Comment: While it is theoretically possible to process many frames in place,
69 any delay in Rx processing would cause us to drop frames. More importantly,
70 the Linux protocol stack is not designed to operate in this manner.
74 The RTL8139 uses a fixed set of four Tx descriptors in register space.
75 In a stunningly bad design choice, Tx frames must be 32 bit aligned. Linux
76 aligns the IP header on word boundaries, and 14 byte ethernet header means
77 that almost all frames will need to be copied to an alignment buffer.
81 http://www.realtek.com.tw/cn/cn.html
82 http://www.scyld.com/expert/NWay.html
86 1) The RTL-8139 has a serious problem with motherboards which do
87 posted MMIO writes to PCI space. This driver works around the
88 problem by having an MMIO register write be immediately followed by
89 an MMIO register read.
91 2) The RTL-8129 is only supported in Donald Becker's rtl8139 driver.
95 #include <linux/module.h>
96 #include <linux/kernel.h>
97 #include <linux/pci.h>
98 #include <linux/init.h>
99 #include <linux/ioport.h>
100 #include <linux/netdevice.h>
101 #include <linux/etherdevice.h>
102 #include <linux/delay.h>
106 #define NETDRV_VERSION "1.0.0"
107 #define MODNAME "netdrv"
108 #define NETDRV_DRIVER_LOAD_MSG "MyVendor Fast Ethernet driver " NETDRV_VERSION " loaded"
109 #define PFX MODNAME ": "
112 /* define to 1 to enable PIO instead of MMIO */
115 /* define to 1 to enable copious debugging info */
118 /* define to 1 to disable lightweight runtime debugging checks */
123 /* note: prints function name for you */
124 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
126 # define DPRINTK(fmt, args...)
130 # define assert(expr) do {} while (0)
132 # define assert(expr) \
134 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
135 #expr,__FILE__,__FUNCTION__,__LINE__); \
140 /* A few user-configurable values. */
142 static int media[] = {-1, -1, -1, -1, -1, -1, -1, -1};
144 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
145 static int max_interrupt_work = 20;
147 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
148 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
149 static int multicast_filter_limit = 32;
151 /* Size of the in-memory receive ring. */
152 #define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */
153 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
154 #define RX_BUF_PAD 16
155 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
156 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
158 /* Number of Tx descriptor registers. */
159 #define NUM_TX_DESC 4
161 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
162 #define MAX_ETH_FRAME_SIZE 1536
164 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
165 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
166 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
168 /* PCI Tuning Parameters
169 Threshold is bytes transferred to chip before transmission starts. */
170 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
172 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
173 #define RX_FIFO_THRESH 6 /* Rx buffer level before first PCI xfer. */
174 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
175 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
178 /* Operational parameters that usually are not changed. */
179 /* Time in jiffies before concluding the transmitter is hung. */
180 #define TX_TIMEOUT (6*HZ)
184 HAS_CHIP_XCVR = 0x020000,
185 HAS_LNK_CHNG = 0x040000,
188 #define NETDRV_MIN_IO_SIZE 0x80
189 #define RTL8139B_IO_SIZE 256
191 #define NETDRV_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
203 /* indexed by board_t, above */
206 } board_info[] __devinitdata = {
207 { "RealTek RTL8139 Fast Ethernet" },
208 { "RealTek RTL8139B PCI/CardBus" },
209 { "SMC1211TX EZCard 10/100 (RealTek RTL8139)" },
210 /* { MPX5030, "Accton MPX5030 (RealTek RTL8139)" },*/
211 { "Delta Electronics 8139 10/100BaseTX" },
212 { "Addtron Technolgy 8139 10/100BaseTX" },
216 static struct pci_device_id netdrv_pci_tbl[] __devinitdata = {
217 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
218 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, NETDRV_CB },
219 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
220 /* {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
221 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
222 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
225 MODULE_DEVICE_TABLE (pci, netdrv_pci_tbl);
228 /* The rest of these values should never change. */
230 /* Symbolic offsets to registers. */
231 enum NETDRV_registers {
232 MAC0 = 0, /* Ethernet hardware address. */
233 MAR0 = 8, /* Multicast filter. */
234 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
235 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
238 RxEarlyStatus = 0x36,
247 Timer = 0x48, /* A general-purpose counter. */
248 RxMissed = 0x4C, /* 24 bits valid, write clears. */
255 Config4 = 0x5A, /* absent on RTL-8139A */
259 BasicModeCtrl = 0x62,
260 BasicModeStatus = 0x64,
263 NWayExpansion = 0x6A,
264 /* Undocumented registers, but required for proper operation. */
265 FIFOTMS = 0x70, /* FIFO Control and test. */
266 CSCR = 0x74, /* Chip Status and Configuration Register. */
268 PARA7c = 0x7c, /* Magic transceiver parameter register. */
269 Config5 = 0xD8, /* absent on RTL-8139A */
273 MultiIntrClear = 0xF000,
275 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
285 /* Interrupt register bits, using my own meaningful names. */
286 enum IntrStatusBits {
301 TxOutOfWindow = 0x20000000,
302 TxAborted = 0x40000000,
303 TxCarrierLost = 0x80000000,
306 RxMulticast = 0x8000,
308 RxBroadcast = 0x2000,
309 RxBadSymbol = 0x0020,
317 /* Bits in RxConfig. */
321 AcceptBroadcast = 0x08,
322 AcceptMulticast = 0x04,
324 AcceptAllPhys = 0x01,
327 /* Bits in TxConfig. */
328 enum tx_config_bits {
329 TxIFG1 = (1 << 25), /* Interframe Gap Time */
330 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
331 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
332 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
333 TxClearAbt = (1 << 0), /* Clear abort (WO) */
334 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
336 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
339 /* Bits in Config1 */
341 Cfg1_PM_Enable = 0x01,
342 Cfg1_VPD_Enable = 0x02,
346 Cfg1_Driver_Load = 0x20,
352 /* Early Rx threshold, none or X/16 */
353 RxCfgEarlyRxNone = 0,
354 RxCfgEarlyRxShift = 24,
356 /* rx fifo threshold */
358 RxCfgFIFONone = (7 << RxCfgFIFOShift),
362 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
364 /* rx ring buffer length */
366 RxCfgRcv16K = (1 << 11),
367 RxCfgRcv32K = (1 << 12),
368 RxCfgRcv64K = (1 << 11) | (1 << 12),
370 /* Disable packet wrap at end of Rx buffer */
375 /* Twister tuning parameters from RealTek.
376 Completely undocumented, but required to tune bad links. */
378 CSCR_LinkOKBit = 0x0400,
379 CSCR_LinkChangeBit = 0x0800,
380 CSCR_LinkStatusBits = 0x0f000,
381 CSCR_LinkDownOffCmd = 0x003c0,
382 CSCR_LinkDownCmd = 0x0f3c0,
388 Cfg9346_Unlock = 0xC0,
392 #define PARA78_default 0x78fa8388
393 #define PARA7c_default 0xcb38de43 /* param[0][3] */
394 #define PARA7c_xxx 0xcb38de43
395 static const unsigned long param[4][4] = {
396 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
397 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
398 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
399 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
418 /* directly indexed by chip_t, above */
419 const static struct {
421 u8 version; /* from RTL8139C docs */
422 u32 RxConfigMask; /* should clear the bits supported by this chip */
423 } rtl_chip_info[] = {
426 0xf0fe0040, /* XXX copied from RTL8139A, verify */
446 0xf0fe0040, /* XXX copied from RTL8139A, verify */
451 0xf0fc0040, /* XXX copied from RTL8139B, verify */
457 struct netdrv_private {
461 struct pci_dev *pci_dev;
462 struct net_device_stats stats;
463 struct timer_list timer; /* Media selection timer. */
464 unsigned char *rx_ring;
465 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
466 unsigned int tx_flag;
469 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
470 struct ring_info tx_info[NUM_TX_DESC];
471 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
472 unsigned char *tx_bufs; /* Tx bounce buffer region. */
473 dma_addr_t rx_ring_dma;
474 dma_addr_t tx_bufs_dma;
475 char phys[4]; /* MII device addresses. */
476 char twistie, twist_row, twist_col; /* Twister tune state. */
477 unsigned int full_duplex:1; /* Full-duplex operation requested. */
478 unsigned int duplex_lock:1;
479 unsigned int default_port:4; /* Last dev->if_port value. */
480 unsigned int media2:4; /* Secondary monitored media port. */
481 unsigned int medialock:1; /* Don't sense media type. */
482 unsigned int mediasense:1; /* Media sensing in progress. */
487 MODULE_AUTHOR ("Jeff Garzik <jgarzik@mandrakesoft.com>");
488 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
489 MODULE_PARM (multicast_filter_limit, "i");
490 MODULE_PARM (max_interrupt_work, "i");
491 MODULE_PARM (debug, "i");
492 MODULE_PARM (media, "1-" __MODULE_STRING(8) "i");
494 static int read_eeprom (void *ioaddr, int location, int addr_len);
495 static int netdrv_open (struct net_device *dev);
496 static int mdio_read (struct net_device *dev, int phy_id, int location);
497 static void mdio_write (struct net_device *dev, int phy_id, int location,
499 static void netdrv_timer (unsigned long data);
500 static void netdrv_tx_timeout (struct net_device *dev);
501 static void netdrv_init_ring (struct net_device *dev);
502 static int netdrv_start_xmit (struct sk_buff *skb,
503 struct net_device *dev);
504 static void netdrv_interrupt (int irq, void *dev_instance,
505 struct pt_regs *regs);
506 static int netdrv_close (struct net_device *dev);
507 static int mii_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
508 static struct net_device_stats *netdrv_get_stats (struct net_device *dev);
509 static inline u32 ether_crc (int length, unsigned char *data);
510 static void netdrv_set_rx_mode (struct net_device *dev);
511 static void netdrv_hw_start (struct net_device *dev);
516 #define NETDRV_R8(reg) inb (((unsigned long)ioaddr) + (reg))
517 #define NETDRV_R16(reg) inw (((unsigned long)ioaddr) + (reg))
518 #define NETDRV_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
519 #define NETDRV_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
520 #define NETDRV_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
521 #define NETDRV_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
522 #define NETDRV_W8_F NETDRV_W8
523 #define NETDRV_W16_F NETDRV_W16
524 #define NETDRV_W32_F NETDRV_W32
531 #define readb(addr) inb((unsigned long)(addr))
532 #define readw(addr) inw((unsigned long)(addr))
533 #define readl(addr) inl((unsigned long)(addr))
534 #define writeb(val,addr) outb((val),(unsigned long)(addr))
535 #define writew(val,addr) outw((val),(unsigned long)(addr))
536 #define writel(val,addr) outl((val),(unsigned long)(addr))
540 /* write MMIO register, with flush */
541 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
542 #define NETDRV_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
543 #define NETDRV_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
544 #define NETDRV_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
547 #if MMIO_FLUSH_AUDIT_COMPLETE
549 /* write MMIO register */
550 #define NETDRV_W8(reg, val8) writeb ((val8), ioaddr + (reg))
551 #define NETDRV_W16(reg, val16) writew ((val16), ioaddr + (reg))
552 #define NETDRV_W32(reg, val32) writel ((val32), ioaddr + (reg))
556 /* write MMIO register, then flush */
557 #define NETDRV_W8 NETDRV_W8_F
558 #define NETDRV_W16 NETDRV_W16_F
559 #define NETDRV_W32 NETDRV_W32_F
561 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
563 /* read MMIO register */
564 #define NETDRV_R8(reg) readb (ioaddr + (reg))
565 #define NETDRV_R16(reg) readw (ioaddr + (reg))
566 #define NETDRV_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
568 #endif /* USE_IO_OPS */
571 static const u16 netdrv_intr_mask =
572 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
573 TxErr | TxOK | RxErr | RxOK;
575 static const unsigned int netdrv_rx_config =
576 RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
577 (RX_FIFO_THRESH << RxCfgFIFOShift) |
578 (RX_DMA_BURST << RxCfgDMAShift);
581 static int __devinit netdrv_init_board (struct pci_dev *pdev,
582 struct net_device **dev_out,
586 struct net_device *dev;
587 struct netdrv_private *tp;
590 u32 pio_start, pio_end, pio_flags, pio_len;
591 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
596 assert (pdev != NULL);
597 assert (ioaddr_out != NULL);
602 /* dev zeroed in init_etherdev */
603 dev = init_etherdev (NULL, sizeof (*tp));
605 printk (KERN_ERR PFX "unable to alloc new ethernet\n");
606 DPRINTK ("EXIT, returning -ENOMEM\n");
609 SET_MODULE_OWNER(dev);
612 /* enable device (incl. PCI PM wakeup), and bus-mastering */
613 rc = pci_enable_device (pdev);
617 pio_start = pci_resource_start (pdev, 0);
618 pio_end = pci_resource_end (pdev, 0);
619 pio_flags = pci_resource_flags (pdev, 0);
620 pio_len = pci_resource_len (pdev, 0);
622 mmio_start = pci_resource_start (pdev, 1);
623 mmio_end = pci_resource_end (pdev, 1);
624 mmio_flags = pci_resource_flags (pdev, 1);
625 mmio_len = pci_resource_len (pdev, 1);
627 /* set this immediately, we need to know before
628 * we talk to the chip directly */
629 DPRINTK("PIO region size == 0x%02X\n", pio_len);
630 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
632 /* make sure PCI base addr 0 is PIO */
633 if (!(pio_flags & IORESOURCE_IO)) {
634 printk (KERN_ERR PFX "region #0 not a PIO resource, aborting\n");
639 /* make sure PCI base addr 1 is MMIO */
640 if (!(mmio_flags & IORESOURCE_MEM)) {
641 printk (KERN_ERR PFX "region #1 not an MMIO resource, aborting\n");
646 /* check for weird/broken PCI region reporting */
647 if ((pio_len < NETDRV_MIN_IO_SIZE) ||
648 (mmio_len < NETDRV_MIN_IO_SIZE)) {
649 printk (KERN_ERR PFX "Invalid PCI region size(s), aborting\n");
654 rc = pci_request_regions (pdev, dev->name);
658 pci_set_master (pdev);
661 ioaddr = (void *) pio_start;
663 /* ioremap MMIO region */
664 ioaddr = ioremap (mmio_start, mmio_len);
665 if (ioaddr == NULL) {
666 printk (KERN_ERR PFX "cannot remap MMIO, aborting\n");
668 goto err_out_free_res;
670 #endif /* USE_IO_OPS */
672 /* Soft reset the chip. */
673 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
675 /* Check that the chip has finished the reset. */
676 for (i = 1000; i > 0; i--)
677 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
682 /* Bring the chip out of low-power mode. */
683 /* <insert device-specific code here> */
686 /* sanity checks -- ensure PIO and MMIO registers agree */
687 assert (inb (pio_start+Config0) == readb (ioaddr+Config0));
688 assert (inb (pio_start+Config1) == readb (ioaddr+Config1));
689 assert (inb (pio_start+TxConfig) == readb (ioaddr+TxConfig));
690 assert (inb (pio_start+RxConfig) == readb (ioaddr+RxConfig));
691 #endif /* !USE_IO_OPS */
693 /* identify chip attached to board */
694 tmp = NETDRV_R8 (ChipVersion);
695 for (i = ARRAY_SIZE (rtl_chip_info) - 1; i >= 0; i--)
696 if (tmp == rtl_chip_info[i].version) {
701 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
702 printk (KERN_DEBUG PFX "PCI device %s: unknown chip version, assuming RTL-8139\n",
704 printk (KERN_DEBUG PFX "PCI device %s: TxConfig = 0x%lx\n", pdev->slot_name, NETDRV_R32 (TxConfig));
708 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
711 rtl_chip_info[tp->chipset].name);
713 DPRINTK ("EXIT, returning 0\n");
714 *ioaddr_out = ioaddr;
720 pci_release_regions (pdev);
721 #endif /* !USE_IO_OPS */
723 unregister_netdev (dev);
725 DPRINTK ("EXIT, returning %d\n", rc);
730 static int __devinit netdrv_init_one (struct pci_dev *pdev,
731 const struct pci_device_id *ent)
733 struct net_device *dev = NULL;
734 struct netdrv_private *tp;
735 int i, addr_len, option;
737 static int board_idx = -1;
738 static int printed_version = 0;
743 assert (pdev != NULL);
744 assert (ent != NULL);
748 if (!printed_version) {
749 printk (KERN_INFO NETDRV_DRIVER_LOAD_MSG "\n");
753 i = netdrv_init_board (pdev, &dev, &ioaddr);
755 DPRINTK ("EXIT, returning %d\n", i);
761 assert (ioaddr != NULL);
762 assert (dev != NULL);
765 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
766 for (i = 0; i < 3; i++)
767 ((u16 *) (dev->dev_addr))[i] =
768 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
770 /* The Rtl8139-specific entries in the device structure. */
771 dev->open = netdrv_open;
772 dev->hard_start_xmit = netdrv_start_xmit;
773 dev->stop = netdrv_close;
774 dev->get_stats = netdrv_get_stats;
775 dev->set_multicast_list = netdrv_set_rx_mode;
776 dev->do_ioctl = mii_ioctl;
777 dev->tx_timeout = netdrv_tx_timeout;
778 dev->watchdog_timeo = TX_TIMEOUT;
780 dev->irq = pdev->irq;
781 dev->base_addr = (unsigned long) ioaddr;
783 /* dev->priv/tp zeroed and aligned in init_etherdev */
786 /* note: tp->chipset set in netdrv_init_board */
787 tp->drv_flags = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
788 PCI_COMMAND_MASTER | NETDRV_CAPS;
790 tp->board = ent->driver_data;
791 tp->mmio_addr = ioaddr;
792 tp->lock = SPIN_LOCK_UNLOCKED;
794 pci_set_drvdata(pdev, dev);
798 printk (KERN_INFO "%s: %s at 0x%lx, "
799 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
802 board_info[ent->driver_data].name,
804 dev->dev_addr[0], dev->dev_addr[1],
805 dev->dev_addr[2], dev->dev_addr[3],
806 dev->dev_addr[4], dev->dev_addr[5],
809 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
810 dev->name, rtl_chip_info[tp->chipset].name);
812 /* Put the chip into low-power mode. */
813 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
815 /* The lower four bits are the media type. */
816 option = (board_idx > 7) ? 0 : media[board_idx];
818 tp->full_duplex = (option & 0x200) ? 1 : 0;
819 tp->default_port = option & 15;
820 if (tp->default_port)
824 if (tp->full_duplex) {
826 "%s: Media type forced to Full Duplex.\n",
828 mdio_write (dev, tp->phys[0], 4, 0x141);
832 DPRINTK ("EXIT - returning 0\n");
837 static void __devexit netdrv_remove_one (struct pci_dev *pdev)
839 struct net_device *dev = pci_get_drvdata (pdev);
840 struct netdrv_private *np;
844 assert (dev != NULL);
849 unregister_netdev (dev);
852 iounmap (np->mmio_addr);
853 #endif /* !USE_IO_OPS */
855 pci_release_regions (pdev);
857 #ifndef NETDRV_NDEBUG
858 /* poison memory before freeing */
860 sizeof (struct net_device) +
861 sizeof (struct netdrv_private));
862 #endif /* NETDRV_NDEBUG */
866 pci_set_drvdata (pdev, NULL);
868 pci_power_off (pdev, -1);
874 /* Serial EEPROM section. */
876 /* EEPROM_Ctrl bits. */
877 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
878 #define EE_CS 0x08 /* EEPROM chip select. */
879 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
880 #define EE_WRITE_0 0x00
881 #define EE_WRITE_1 0x02
882 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
883 #define EE_ENB (0x80 | EE_CS)
885 /* Delay between EEPROM clock transitions.
886 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
889 #define eeprom_delay() readl(ee_addr)
891 /* The EEPROM commands include the alway-set leading bit. */
892 #define EE_WRITE_CMD (5)
893 #define EE_READ_CMD (6)
894 #define EE_ERASE_CMD (7)
896 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
900 void *ee_addr = ioaddr + Cfg9346;
901 int read_cmd = location | (EE_READ_CMD << addr_len);
905 writeb (EE_ENB & ~EE_CS, ee_addr);
906 writeb (EE_ENB, ee_addr);
909 /* Shift the read command bits out. */
910 for (i = 4 + addr_len; i >= 0; i--) {
911 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
912 writeb (EE_ENB | dataval, ee_addr);
914 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
917 writeb (EE_ENB, ee_addr);
920 for (i = 16; i > 0; i--) {
921 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
924 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
926 writeb (EE_ENB, ee_addr);
930 /* Terminate the EEPROM access. */
931 writeb (~EE_CS, ee_addr);
934 DPRINTK ("EXIT - returning %d\n", retval);
938 /* MII serial management: mostly bogus for now. */
939 /* Read and write the MII management registers using software-generated
940 serial MDIO protocol.
941 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
942 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
943 "overclocking" issues. */
944 #define MDIO_DIR 0x80
945 #define MDIO_DATA_OUT 0x04
946 #define MDIO_DATA_IN 0x02
947 #define MDIO_CLK 0x01
948 #define MDIO_WRITE0 (MDIO_DIR)
949 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
951 #define mdio_delay() readb(mdio_addr)
954 static char mii_2_8139_map[8] = {
966 /* Syncronize the MII management interface by shifting 32 one bits out. */
967 static void mdio_sync (void *mdio_addr)
973 for (i = 32; i >= 0; i--) {
974 writeb (MDIO_WRITE1, mdio_addr);
976 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
984 static int mdio_read (struct net_device *dev, int phy_id, int location)
986 struct netdrv_private *tp = dev->priv;
987 void *mdio_addr = tp->mmio_addr + Config4;
988 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
994 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
995 DPRINTK ("EXIT after directly using 8139 internal regs\n");
996 return location < 8 && mii_2_8139_map[location] ?
997 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
999 mdio_sync (mdio_addr);
1000 /* Shift the read command bits out. */
1001 for (i = 15; i >= 0; i--) {
1002 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1004 writeb (MDIO_DIR | dataval, mdio_addr);
1006 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1010 /* Read the two transition, 16 data, and wire-idle bits. */
1011 for (i = 19; i > 0; i--) {
1012 writeb (0, mdio_addr);
1015 (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1
1017 writeb (MDIO_CLK, mdio_addr);
1021 DPRINTK ("EXIT, returning %d\n", (retval >> 1) & 0xffff);
1022 return (retval >> 1) & 0xffff;
1026 static void mdio_write (struct net_device *dev, int phy_id, int location,
1029 struct netdrv_private *tp = dev->priv;
1030 void *mdio_addr = tp->mmio_addr + Config4;
1032 (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1035 DPRINTK ("ENTER\n");
1037 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1038 if (location < 8 && mii_2_8139_map[location]) {
1040 tp->mmio_addr + mii_2_8139_map[location]);
1041 readw (tp->mmio_addr + mii_2_8139_map[location]);
1043 DPRINTK ("EXIT after directly using 8139 internal regs\n");
1046 mdio_sync (mdio_addr);
1048 /* Shift the command bits out. */
1049 for (i = 31; i >= 0; i--) {
1051 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1052 writeb (dataval, mdio_addr);
1054 writeb (dataval | MDIO_CLK, mdio_addr);
1058 /* Clear out extra bits. */
1059 for (i = 2; i > 0; i--) {
1060 writeb (0, mdio_addr);
1062 writeb (MDIO_CLK, mdio_addr);
1070 static int netdrv_open (struct net_device *dev)
1072 struct netdrv_private *tp = dev->priv;
1075 void *ioaddr = tp->mmio_addr;
1078 DPRINTK ("ENTER\n");
1080 retval = request_irq (dev->irq, netdrv_interrupt, SA_SHIRQ, dev->name, dev);
1082 DPRINTK ("EXIT, returning %d\n", retval);
1086 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1088 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1090 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1091 free_irq(dev->irq, dev);
1094 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1095 tp->tx_bufs, tp->tx_bufs_dma);
1097 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1098 tp->rx_ring, tp->rx_ring_dma);
1100 DPRINTK ("EXIT, returning -ENOMEM\n");
1105 tp->full_duplex = tp->duplex_lock;
1106 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1108 netdrv_init_ring (dev);
1109 netdrv_hw_start (dev);
1111 DPRINTK ("%s: netdrv_open() ioaddr %#lx IRQ %d"
1112 " GP Pins %2.2x %s-duplex.\n",
1113 dev->name, pci_resource_start (tp->pci_dev, 1),
1114 dev->irq, NETDRV_R8 (MediaStatus),
1115 tp->full_duplex ? "full" : "half");
1117 /* Set the timer to switch to check for link beat and perhaps switch
1118 to an alternate media type. */
1119 init_timer (&tp->timer);
1120 tp->timer.expires = jiffies + 3 * HZ;
1121 tp->timer.data = (unsigned long) dev;
1122 tp->timer.function = &netdrv_timer;
1123 add_timer (&tp->timer);
1125 DPRINTK ("EXIT, returning 0\n");
1130 /* Start the hardware at open or resume. */
1131 static void netdrv_hw_start (struct net_device *dev)
1133 struct netdrv_private *tp = dev->priv;
1134 void *ioaddr = tp->mmio_addr;
1138 DPRINTK ("ENTER\n");
1140 /* Soft reset the chip. */
1141 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
1144 /* Check that the chip has finished the reset. */
1145 for (i = 1000; i > 0; i--)
1146 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
1149 /* Restore our idea of the MAC address. */
1150 NETDRV_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1151 NETDRV_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1153 /* Must enable Tx/Rx before setting transfer thresholds! */
1154 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1155 CmdRxEnb | CmdTxEnb);
1157 i = netdrv_rx_config |
1158 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1159 NETDRV_W32_F (RxConfig, i);
1161 /* Check this value: the documentation for IFG contradicts ifself. */
1162 NETDRV_W32 (TxConfig, (TX_DMA_BURST << TxDMAShift));
1164 /* unlock Config[01234] and BMCR register writes */
1165 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
1170 /* Lock Config[01234] and BMCR register writes */
1171 NETDRV_W8_F (Cfg9346, Cfg9346_Lock);
1174 /* init Rx ring buffer DMA address */
1175 NETDRV_W32_F (RxBuf, tp->rx_ring_dma);
1177 /* init Tx buffer DMA addresses */
1178 for (i = 0; i < NUM_TX_DESC; i++)
1179 NETDRV_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1181 NETDRV_W32_F (RxMissed, 0);
1183 netdrv_set_rx_mode (dev);
1185 /* no early-rx interrupts */
1186 NETDRV_W16 (MultiIntr, NETDRV_R16 (MultiIntr) & MultiIntrClear);
1188 /* make sure RxTx has started */
1189 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1190 CmdRxEnb | CmdTxEnb);
1192 /* Enable all known interrupts by setting the interrupt mask. */
1193 NETDRV_W16_F (IntrMask, netdrv_intr_mask);
1195 netif_start_queue (dev);
1201 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1202 static void netdrv_init_ring (struct net_device *dev)
1204 struct netdrv_private *tp = dev->priv;
1207 DPRINTK ("ENTER\n");
1210 atomic_set (&tp->cur_tx, 0);
1211 atomic_set (&tp->dirty_tx, 0);
1213 for (i = 0; i < NUM_TX_DESC; i++) {
1214 tp->tx_info[i].skb = NULL;
1215 tp->tx_info[i].mapping = 0;
1216 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1223 static void netdrv_timer (unsigned long data)
1225 struct net_device *dev = (struct net_device *) data;
1226 struct netdrv_private *tp = dev->priv;
1227 void *ioaddr = tp->mmio_addr;
1228 int next_tick = 60 * HZ;
1231 mii_reg5 = mdio_read (dev, tp->phys[0], 5);
1233 if (!tp->duplex_lock && mii_reg5 != 0xffff) {
1234 int duplex = (mii_reg5 & 0x0100)
1235 || (mii_reg5 & 0x01C0) == 0x0040;
1236 if (tp->full_duplex != duplex) {
1237 tp->full_duplex = duplex;
1239 "%s: Setting %s-duplex based on MII #%d link"
1240 " partner ability of %4.4x.\n", dev->name,
1241 tp->full_duplex ? "full" : "half",
1242 tp->phys[0], mii_reg5);
1243 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1244 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1245 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1249 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1250 dev->name, NETDRV_R16 (NWayLPAR));
1251 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x"
1252 " RxStatus %4.4x.\n", dev->name,
1253 NETDRV_R16 (IntrMask),
1254 NETDRV_R16 (IntrStatus),
1255 NETDRV_R32 (RxEarlyStatus));
1256 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1257 dev->name, NETDRV_R8 (Config0),
1258 NETDRV_R8 (Config1));
1260 tp->timer.expires = jiffies + next_tick;
1261 add_timer (&tp->timer);
1265 static void netdrv_tx_clear (struct netdrv_private *tp)
1269 atomic_set (&tp->cur_tx, 0);
1270 atomic_set (&tp->dirty_tx, 0);
1272 /* Dump the unsent Tx packets. */
1273 for (i = 0; i < NUM_TX_DESC; i++) {
1274 struct ring_info *rp = &tp->tx_info[i];
1275 if (rp->mapping != 0) {
1276 pci_unmap_single (tp->pci_dev, rp->mapping,
1277 rp->skb->len, PCI_DMA_TODEVICE);
1281 dev_kfree_skb (rp->skb);
1283 tp->stats.tx_dropped++;
1289 static void netdrv_tx_timeout (struct net_device *dev)
1291 struct netdrv_private *tp = dev->priv;
1292 void *ioaddr = tp->mmio_addr;
1295 unsigned long flags;
1297 DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1298 "media %2.2x.\n", dev->name,
1299 NETDRV_R8 (ChipCmd),
1300 NETDRV_R16 (IntrStatus),
1301 NETDRV_R8 (MediaStatus));
1303 /* disable Tx ASAP, if not already */
1304 tmp8 = NETDRV_R8 (ChipCmd);
1305 if (tmp8 & CmdTxEnb)
1306 NETDRV_W8 (ChipCmd, tmp8 & ~CmdTxEnb);
1308 /* Disable interrupts by clearing the interrupt mask. */
1309 NETDRV_W16 (IntrMask, 0x0000);
1311 /* Emit info to figure out what went wrong. */
1312 printk (KERN_DEBUG "%s: Tx queue start entry %d dirty entry %d.\n",
1313 dev->name, atomic_read (&tp->cur_tx),
1314 atomic_read (&tp->dirty_tx));
1315 for (i = 0; i < NUM_TX_DESC; i++)
1316 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1317 dev->name, i, NETDRV_R32 (TxStatus0 + (i * 4)),
1318 i == atomic_read (&tp->dirty_tx) % NUM_TX_DESC ?
1319 " (queue head)" : "");
1321 /* Stop a shared interrupt from scavenging while we are. */
1322 spin_lock_irqsave (&tp->lock, flags);
1324 netdrv_tx_clear (tp);
1326 spin_unlock_irqrestore (&tp->lock, flags);
1328 /* ...and finally, reset everything */
1329 netdrv_hw_start (dev);
1331 netif_wake_queue (dev);
1336 static int netdrv_start_xmit (struct sk_buff *skb, struct net_device *dev)
1338 struct netdrv_private *tp = dev->priv;
1339 void *ioaddr = tp->mmio_addr;
1342 /* Calculate the next Tx descriptor entry. */
1343 entry = atomic_read (&tp->cur_tx) % NUM_TX_DESC;
1345 assert (tp->tx_info[entry].skb == NULL);
1346 assert (tp->tx_info[entry].mapping == 0);
1348 tp->tx_info[entry].skb = skb;
1349 /* tp->tx_info[entry].mapping = 0; */
1350 memcpy (tp->tx_buf[entry], skb->data, skb->len);
1352 /* Note: the chip doesn't have auto-pad! */
1353 NETDRV_W32 (TxStatus0 + (entry * sizeof(u32)),
1354 tp->tx_flag | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1356 dev->trans_start = jiffies;
1357 atomic_inc (&tp->cur_tx);
1358 if ((atomic_read (&tp->cur_tx) - atomic_read (&tp->dirty_tx)) >= NUM_TX_DESC)
1359 netif_stop_queue (dev);
1361 DPRINTK ("%s: Queued Tx packet at %p size %u to slot %d.\n",
1362 dev->name, skb->data, skb->len, entry);
1368 static void netdrv_tx_interrupt (struct net_device *dev,
1369 struct netdrv_private *tp,
1372 int cur_tx, dirty_tx, tx_left;
1374 assert (dev != NULL);
1375 assert (tp != NULL);
1376 assert (ioaddr != NULL);
1378 dirty_tx = atomic_read (&tp->dirty_tx);
1380 cur_tx = atomic_read (&tp->cur_tx);
1381 tx_left = cur_tx - dirty_tx;
1382 while (tx_left > 0) {
1383 int entry = dirty_tx % NUM_TX_DESC;
1386 txstatus = NETDRV_R32 (TxStatus0 + (entry * sizeof (u32)));
1388 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1389 break; /* It still hasn't been Txed */
1391 /* Note: TxCarrierLost is always asserted at 100mbps. */
1392 if (txstatus & (TxOutOfWindow | TxAborted)) {
1393 /* There was an major error, log it. */
1394 DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
1395 dev->name, txstatus);
1396 tp->stats.tx_errors++;
1397 if (txstatus & TxAborted) {
1398 tp->stats.tx_aborted_errors++;
1399 NETDRV_W32 (TxConfig, TxClearAbt | (TX_DMA_BURST << TxDMAShift));
1401 if (txstatus & TxCarrierLost)
1402 tp->stats.tx_carrier_errors++;
1403 if (txstatus & TxOutOfWindow)
1404 tp->stats.tx_window_errors++;
1406 if ((txstatus & 0x0f000000) == 0x0f000000)
1407 tp->stats.collisions16++;
1410 if (txstatus & TxUnderrun) {
1411 /* Add 64 to the Tx FIFO threshold. */
1412 if (tp->tx_flag < 0x00300000)
1413 tp->tx_flag += 0x00020000;
1414 tp->stats.tx_fifo_errors++;
1416 tp->stats.collisions += (txstatus >> 24) & 15;
1417 tp->stats.tx_bytes += txstatus & 0x7ff;
1418 tp->stats.tx_packets++;
1421 /* Free the original skb. */
1422 if (tp->tx_info[entry].mapping != 0) {
1423 pci_unmap_single(tp->pci_dev,
1424 tp->tx_info[entry].mapping,
1425 tp->tx_info[entry].skb->len,
1427 tp->tx_info[entry].mapping = 0;
1429 dev_kfree_skb_irq (tp->tx_info[entry].skb);
1430 tp->tx_info[entry].skb = NULL;
1432 if (dirty_tx < 0) { /* handle signed int overflow */
1433 atomic_sub (cur_tx, &tp->cur_tx); /* XXX racy? */
1434 dirty_tx = cur_tx - tx_left + 1;
1436 if (netif_queue_stopped (dev))
1437 netif_wake_queue (dev);
1439 cur_tx = atomic_read (&tp->cur_tx);
1440 tx_left = cur_tx - dirty_tx;
1444 #ifndef NETDRV_NDEBUG
1445 if (atomic_read (&tp->cur_tx) - dirty_tx > NUM_TX_DESC) {
1447 "%s: Out-of-sync dirty pointer, %d vs. %d.\n",
1448 dev->name, dirty_tx, atomic_read (&tp->cur_tx));
1449 dirty_tx += NUM_TX_DESC;
1451 #endif /* NETDRV_NDEBUG */
1453 atomic_set (&tp->dirty_tx, dirty_tx);
1457 /* TODO: clean this up! Rx reset need not be this intensive */
1458 static void netdrv_rx_err (u32 rx_status, struct net_device *dev,
1459 struct netdrv_private *tp, void *ioaddr)
1462 int tmp_work = 1000;
1464 DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
1465 dev->name, rx_status);
1466 if (rx_status & RxTooLong) {
1467 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1468 dev->name, rx_status);
1469 /* A.C.: The chip hangs here. */
1471 tp->stats.rx_errors++;
1472 if (rx_status & (RxBadSymbol | RxBadAlign))
1473 tp->stats.rx_frame_errors++;
1474 if (rx_status & (RxRunt | RxTooLong))
1475 tp->stats.rx_length_errors++;
1476 if (rx_status & RxCRCErr)
1477 tp->stats.rx_crc_errors++;
1478 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1481 /* disable receive */
1482 tmp8 = NETDRV_R8 (ChipCmd) & ChipCmdClear;
1483 NETDRV_W8_F (ChipCmd, tmp8 | CmdTxEnb);
1485 /* A.C.: Reset the multicast list. */
1486 netdrv_set_rx_mode (dev);
1488 /* XXX potentially temporary hack to
1489 * restart hung receiver */
1490 while (--tmp_work > 0) {
1491 tmp8 = NETDRV_R8 (ChipCmd);
1492 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1494 NETDRV_W8_F (ChipCmd,
1495 (tmp8 & ChipCmdClear) | CmdRxEnb | CmdTxEnb);
1498 /* G.S.: Re-enable receiver */
1499 /* XXX temporary hack to work around receiver hang */
1500 netdrv_set_rx_mode (dev);
1503 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1507 /* The data sheet doesn't describe the Rx ring at all, so I'm guessing at the
1508 field alignments and semantics. */
1509 static void netdrv_rx_interrupt (struct net_device *dev,
1510 struct netdrv_private *tp, void *ioaddr)
1512 unsigned char *rx_ring;
1515 assert (dev != NULL);
1516 assert (tp != NULL);
1517 assert (ioaddr != NULL);
1519 rx_ring = tp->rx_ring;
1520 cur_rx = tp->cur_rx;
1522 DPRINTK ("%s: In netdrv_rx(), current %4.4x BufAddr %4.4x,"
1523 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1524 NETDRV_R16 (RxBufAddr),
1525 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1527 while ((NETDRV_R8 (ChipCmd) & RxBufEmpty) == 0) {
1528 int ring_offset = cur_rx % RX_BUF_LEN;
1530 unsigned int rx_size;
1531 unsigned int pkt_size;
1532 struct sk_buff *skb;
1534 /* read size+status of next frame from DMA ring buffer */
1535 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1536 rx_size = rx_status >> 16;
1537 pkt_size = rx_size - 4;
1539 DPRINTK ("%s: netdrv_rx() status %4.4x, size %4.4x,"
1540 " cur %4.4x.\n", dev->name, rx_status,
1542 #if NETDRV_DEBUG > 2
1545 DPRINTK ("%s: Frame contents ", dev->name);
1546 for (i = 0; i < 70; i++)
1548 rx_ring[ring_offset + i]);
1554 /* Note from BSD driver:
1555 * Here's a totally undocumented fact for you. When the
1556 * RealTek chip is in the process of copying a packet into
1557 * RAM for you, the length will be 0xfff0. If you spot a
1558 * packet header with this value, you need to stop. The
1559 * datasheet makes absolutely no mention of this and
1560 * RealTek should be shot for this.
1562 if (rx_size == 0xfff0)
1565 /* If Rx err or invalid rx_size/rx_status received
1566 * (which happens if we get lost in the ring),
1567 * Rx process gets reset, so we abort any further
1570 if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1571 (!(rx_status & RxStatusOK))) {
1572 netdrv_rx_err (rx_status, dev, tp, ioaddr);
1576 /* Malloc up new buffer, compatible with net-2e. */
1577 /* Omit the four octet CRC from the length. */
1579 /* TODO: consider allocating skb's outside of
1580 * interrupt context, both to speed interrupt processing,
1581 * and also to reduce the chances of having to
1582 * drop packets here under memory pressure.
1585 skb = dev_alloc_skb (pkt_size + 2);
1588 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
1590 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
1591 skb_put (skb, pkt_size);
1593 skb->protocol = eth_type_trans (skb, dev);
1595 dev->last_rx = jiffies;
1596 tp->stats.rx_bytes += pkt_size;
1597 tp->stats.rx_packets++;
1599 printk (KERN_WARNING
1600 "%s: Memory squeeze, dropping packet.\n",
1602 tp->stats.rx_dropped++;
1605 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1606 NETDRV_W16_F (RxBufPtr, cur_rx - 16);
1609 DPRINTK ("%s: Done netdrv_rx(), current %4.4x BufAddr %4.4x,"
1610 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1611 NETDRV_R16 (RxBufAddr),
1612 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1614 tp->cur_rx = cur_rx;
1618 static void netdrv_weird_interrupt (struct net_device *dev,
1619 struct netdrv_private *tp,
1621 int status, int link_changed)
1623 printk (KERN_DEBUG "%s: Abnormal interrupt, status %8.8x.\n",
1626 assert (dev != NULL);
1627 assert (tp != NULL);
1628 assert (ioaddr != NULL);
1630 /* Update the error count. */
1631 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1632 NETDRV_W32 (RxMissed, 0);
1634 if ((status & RxUnderrun) && link_changed &&
1635 (tp->drv_flags & HAS_LNK_CHNG)) {
1636 /* Really link-change on new chips. */
1637 int lpar = NETDRV_R16 (NWayLPAR);
1638 int duplex = (lpar & 0x0100) || (lpar & 0x01C0) == 0x0040
1640 if (tp->full_duplex != duplex) {
1641 tp->full_duplex = duplex;
1642 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1643 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1644 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1646 status &= ~RxUnderrun;
1649 /* XXX along with netdrv_rx_err, are we double-counting errors? */
1651 (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
1652 tp->stats.rx_errors++;
1654 if (status & (PCSTimeout))
1655 tp->stats.rx_length_errors++;
1656 if (status & (RxUnderrun | RxFIFOOver))
1657 tp->stats.rx_fifo_errors++;
1658 if (status & RxOverflow) {
1659 tp->stats.rx_over_errors++;
1660 tp->cur_rx = NETDRV_R16 (RxBufAddr) % RX_BUF_LEN;
1661 NETDRV_W16_F (RxBufPtr, tp->cur_rx - 16);
1663 if (status & PCIErr) {
1665 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
1667 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
1668 dev->name, pci_cmd_status);
1673 /* The interrupt handler does all of the Rx thread work and cleans up
1674 after the Tx thread. */
1675 static void netdrv_interrupt (int irq, void *dev_instance,
1676 struct pt_regs *regs)
1678 struct net_device *dev = (struct net_device *) dev_instance;
1679 struct netdrv_private *tp = dev->priv;
1680 int boguscnt = max_interrupt_work;
1681 void *ioaddr = tp->mmio_addr;
1682 int status = 0, link_changed = 0; /* avoid bogus "uninit" warning */
1684 spin_lock (&tp->lock);
1687 status = NETDRV_R16 (IntrStatus);
1689 /* h/w no longer present (hotplug?) or major error, bail */
1690 if (status == 0xFFFF)
1693 /* Acknowledge all of the current interrupt sources ASAP */
1694 NETDRV_W16_F (IntrStatus, status);
1696 DPRINTK ("%s: interrupt status=%#4.4x new intstat=%#4.4x.\n",
1698 NETDRV_R16 (IntrStatus));
1701 (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1702 RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
1705 /* Check uncommon events with one test. */
1706 if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1707 RxFIFOOver | TxErr | RxErr))
1708 netdrv_weird_interrupt (dev, tp, ioaddr,
1709 status, link_changed);
1711 if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) /* Rx interrupt */
1712 netdrv_rx_interrupt (dev, tp, ioaddr);
1714 if (status & (TxOK | TxErr))
1715 netdrv_tx_interrupt (dev, tp, ioaddr);
1718 } while (boguscnt > 0);
1720 if (boguscnt <= 0) {
1721 printk (KERN_WARNING
1722 "%s: Too much work at interrupt, "
1723 "IntrStatus=0x%4.4x.\n", dev->name,
1726 /* Clear all interrupt sources. */
1727 NETDRV_W16 (IntrStatus, 0xffff);
1730 spin_unlock (&tp->lock);
1732 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
1733 dev->name, NETDRV_R16 (IntrStatus));
1737 static int netdrv_close (struct net_device *dev)
1739 struct netdrv_private *tp = dev->priv;
1740 void *ioaddr = tp->mmio_addr;
1741 unsigned long flags;
1743 DPRINTK ("ENTER\n");
1745 netif_stop_queue (dev);
1747 DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
1748 dev->name, NETDRV_R16 (IntrStatus));
1750 del_timer_sync (&tp->timer);
1752 spin_lock_irqsave (&tp->lock, flags);
1754 /* Stop the chip's Tx and Rx DMA processes. */
1755 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1757 /* Disable interrupts by clearing the interrupt mask. */
1758 NETDRV_W16 (IntrMask, 0x0000);
1760 /* Update the error counts. */
1761 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1762 NETDRV_W32 (RxMissed, 0);
1764 spin_unlock_irqrestore (&tp->lock, flags);
1767 free_irq (dev->irq, dev);
1769 netdrv_tx_clear (tp);
1771 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1772 tp->rx_ring, tp->rx_ring_dma);
1773 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1774 tp->tx_bufs, tp->tx_bufs_dma);
1778 /* Green! Put the chip in low-power mode. */
1779 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1780 NETDRV_W8 (Config1, 0x03);
1781 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1788 static int mii_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1790 struct netdrv_private *tp = dev->priv;
1791 u16 *data = (u16 *) & rq->ifr_data;
1792 unsigned long flags;
1795 DPRINTK ("ENTER\n");
1798 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
1799 data[0] = tp->phys[0] & 0x3f;
1802 case SIOCDEVPRIVATE + 1: /* Read the specified MII register. */
1803 spin_lock_irqsave (&tp->lock, flags);
1804 data[3] = mdio_read (dev, data[0], data[1] & 0x1f);
1805 spin_unlock_irqrestore (&tp->lock, flags);
1808 case SIOCDEVPRIVATE + 2: /* Write the specified MII register */
1809 if (!capable (CAP_NET_ADMIN)) {
1814 spin_lock_irqsave (&tp->lock, flags);
1815 mdio_write (dev, data[0], data[1] & 0x1f, data[2]);
1816 spin_unlock_irqrestore (&tp->lock, flags);
1824 DPRINTK ("EXIT, returning %d\n", rc);
1829 static struct net_device_stats *netdrv_get_stats (struct net_device *dev)
1831 struct netdrv_private *tp = dev->priv;
1832 void *ioaddr = tp->mmio_addr;
1834 DPRINTK ("ENTER\n");
1836 assert (tp != NULL);
1838 if (netif_running(dev)) {
1839 unsigned long flags;
1841 spin_lock_irqsave (&tp->lock, flags);
1843 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1844 NETDRV_W32 (RxMissed, 0);
1846 spin_unlock_irqrestore (&tp->lock, flags);
1853 /* Set or clear the multicast filter for this adaptor.
1854 This routine is not state sensitive and need not be SMP locked. */
1856 static unsigned const ethernet_polynomial = 0x04c11db7U;
1857 static inline u32 ether_crc (int length, unsigned char *data)
1861 DPRINTK ("ENTER\n");
1863 while (--length >= 0) {
1864 unsigned char current_octet = *data++;
1866 for (bit = 0; bit < 8; bit++, current_octet >>= 1)
1868 ((crc < 0) ^ (current_octet & 1) ?
1869 ethernet_polynomial : 0);
1877 static void netdrv_set_rx_mode (struct net_device *dev)
1879 struct netdrv_private *tp = dev->priv;
1880 void *ioaddr = tp->mmio_addr;
1881 u32 mc_filter[2]; /* Multicast hash filter */
1885 DPRINTK ("ENTER\n");
1887 DPRINTK ("%s: netdrv_set_rx_mode(%4.4x) done -- Rx config %8.8x.\n",
1888 dev->name, dev->flags, NETDRV_R32 (RxConfig));
1890 /* Note: do not reorder, GCC is clever about common statements. */
1891 if (dev->flags & IFF_PROMISC) {
1892 /* Unconditionally log net taps. */
1893 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1896 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1898 mc_filter[1] = mc_filter[0] = 0xffffffff;
1899 } else if ((dev->mc_count > multicast_filter_limit)
1900 || (dev->flags & IFF_ALLMULTI)) {
1901 /* Too many to filter perfectly -- accept all multicasts. */
1902 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1903 mc_filter[1] = mc_filter[0] = 0xffffffff;
1905 struct dev_mc_list *mclist;
1906 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1907 mc_filter[1] = mc_filter[0] = 0;
1908 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1909 i++, mclist = mclist->next)
1910 set_bit (ether_crc (ETH_ALEN, mclist->dmi_addr) >> 26,
1914 /* if called from irq handler, lock already acquired */
1916 spin_lock_irq (&tp->lock);
1918 /* We can safely update without stopping the chip. */
1919 tmp = netdrv_rx_config | rx_mode |
1920 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1921 NETDRV_W32_F (RxConfig, tmp);
1922 NETDRV_W32_F (MAR0 + 0, mc_filter[0]);
1923 NETDRV_W32_F (MAR0 + 4, mc_filter[1]);
1926 spin_unlock_irq (&tp->lock);
1932 static void netdrv_suspend (struct pci_dev *pdev)
1934 struct net_device *dev = pci_get_drvdata (pdev);
1935 struct netdrv_private *tp = dev->priv;
1936 void *ioaddr = tp->mmio_addr;
1937 unsigned long flags;
1939 if (!netif_running(dev))
1941 netif_device_detach (dev);
1943 spin_lock_irqsave (&tp->lock, flags);
1945 /* Disable interrupts, stop Tx and Rx. */
1946 NETDRV_W16 (IntrMask, 0x0000);
1947 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1949 /* Update the error counts. */
1950 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1951 NETDRV_W32 (RxMissed, 0);
1953 spin_unlock_irqrestore (&tp->lock, flags);
1955 pci_power_off (pdev, -1);
1959 static void netdrv_resume (struct pci_dev *pdev)
1961 struct net_device *dev = pci_get_drvdata (pdev);
1963 if (!netif_running(dev))
1965 pci_power_on (pdev);
1966 netif_device_attach (dev);
1967 netdrv_hw_start (dev);
1971 static struct pci_driver netdrv_pci_driver = {
1973 id_table: netdrv_pci_tbl,
1974 probe: netdrv_init_one,
1975 remove: netdrv_remove_one,
1976 suspend: netdrv_suspend,
1977 resume: netdrv_resume,
1981 static int __init netdrv_init_module (void)
1983 return pci_module_init (&netdrv_pci_driver);
1987 static void __exit netdrv_cleanup_module (void)
1989 pci_unregister_driver (&netdrv_pci_driver);
1993 module_init(netdrv_init_module);
1994 module_exit(netdrv_cleanup_module);