2 * sata_svw.c - ServerWorks / Apple K2 SATA
4 * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
5 * Jeff Garzik <jgarzik@pobox.com>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
11 * Bits from Jeff Garzik, Copyright RedHat, Inc.
13 * This driver probably works with non-Apple versions of the
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2, or (at your option)
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; see the file COPYING. If not, write to
29 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
32 * libata documentation is available via 'make {ps|pdf}docs',
33 * as Documentation/DocBook/libata.*
35 * Hardware documentation available under NDA.
39 #include <linux/config.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/pci.h>
43 #include <linux/init.h>
44 #include <linux/blkdev.h>
45 #include <linux/delay.h>
46 #include <linux/interrupt.h>
47 #include <linux/device.h>
48 #include <scsi/scsi_host.h>
49 #include <linux/libata.h>
53 #include <asm/pci-bridge.h>
54 #endif /* CONFIG_PPC_OF */
56 #define DRV_NAME "sata_svw"
57 #define DRV_VERSION "1.07"
60 /* Taskfile registers offsets */
61 K2_SATA_TF_CMD_OFFSET = 0x00,
62 K2_SATA_TF_DATA_OFFSET = 0x00,
63 K2_SATA_TF_ERROR_OFFSET = 0x04,
64 K2_SATA_TF_NSECT_OFFSET = 0x08,
65 K2_SATA_TF_LBAL_OFFSET = 0x0c,
66 K2_SATA_TF_LBAM_OFFSET = 0x10,
67 K2_SATA_TF_LBAH_OFFSET = 0x14,
68 K2_SATA_TF_DEVICE_OFFSET = 0x18,
69 K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,
70 K2_SATA_TF_CTL_OFFSET = 0x20,
73 K2_SATA_DMA_CMD_OFFSET = 0x30,
76 K2_SATA_SCR_STATUS_OFFSET = 0x40,
77 K2_SATA_SCR_ERROR_OFFSET = 0x44,
78 K2_SATA_SCR_CONTROL_OFFSET = 0x48,
81 K2_SATA_SICR1_OFFSET = 0x80,
82 K2_SATA_SICR2_OFFSET = 0x84,
83 K2_SATA_SIM_OFFSET = 0x88,
86 K2_SATA_PORT_OFFSET = 0x100,
89 static u8 k2_stat_check_status(struct ata_port *ap);
92 static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
94 if (sc_reg > SCR_CONTROL)
96 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
100 static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
103 if (sc_reg > SCR_CONTROL)
105 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
109 static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
111 struct ata_ioports *ioaddr = &ap->ioaddr;
112 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
114 if (tf->ctl != ap->last_ctl) {
115 writeb(tf->ctl, (void __iomem *) ioaddr->ctl_addr);
116 ap->last_ctl = tf->ctl;
119 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
120 writew(tf->feature | (((u16)tf->hob_feature) << 8),
121 (void __iomem *) ioaddr->feature_addr);
122 writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
123 (void __iomem *) ioaddr->nsect_addr);
124 writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
125 (void __iomem *) ioaddr->lbal_addr);
126 writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
127 (void __iomem *) ioaddr->lbam_addr);
128 writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
129 (void __iomem *) ioaddr->lbah_addr);
130 } else if (is_addr) {
131 writew(tf->feature, (void __iomem *) ioaddr->feature_addr);
132 writew(tf->nsect, (void __iomem *) ioaddr->nsect_addr);
133 writew(tf->lbal, (void __iomem *) ioaddr->lbal_addr);
134 writew(tf->lbam, (void __iomem *) ioaddr->lbam_addr);
135 writew(tf->lbah, (void __iomem *) ioaddr->lbah_addr);
138 if (tf->flags & ATA_TFLAG_DEVICE)
139 writeb(tf->device, (void __iomem *) ioaddr->device_addr);
145 static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
147 struct ata_ioports *ioaddr = &ap->ioaddr;
148 u16 nsect, lbal, lbam, lbah, feature;
150 tf->command = k2_stat_check_status(ap);
151 tf->device = readw((void __iomem *) ioaddr->device_addr);
152 feature = readw((void __iomem *) ioaddr->error_addr);
153 nsect = readw((void __iomem *) ioaddr->nsect_addr);
154 lbal = readw((void __iomem *) ioaddr->lbal_addr);
155 lbam = readw((void __iomem *) ioaddr->lbam_addr);
156 lbah = readw((void __iomem *) ioaddr->lbah_addr);
158 tf->feature = feature;
164 if (tf->flags & ATA_TFLAG_LBA48) {
165 tf->hob_feature = feature >> 8;
166 tf->hob_nsect = nsect >> 8;
167 tf->hob_lbal = lbal >> 8;
168 tf->hob_lbam = lbam >> 8;
169 tf->hob_lbah = lbah >> 8;
174 * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
175 * @qc: Info associated with this ATA transaction.
178 * spin_lock_irqsave(host_set lock)
181 static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
183 struct ata_port *ap = qc->ap;
184 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
186 void *mmio = (void *) ap->ioaddr.bmdma_addr;
187 /* load PRD table addr. */
188 mb(); /* make sure PRD table writes are visible to controller */
189 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
191 /* specify data direction, triple-check start bit is clear */
192 dmactl = readb(mmio + ATA_DMA_CMD);
193 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
195 dmactl |= ATA_DMA_WR;
196 writeb(dmactl, mmio + ATA_DMA_CMD);
198 /* issue r/w command if this is not a ATA DMA command*/
199 if (qc->tf.protocol != ATA_PROT_DMA)
200 ap->ops->exec_command(ap, &qc->tf);
204 * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
205 * @qc: Info associated with this ATA transaction.
208 * spin_lock_irqsave(host_set lock)
211 static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
213 struct ata_port *ap = qc->ap;
214 void *mmio = (void *) ap->ioaddr.bmdma_addr;
217 /* start host DMA transaction */
218 dmactl = readb(mmio + ATA_DMA_CMD);
219 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
220 /* There is a race condition in certain SATA controllers that can
221 be seen when the r/w command is given to the controller before the
222 host DMA is started. On a Read command, the controller would initiate
223 the command to the drive even before it sees the DMA start. When there
224 are very fast drives connected to the controller, or when the data request
225 hits in the drive cache, there is the possibility that the drive returns a part
226 or all of the requested data to the controller before the DMA start is issued.
227 In this case, the controller would become confused as to what to do with the data.
228 In the worst case when all the data is returned back to the controller, the
229 controller could hang. In other cases it could return partial data returning
230 in data corruption. This problem has been seen in PPC systems and can also appear
231 on an system with very fast disks, where the SATA controller is sitting behind a
232 number of bridges, and hence there is significant latency between the r/w command
233 and the start command. */
234 /* issue r/w command if the access is to ATA*/
235 if (qc->tf.protocol == ATA_PROT_DMA)
236 ap->ops->exec_command(ap, &qc->tf);
240 static u8 k2_stat_check_status(struct ata_port *ap)
242 return readl((void *) ap->ioaddr.status_addr);
248 * inout : decides on the direction of the dataflow and the meaning of the
250 * buffer: If inout==FALSE data is being written to it else read from it
251 * *start: If inout==FALSE start of the valid data in the buffer
252 * offset: If inout==FALSE offset from the beginning of the imaginary file
253 * from which we start writing into the buffer
254 * length: If inout==FALSE max number of bytes to be written into the buffer
255 * else number of bytes in the buffer
257 static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
258 off_t offset, int count, int inout)
261 struct device_node *np;
264 /* Find the ata_port */
265 ap = (struct ata_port *) &shost->hostdata[0];
269 /* Find the OF node for the PCI device proper */
270 np = pci_device_to_OF_node(to_pci_dev(ap->host_set->dev));
274 /* Match it to a port node */
275 index = (ap == ap->host_set->ports[0]) ? 0 : 1;
276 for (np = np->child; np != NULL; np = np->sibling) {
277 u32 *reg = (u32 *)get_property(np, "reg", NULL);
286 len = sprintf(page, "devspec: %s\n", np->full_name);
290 #endif /* CONFIG_PPC_OF */
293 static struct scsi_host_template k2_sata_sht = {
294 .module = THIS_MODULE,
296 .ioctl = ata_scsi_ioctl,
297 .queuecommand = ata_scsi_queuecmd,
298 .can_queue = ATA_DEF_QUEUE,
299 .this_id = ATA_SHT_THIS_ID,
300 .sg_tablesize = LIBATA_MAX_PRD,
301 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
302 .emulated = ATA_SHT_EMULATED,
303 .use_clustering = ATA_SHT_USE_CLUSTERING,
304 .proc_name = DRV_NAME,
305 .dma_boundary = ATA_DMA_BOUNDARY,
306 .slave_configure = ata_scsi_slave_config,
308 .proc_info = k2_sata_proc_info,
310 .bios_param = ata_std_bios_param,
314 static const struct ata_port_operations k2_sata_ops = {
315 .port_disable = ata_port_disable,
316 .tf_load = k2_sata_tf_load,
317 .tf_read = k2_sata_tf_read,
318 .check_status = k2_stat_check_status,
319 .exec_command = ata_exec_command,
320 .dev_select = ata_std_dev_select,
321 .phy_reset = sata_phy_reset,
322 .bmdma_setup = k2_bmdma_setup_mmio,
323 .bmdma_start = k2_bmdma_start_mmio,
324 .bmdma_stop = ata_bmdma_stop,
325 .bmdma_status = ata_bmdma_status,
326 .qc_prep = ata_qc_prep,
327 .qc_issue = ata_qc_issue_prot,
328 .eng_timeout = ata_eng_timeout,
329 .irq_handler = ata_interrupt,
330 .irq_clear = ata_bmdma_irq_clear,
331 .scr_read = k2_sata_scr_read,
332 .scr_write = k2_sata_scr_write,
333 .port_start = ata_port_start,
334 .port_stop = ata_port_stop,
335 .host_stop = ata_pci_host_stop,
338 static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base)
340 port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
341 port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
343 port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
344 port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
345 port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
346 port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
347 port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
348 port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
350 port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
351 port->altstatus_addr =
352 port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
353 port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
354 port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
358 static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
360 static int printed_version;
361 struct ata_probe_ent *probe_ent = NULL;
363 void __iomem *mmio_base;
364 int pci_dev_busy = 0;
368 if (!printed_version++)
369 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
372 * If this driver happens to only be useful on Apple's K2, then
373 * we should check that here as it has a normal Serverworks ID
375 rc = pci_enable_device(pdev);
379 * Check if we have resources mapped at all (second function may
380 * have been disabled by firmware)
382 if (pci_resource_len(pdev, 5) == 0)
385 /* Request PCI regions */
386 rc = pci_request_regions(pdev, DRV_NAME);
392 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
394 goto err_out_regions;
395 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
397 goto err_out_regions;
399 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
400 if (probe_ent == NULL) {
402 goto err_out_regions;
405 memset(probe_ent, 0, sizeof(*probe_ent));
406 probe_ent->dev = pci_dev_to_dev(pdev);
407 INIT_LIST_HEAD(&probe_ent->node);
409 mmio_base = pci_iomap(pdev, 5, 0);
410 if (mmio_base == NULL) {
412 goto err_out_free_ent;
414 base = (unsigned long) mmio_base;
416 /* Clear a magic bit in SCR1 according to Darwin, those help
417 * some funky seagate drives (though so far, those were already
418 * set by the firmware on the machines I had access to)
420 writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
421 mmio_base + K2_SATA_SICR1_OFFSET);
423 /* Clear SATA error & interrupts we don't use */
424 writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
425 writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
427 probe_ent->sht = &k2_sata_sht;
428 probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET |
429 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO;
430 probe_ent->port_ops = &k2_sata_ops;
431 probe_ent->n_ports = 4;
432 probe_ent->irq = pdev->irq;
433 probe_ent->irq_flags = SA_SHIRQ;
434 probe_ent->mmio_base = mmio_base;
436 /* We don't care much about the PIO/UDMA masks, but the core won't like us
437 * if we don't fill these
439 probe_ent->pio_mask = 0x1f;
440 probe_ent->mwdma_mask = 0x7;
441 probe_ent->udma_mask = 0x7f;
443 /* different controllers have different number of ports - currently 4 or 8 */
444 /* All ports are on the same function. Multi-function device is no
445 * longer available. This should not be seen in any system. */
446 for (i = 0; i < ent->driver_data; i++)
447 k2_sata_setup_port(&probe_ent->port[i], base + i * K2_SATA_PORT_OFFSET);
449 pci_set_master(pdev);
451 /* FIXME: check ata_device_add return value */
452 ata_device_add(probe_ent);
460 pci_release_regions(pdev);
463 pci_disable_device(pdev);
467 /* 0x240 is device ID for Apple K2 device
468 * 0x241 is device ID for Serverworks Frodo4
469 * 0x242 is device ID for Serverworks Frodo8
470 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
473 static const struct pci_device_id k2_sata_pci_tbl[] = {
474 { 0x1166, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
475 { 0x1166, 0x0241, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
476 { 0x1166, 0x0242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
477 { 0x1166, 0x024a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
478 { 0x1166, 0x024b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
483 static struct pci_driver k2_sata_pci_driver = {
485 .id_table = k2_sata_pci_tbl,
486 .probe = k2_sata_init_one,
487 .remove = ata_pci_remove_one,
491 static int __init k2_sata_init(void)
493 return pci_module_init(&k2_sata_pci_driver);
497 static void __exit k2_sata_exit(void)
499 pci_unregister_driver(&k2_sata_pci_driver);
503 MODULE_AUTHOR("Benjamin Herrenschmidt");
504 MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
505 MODULE_LICENSE("GPL");
506 MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
507 MODULE_VERSION(DRV_VERSION);
509 module_init(k2_sata_init);
510 module_exit(k2_sata_exit);