1 /* *********************************************************************
2 * SB1250 Board Support Package
4 * SCD Constants and Macros File: sb1250_scd.h
6 * This module contains constants and macros useful for
7 * manipulating the System Control and Debug module on the 1250.
9 * SB1250 specification level: User's manual 1/02/02
11 * Author: Mitch Lichtenberg (mpl@broadcom.com)
13 *********************************************************************
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 ********************************************************************* */
37 #include "sb1250_defs.h"
39 /* *********************************************************************
40 * System control/debug registers
41 ********************************************************************* */
44 * System Revision Register (Table 4-1)
47 #define M_SYS_RESERVED _SB_MAKEMASK(8,0)
49 #define S_SYS_REVISION _SB_MAKE64(8)
50 #define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION)
51 #define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION)
52 #define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION)
54 #if SIBYTE_HDR_FEATURE_CHIP(1250)
55 #define K_SYS_REVISION_BCM1250_PASS1 1
56 #define K_SYS_REVISION_BCM1250_PASS2 3
57 #define K_SYS_REVISION_BCM1250_A10 11
58 #define K_SYS_REVISION_BCM1250_PASS2_2 16
59 #define K_SYS_REVISION_BCM1250_B2 17
60 #define K_SYS_REVISION_BCM1250_PASS3 32
62 /* XXX: discourage people from using these constants. */
63 #define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1
64 #define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2
65 #define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2
66 #define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3
69 #if SIBYTE_HDR_FEATURE_CHIP(112x)
70 #define K_SYS_REVISION_BCM112x_A1 32
71 #define K_SYS_REVISION_BCM112x_A2 33
74 /* XXX: discourage people from using these constants. */
75 #define S_SYS_PART _SB_MAKE64(16)
76 #define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART)
77 #define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART)
78 #define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART)
80 /* XXX: discourage people from using these constants. */
81 #define K_SYS_PART_SB1250 0x1250
82 #define K_SYS_PART_BCM1120 0x1121
83 #define K_SYS_PART_BCM1125 0x1123
84 #define K_SYS_PART_BCM1125H 0x1124
86 /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */
87 #define S_SYS_SOC_TYPE _SB_MAKE64(16)
88 #define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE)
89 #define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE)
90 #define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE)
92 #define K_SYS_SOC_TYPE_BCM1250 0x0
93 #define K_SYS_SOC_TYPE_BCM1120 0x1
94 #define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */
95 #define K_SYS_SOC_TYPE_BCM1125 0x3
96 #define K_SYS_SOC_TYPE_BCM1125H 0x4
97 #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */
100 * Calculate correct SOC type given a copy of system revision register.
102 * (For the assembler version, sysrev and dest may be the same register.
103 * Also, it clobbers AT.)
106 #define SYS_SOC_TYPE(dest, sysrev) \
109 dsrl dest, sysrev, S_SYS_SOC_TYPE ; \
110 andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \
111 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \
112 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \
114 991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \
118 #define SYS_SOC_TYPE(sysrev) \
119 ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \
120 || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \
121 ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev))
124 #define S_SYS_WID _SB_MAKE64(32)
125 #define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID)
126 #define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID)
127 #define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID)
130 * System Config Register (Table 4-2)
131 * Register: SCD_SYSTEM_CFG
134 #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3)
135 #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4)
136 #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5)
137 #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6)
139 #define S_SYS_PLL_DIV _SB_MAKE64(7)
140 #define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV)
141 #define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV)
142 #define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV)
144 #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12)
145 #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13)
146 #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14)
147 #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15)
148 #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
150 #define S_SYS_BOOT_MODE _SB_MAKE64(17)
151 #define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE)
152 #define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE)
153 #define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE)
154 #define K_SYS_BOOT_MODE_ROM32 0
155 #define K_SYS_BOOT_MODE_ROM8 1
156 #define K_SYS_BOOT_MODE_SMBUS_SMALL 2
157 #define K_SYS_BOOT_MODE_SMBUS_BIG 3
159 #define M_SYS_PCI_HOST _SB_MAKEMASK1(19)
160 #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20)
161 #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21)
162 #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22)
163 #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23)
164 #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24)
165 #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25)
167 #define S_SYS_CONFIG 26
168 #define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG)
169 #define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG)
170 #define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG)
172 /* The following bits are writeable by JTAG only. */
174 #define M_SYS_CLKSTOP _SB_MAKEMASK1(32)
175 #define M_SYS_CLKSTEP _SB_MAKEMASK1(33)
177 #define S_SYS_CLKCOUNT 34
178 #define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT)
179 #define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT)
180 #define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT)
182 #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42)
184 #define S_SYS_PLL_IREF 43
185 #define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF)
187 #define S_SYS_PLL_VCO 45
188 #define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO)
190 #define S_SYS_PLL_VREG 47
191 #define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG)
193 #define M_SYS_MEM_RESET _SB_MAKEMASK1(49)
194 #define M_SYS_L2C_RESET _SB_MAKEMASK1(50)
195 #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51)
196 #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52)
197 #define M_SYS_SCD_RESET _SB_MAKEMASK1(53)
199 /* End of bits writable by JTAG only. */
201 #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54)
202 #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55)
204 #define M_SYS_UNICPU0 _SB_MAKEMASK1(56)
205 #define M_SYS_UNICPU1 _SB_MAKEMASK1(57)
207 #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58)
208 #define M_SYS_EXT_RESET _SB_MAKEMASK1(59)
209 #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60)
211 #define M_SYS_MISR_MODE _SB_MAKEMASK1(61)
212 #define M_SYS_MISR_RESET _SB_MAKEMASK1(62)
214 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
215 #define M_SYS_SW_FLAG _SB_MAKEMASK1(63)
216 #endif /* 1250 PASS2 || 112x PASS1 */
220 * Mailbox Registers (Table 4-3)
221 * Registers: SCD_MBOX_CPU_x
224 #define S_MBOX_INT_3 0
225 #define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3)
226 #define S_MBOX_INT_2 16
227 #define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2)
228 #define S_MBOX_INT_1 32
229 #define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1)
230 #define S_MBOX_INT_0 48
231 #define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0)
234 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
235 * Registers: SCD_WDOG_INIT_CNT_x
238 #define V_SCD_WDOG_FREQ 1000000
240 #define S_SCD_WDOG_INIT 0
241 #define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT)
243 #define S_SCD_WDOG_CNT 0
244 #define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT)
246 #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(0)
249 * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13)
252 #define V_SCD_TIMER_FREQ 1000000
254 #define S_SCD_TIMER_INIT 0
255 #define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT)
256 #define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
257 #define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)
259 #define S_SCD_TIMER_CNT 0
260 #define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT)
261 #define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
262 #define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT)
264 #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0)
265 #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1)
266 #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE
269 * System Performance Counters
272 #define S_SPC_CFG_SRC0 0
273 #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0)
274 #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0)
275 #define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0)
277 #define S_SPC_CFG_SRC1 8
278 #define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1)
279 #define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1)
280 #define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1)
282 #define S_SPC_CFG_SRC2 16
283 #define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2)
284 #define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2)
285 #define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2)
287 #define S_SPC_CFG_SRC3 24
288 #define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3)
289 #define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3)
290 #define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3)
292 #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
293 #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33)
300 #define S_SCD_BERR_TID 8
301 #define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID)
302 #define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID)
303 #define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID)
305 #define S_SCD_BERR_RID 18
306 #define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID)
307 #define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID)
308 #define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID)
310 #define S_SCD_BERR_DCODE 22
311 #define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE)
312 #define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE)
313 #define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE)
315 #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30)
318 #define S_SCD_L2ECC_CORR_D 0
319 #define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D)
320 #define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D)
321 #define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D)
323 #define S_SCD_L2ECC_BAD_D 8
324 #define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D)
325 #define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D)
326 #define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D)
328 #define S_SCD_L2ECC_CORR_T 16
329 #define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T)
330 #define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T)
331 #define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T)
333 #define S_SCD_L2ECC_BAD_T 24
334 #define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T)
335 #define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T)
336 #define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T)
338 #define S_SCD_MEM_ECC_CORR 0
339 #define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR)
340 #define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR)
341 #define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR)
343 #define S_SCD_MEM_ECC_BAD 8
344 #define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD)
345 #define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD)
346 #define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD)
348 #define S_SCD_MEM_BUSERR 16
349 #define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR)
350 #define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR)
351 #define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR)
355 * Address Trap Registers
358 #define M_ATRAP_INDEX _SB_MAKEMASK(4,0)
359 #define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0)
361 #define S_ATRAP_CFG_CNT 0
362 #define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT)
363 #define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT)
364 #define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT)
366 #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
367 #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
368 #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5)
369 #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6)
370 #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
372 #define S_ATRAP_CFG_AGENTID 8
373 #define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID)
374 #define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID)
375 #define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID)
377 #define K_BUS_AGENT_CPU0 0
378 #define K_BUS_AGENT_CPU1 1
379 #define K_BUS_AGENT_IOB0 2
380 #define K_BUS_AGENT_IOB1 3
381 #define K_BUS_AGENT_SCD 4
382 #define K_BUS_AGENT_RESERVED 5
383 #define K_BUS_AGENT_L2C 6
384 #define K_BUS_AGENT_MC 7
386 #define S_ATRAP_CFG_CATTR 12
387 #define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR)
388 #define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR)
389 #define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR)
391 #define K_ATRAP_CFG_CATTR_IGNORE 0
392 #define K_ATRAP_CFG_CATTR_UNC 1
393 #define K_ATRAP_CFG_CATTR_CACHEABLE 2
394 #define K_ATRAP_CFG_CATTR_NONCOH 3
395 #define K_ATRAP_CFG_CATTR_COHERENT 4
396 #define K_ATRAP_CFG_CATTR_NOTUNC 5
397 #define K_ATRAP_CFG_CATTR_NOTNONCOH 6
398 #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7
401 * Trace Buffer Config register
404 #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
405 #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
406 #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
407 #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3)
408 #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4)
409 #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
410 #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
411 #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
412 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
413 #define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8)
414 #endif /* 1250 PASS2 || 112x PASS1 */
416 #define S_SCD_TRACE_CFG_CUR_ADDR 10
417 #define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR)
418 #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR)
419 #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR)
422 * Trace Event registers
425 #define S_SCD_TREVT_ADDR_MATCH 0
426 #define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH)
427 #define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH)
428 #define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH)
430 #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4)
431 #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5)
432 #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6)
433 #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7)
434 #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9)
435 #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10)
436 #define M_SCD_TREVT_READ _SB_MAKEMASK1(11)
438 #define S_SCD_TREVT_REQID 12
439 #define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID)
440 #define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID)
441 #define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID)
443 #define S_SCD_TREVT_RESPID 16
444 #define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID)
445 #define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID)
446 #define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID)
448 #define S_SCD_TREVT_DATAID 20
449 #define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID)
450 #define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID)
451 #define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID)
453 #define S_SCD_TREVT_COUNT 24
454 #define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT)
455 #define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT)
456 #define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT)
459 * Trace Sequence registers
462 #define S_SCD_TRSEQ_EVENT4 0
463 #define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4)
464 #define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4)
465 #define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4)
467 #define S_SCD_TRSEQ_EVENT3 4
468 #define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3)
469 #define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3)
470 #define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3)
472 #define S_SCD_TRSEQ_EVENT2 8
473 #define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2)
474 #define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2)
475 #define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2)
477 #define S_SCD_TRSEQ_EVENT1 12
478 #define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1)
479 #define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1)
480 #define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1)
482 #define K_SCD_TRSEQ_E0 0
483 #define K_SCD_TRSEQ_E1 1
484 #define K_SCD_TRSEQ_E2 2
485 #define K_SCD_TRSEQ_E3 3
486 #define K_SCD_TRSEQ_E0_E1 4
487 #define K_SCD_TRSEQ_E1_E2 5
488 #define K_SCD_TRSEQ_E2_E3 6
489 #define K_SCD_TRSEQ_E0_E1_E2 7
490 #define K_SCD_TRSEQ_E0_E1_E2_E3 8
491 #define K_SCD_TRSEQ_E0E1 9
492 #define K_SCD_TRSEQ_E0E1E2 10
493 #define K_SCD_TRSEQ_E0E1E2E3 11
494 #define K_SCD_TRSEQ_E0E1_E2 12
495 #define K_SCD_TRSEQ_E0E1_E2E3 13
496 #define K_SCD_TRSEQ_E0E1_E2_E3 14
497 #define K_SCD_TRSEQ_IGNORED 15
499 #define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \
500 V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \
501 V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \
502 V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED))
504 #define S_SCD_TRSEQ_FUNCTION 16
505 #define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION)
506 #define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION)
507 #define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION)
509 #define K_SCD_TRSEQ_FUNC_NOP 0
510 #define K_SCD_TRSEQ_FUNC_START 1
511 #define K_SCD_TRSEQ_FUNC_STOP 2
512 #define K_SCD_TRSEQ_FUNC_FREEZE 3
514 #define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP)
515 #define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START)
516 #define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP)
517 #define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE)
519 #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18)
520 #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19)
521 #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20)
522 #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21)
523 #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22)