1 #ifndef ASM_IA64_SN_SYNERGY_H
2 #define ASM_IA64_SN_SYNERGY_H
5 #include "asm/sn/intr_public.h"
9 * Definitions for the synergy asic driver
11 * These are for SGI platforms only.
13 * Copyright (C) 2000 Silicon Graphics, Inc
14 * Copyright (C) 2000 Alan Mayer (ajm@sgi.com)
18 #define SSPEC_BASE (0xe0000000000)
19 #define LB_REG_BASE (SSPEC_BASE + 0x0)
21 #define VEC_MASK3A_ADDR (0x2a0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
22 #define VEC_MASK3B_ADDR (0x2a8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
23 #define VEC_MASK3A (0x2a0)
24 #define VEC_MASK3B (0x2a8)
26 #define VEC_MASK2A_ADDR (0x2b0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
27 #define VEC_MASK2B_ADDR (0x2b8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
28 #define VEC_MASK2A (0x2b0)
29 #define VEC_MASK2B (0x2b8)
31 #define VEC_MASK1A_ADDR (0x2c0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
32 #define VEC_MASK1B_ADDR (0x2c8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
33 #define VEC_MASK1A (0x2c0)
34 #define VEC_MASK1B (0x2c8)
36 #define VEC_MASK0A_ADDR (0x2d0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
37 #define VEC_MASK0B_ADDR (0x2d8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
38 #define VEC_MASK0A (0x2d0)
39 #define VEC_MASK0B (0x2d8)
41 #define WRITE_LOCAL_SYNERGY_REG(addr, value) __synergy_out(addr, value)
43 #define HUBREG_CAST (volatile hubreg_t *)
44 #define NODE_OFFSET(_n) (UINT64_CAST (_n) << NODE_SIZE_BITS)
45 #define SYN_UNCACHED_SPACE 0xc000000000000000
46 #define NODE_HSPEC_BASE(_n) (HSPEC_BASE + NODE_OFFSET(_n))
47 #define NODE_LREG_BASE(_n) (NODE_HSPEC_BASE(_n) + 0x30000000)
48 #define RREG_BASE(_n) (NODE_LREG_BASE(_n))
49 #define REMOTE_HSPEC(_n, _x) (HUBREG_CAST (RREG_BASE(_n) + (_x)))
50 #define HSPEC_SYNERGY0_0 0x04000000 /* Synergy0 Registers */
51 #define HSPEC_SYNERGY1_0 0x05000000 /* Synergy1 Registers */
52 #define HS_SYNERGY_STRIDE (HSPEC_SYNERGY1_0 - HSPEC_SYNERGY0_0)
55 #define HUB_L(_a) *(_a)
56 #define HUB_S(_a, _d) *(_a) = (_d)
59 #define REMOTE_SYNERGY_LOAD(nasid, fsb, reg) __remote_synergy_in(nasid, fsb, reg)
60 #define REMOTE_SYNERGY_STORE(nasid, fsb, reg, val) __remote_synergy_out(nasid, fsb, reg, val)
63 __remote_synergy_out(int nasid, int fsb, unsigned long reg, unsigned long val) {
64 unsigned long addr = ((RREG_BASE(nasid)) +
65 ((HSPEC_SYNERGY0_0 | (fsb)*HS_SYNERGY_STRIDE) | ((reg) << 2)));
67 HUB_S((unsigned long *)(addr), (val) >> 48);
68 HUB_S((unsigned long *)(addr+0x08), (val) >> 32);
69 HUB_S((unsigned long *)(addr+0x10), (val) >> 16);
70 HUB_S((unsigned long *)(addr+0x18), (val) );
74 extern inline unsigned long
75 __remote_synergy_in(int nasid, int fsb, unsigned long reg) {
76 volatile unsigned long *addr = (unsigned long *) ((RREG_BASE(nasid)) +
77 ((HSPEC_SYNERGY0_0 | (fsb)*HS_SYNERGY_STRIDE) | (reg)));
86 __synergy_out(unsigned long addr, unsigned long value)
88 volatile unsigned long *adr = (unsigned long *)
89 (addr | __IA64_UNCACHED_OFFSET);
95 #define READ_LOCAL_SYNERGY_REG(addr) __synergy_in(addr)
97 extern inline unsigned long
98 __synergy_in(unsigned long addr)
100 unsigned long ret, *adr = (unsigned long *)
101 (addr | __IA64_UNCACHED_OFFSET);
108 struct sn1_intr_action {
109 void (*handler)(int, void *, struct pt_regs *);
112 struct sn1_intr_action * next;
115 typedef struct synergy_da_s {
116 hub_intmasks_t s_intmasks;
119 struct sn1_cnode_action_list {
120 spinlock_t action_list_lock;
121 struct sn1_intr_action *action_list;
125 /* Temporary defintions for testing: */
127 #endif ASM_IA64_SN_SYNERGY_H