2 * linux/include/asm-arm/arch-sa1100/assabet.h
4 * Created 2000/06/05 by Nicolas Pitre <nico@cam.org>
6 * This file contains the hardware specific definitions for Assabet
8 * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
9 * Definitions for Neponset added.
12 #ifndef __ASM_ARCH_HARDWARE_H
13 #error "include <asm/hardware.h> instead"
17 /* System Configuration Register flags */
19 #define SCR_SDRAM_LOW (1<<2) /* SDRAM size (low bit) */
20 #define SCR_SDRAM_HIGH (1<<3) /* SDRAM size (high bit) */
21 #define SCR_FLASH_LOW (1<<4) /* Flash size (low bit) */
22 #define SCR_FLASH_HIGH (1<<5) /* Flash size (high bit) */
23 #define SCR_GFX (1<<8) /* Graphics Accelerator (0 = present) */
24 #define SCR_SA1111 (1<<9) /* Neponset (0 = present) */
29 /* Board Control Register */
31 #define BCR_BASE 0xf1000000
32 #define BCR (*(volatile unsigned int *)(BCR_BASE))
34 #define BCR_DB1110 (0x00A07410)
35 #define BCR_DB1111 (0x00A07462)
37 #define BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */
38 #define BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */
39 #define BCR_GFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */
40 #define BCR_CODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */
41 #define BCR_IRDA_FSEL (1<<3) /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */
42 #define BCR_IRDA_MD0 (1<<4) /* Range/Power select */
43 #define BCR_IRDA_MD1 (1<<5) /* Range/Power select */
44 #define BCR_STEREO_LB (1<<6) /* Stereo Loopback */
45 #define BCR_CF_BUS_OFF (1<<7) /* Compact Flash bus (0 = on, 1 = off (float)) */
46 #define BCR_AUDIO_ON (1<<8) /* Audio power on */
47 #define BCR_LIGHT_ON (1<<9) /* Backlight */
48 #define BCR_LCD_12RGB (1<<10) /* 0 = 16RGB, 1 = 12RGB */
49 #define BCR_LCD_ON (1<<11) /* LCD power on */
50 #define BCR_RS232EN (1<<12) /* RS232 transceiver enable */
51 #define BCR_LED_RED (1<<13) /* D9 (0 = on, 1 = off) */
52 #define BCR_LED_GREEN (1<<14) /* D8 (0 = on, 1 = off) */
53 #define BCR_VIB_ON (1<<15) /* Vibration motor (quiet alert) */
54 #define BCR_COM_DTR (1<<16) /* COMport Data Terminal Ready */
55 #define BCR_COM_RTS (1<<17) /* COMport Request To Send */
56 #define BCR_RAD_WU (1<<18) /* Radio wake up interrupt */
57 #define BCR_SMB_EN (1<<19) /* System management bus enable */
58 #define BCR_TV_IR_DEC (1<<20) /* TV IR Decode Enable */
59 #define BCR_QMUTE (1<<21) /* Quick Mute */
60 #define BCR_RAD_ON (1<<22) /* Radio Power On */
61 #define BCR_SPK_OFF (1<<23) /* 1 = Speaker amplifier power off */
64 extern unsigned long SCR_value;
65 extern unsigned long BCR_value;
66 #define BCR_set( x ) BCR = (BCR_value |= (x))
67 #define BCR_clear( x ) BCR = (BCR_value &= ~(x))
71 /* GPIOs for which the generic definition doesn't say much */
72 #define GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */
73 #define GPIO_L3_I2C_SDA GPIO_GPIO (15) /* L3 and SMB control ports */
74 #define GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */
75 #define GPIO_L3_MODE GPIO_GPIO (17) /* L3 mode signal with LED */
76 #define GPIO_L3_I2C_SCL GPIO_GPIO (18) /* L3 and I2C control ports */
77 #define GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */
78 #define GPIO_CF_IRQ GPIO_GPIO (21) /* CF IRQ */
79 #define GPIO_MBGNT GPIO_GPIO (21) /* 1111 MBGNT */
80 #define GPIO_CF_CD GPIO_GPIO (22) /* CF CD */
81 #define GPIO_MBREQ GPIO_GPIO (22) /* 1111 MBREQ */
82 #define GPIO_UCB1300_IRQ GPIO_GPIO (23) /* UCB GPIO and touchscreen */
83 #define GPIO_CF_BVD2 GPIO_GPIO (24) /* CF BVD */
84 #define GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */
85 #define GPIO_CF_BVD1 GPIO_GPIO (25) /* CF BVD */
86 #define GPIO_NEP_IRQ GPIO_GPIO (25) /* Neponset IRQ */
87 #define GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */
88 #define GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */
90 #define IRQ_GPIO_CF_IRQ IRQ_GPIO21
91 #define IRQ_GPIO_CF_CD IRQ_GPIO22
92 #define IRQ_GPIO_UCB1300_IRQ IRQ_GPIO23
93 #define IRQ_GPIO_CF_BVD2 IRQ_GPIO24
94 #define IRQ_GPIO_CF_BVD1 IRQ_GPIO25
95 #define IRQ_GPIO_NEP_IRQ IRQ_GPIO25
99 * Neponset definitions:
102 #define SA1111_BASE (0x40000000)
104 #define NEPONSET_ETHERNET_IRQ MISC_IRQ0
105 #define NEPONSET_USAR_IRQ MISC_IRQ1
107 #define NEPONSET_CPLD_BASE (0x10000000)
108 #define Nep_p2v( x ) ((x) - NEPONSET_CPLD_BASE + 0xf0000000)
109 #define Nep_v2p( x ) ((x) - 0xf0000000 + NEPONSET_CPLD_BASE)
111 #define _IRR 0x10000024 /* Interrupt Reason Register */
112 #define _AUD_CTL 0x100000c0 /* Audio controls (RW) */
113 #define _MDM_CTL_0 0x100000b0 /* Modem control 0 (RW) */
114 #define _MDM_CTL_1 0x100000b4 /* Modem control 1 (RW) */
115 #define _NCR_0 0x100000a0 /* Control Register (RW) */
116 #define _KP_X_OUT 0x10000090 /* Keypad row write (RW) */
117 #define _KP_Y_IN 0x10000080 /* Keypad column read (RO) */
118 #define _SWPK 0x10000020 /* Switch pack (RO) */
119 #define _WHOAMI 0x10000000 /* System ID Register (RO) */
121 #define _LEDS 0x10000010 /* LEDs [31:0] (WO) */
125 #define IRR (*((volatile u_char *) Nep_p2v(_IRR)))
126 #define AUD_CTL (*((volatile u_char *) Nep_p2v(_AUD_CTL)))
127 #define MDM_CTL_0 (*((volatile u_char *) Nep_p2v(_MDM_CTL_0)))
128 #define MDM_CTL_1 (*((volatile u_char *) Nep_p2v(_MDM_CTL_1)))
129 #define NCR_0 (*((volatile u_char *) Nep_p2v(_NCR_0)))
130 #define KP_X_OUT (*((volatile u_char *) Nep_p2v(_KP_X_OUT)))
131 #define KP_Y_IN (*((volatile u_char *) Nep_p2v(_KP_Y_IN)))
132 #define SWPK (*((volatile u_char *) Nep_p2v(_SWPK)))
133 #define WHOAMI (*((volatile u_char *) Nep_p2v(_WHOAMI)))
135 #define LEDS (*((volatile Word *) Nep_p2v(_LEDS)))
139 #define IRR_ETHERNET (1<<0)
140 #define IRR_USAR (1<<1)
141 #define IRR_SA1111 (1<<2)
143 #define NCR_GP01_OFF (1<<0)
144 #define NCR_TP_PWR_EN (1<<1)
145 #define NCR_MS_PWR_EN (1<<2)
146 #define NCR_ENET_OSC_EN (1<<3)
147 #define NCR_SPI_KB_WK_UP (1<<4)
148 #define NCR_A0VPP (1<<5)
149 #define NCR_A1VPP (1<<6)
152 #define machine_has_neponset() ((SCR_value & SCR_SA1111) == 0)