drivers/ide/hpt366.c

   1 /*
   2  * linux/drivers/ide/hpt366.c           Version 0.18    June. 9, 2000
   3  *
   4  * Copyright (C) 1999-2000              Andre Hedrick <andre@linux-ide.org>
   5  * May be copied or modified under the terms of the GNU General Public License
   6  *
   7  * Thanks to HighPoint Technologies for their assistance, and hardware.
   8  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
   9  * donation of an ABit BP6 mainboard, processor, and memory acellerated
  10  * development and support.
  11  *
  12  * Note that final HPT370 support was done by force extraction of GPL.
  13  *
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/types.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/timer.h>
  21 #include <linux/mm.h>
  22 #include <linux/ioport.h>
  23 #include <linux/blkdev.h>
  24 #include <linux/hdreg.h>
  25
  26 #include <linux/interrupt.h>
  27 #include <linux/pci.h>
  28 #include <linux/init.h>
  29 #include <linux/ide.h>
  30
  31 #include <asm/io.h>
  32 #include <asm/irq.h>
  33
  34 #include "ide_modes.h"
  35
  36 #define DISPLAY_HPT366_TIMINGS
  37
  38 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
  39 #include <linux/stat.h>
  40 #include <linux/proc_fs.h>
  41 #endif  /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
  42
  43 extern char *ide_dmafunc_verbose(ide_dma_action_t dmafunc);
  44
  45 const char *quirk_drives[] = {
  46         "QUANTUM FIREBALLlct08 08",
  47         "QUANTUM FIREBALLP KA6.4",
  48         "QUANTUM FIREBALLP LM20.4",
  49         "QUANTUM FIREBALLP LM20.5",
  50         NULL
  51 };
  52
  53 const char *bad_ata100_5[] = {
  54         NULL
  55 };
  56
  57 const char *bad_ata66_4[] = {
  58         "WDC AC310200R",
  59         NULL
  60 };
  61
  62 const char *bad_ata66_3[] = {
  63         "WDC AC310200R",
  64         NULL
  65 };
  66
  67 const char *bad_ata33[] = {
  68         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
  69         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
  70         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
  71         "Maxtor 90510D4",
  72         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
  73         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
  74         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
  75         NULL
  76 };
  77
  78 struct chipset_bus_clock_list_entry {
  79         byte            xfer_speed;
  80         unsigned int    chipset_settings_write;
  81         unsigned int    chipset_settings_read;
  82 };
  83
  84 struct chipset_bus_clock_list_entry forty_base [] = {
  85
  86         {       XFER_UDMA_4,    0x900fd943,     0x900fd943      },
  87         {       XFER_UDMA_3,    0x900ad943,     0x900ad943      },
  88         {       XFER_UDMA_2,    0x900bd943,     0x900bd943      },
  89         {       XFER_UDMA_1,    0x9008d943,     0x9008d943      },
  90         {       XFER_UDMA_0,    0x9008d943,     0x9008d943      },
  91
  92         {       XFER_MW_DMA_2,  0xa008d943,     0xa008d943      },
  93         {       XFER_MW_DMA_1,  0xa010d955,     0xa010d955      },
  94         {       XFER_MW_DMA_0,  0xa010d9fc,     0xa010d9fc      },
  95
  96         {       XFER_PIO_4,     0xc008d963,     0xc008d963      },
  97         {       XFER_PIO_3,     0xc010d974,     0xc010d974      },
  98         {       XFER_PIO_2,     0xc010d997,     0xc010d997      },
  99         {       XFER_PIO_1,     0xc010d9c7,     0xc010d9c7      },
 100         {       XFER_PIO_0,     0xc018d9d9,     0xc018d9d9      },
 101         {       0,              0x0120d9d9,     0x0120d9d9      }
 102 };
 103
 104 struct chipset_bus_clock_list_entry thirty_three_base [] = {
 105
 106         {       XFER_UDMA_4,    0x90c9a731,     0x90c9a731      },
 107         {       XFER_UDMA_3,    0x90cfa731,     0x90cfa731      },
 108         {       XFER_UDMA_2,    0x90caa731,     0x90caa731      },
 109         {       XFER_UDMA_1,    0x90cba731,     0x90cba731      },
 110         {       XFER_UDMA_0,    0x90c8a731,     0x90c8a731      },
 111
 112         {       XFER_MW_DMA_2,  0xa0c8a731,     0xa0c8a731      },
 113         {       XFER_MW_DMA_1,  0xa0c8a732,     0xa0c8a732      },      /* 0xa0c8a733 */
 114         {       XFER_MW_DMA_0,  0xa0c8a797,     0xa0c8a797      },
 115
 116         {       XFER_PIO_4,     0xc0c8a731,     0xc0c8a731      },
 117         {       XFER_PIO_3,     0xc0c8a742,     0xc0c8a742      },
 118         {       XFER_PIO_2,     0xc0d0a753,     0xc0d0a753      },
 119         {       XFER_PIO_1,     0xc0d0a7a3,     0xc0d0a7a3      },      /* 0xc0d0a793 */
 120         {       XFER_PIO_0,     0xc0d0a7aa,     0xc0d0a7aa      },      /* 0xc0d0a7a7 */
 121         {       0,              0x0120a7a7,     0x0120a7a7      }
 122 };
 123
 124 struct chipset_bus_clock_list_entry twenty_five_base [] = {
 125
 126         {       XFER_UDMA_4,    0x90c98521,     0x90c98521      },
 127         {       XFER_UDMA_3,    0x90cf8521,     0x90cf8521      },
 128         {       XFER_UDMA_2,    0x90cf8521,     0x90cf8521      },
 129         {       XFER_UDMA_1,    0x90cb8521,     0x90cb8521      },
 130         {       XFER_UDMA_0,    0x90cb8521,     0x90cb8521      },
 131
 132         {       XFER_MW_DMA_2,  0xa0ca8521,     0xa0ca8521      },
 133         {       XFER_MW_DMA_1,  0xa0ca8532,     0xa0ca8532      },
 134         {       XFER_MW_DMA_0,  0xa0ca8575,     0xa0ca8575      },
 135
 136         {       XFER_PIO_4,     0xc0ca8521,     0xc0ca8521      },
 137         {       XFER_PIO_3,     0xc0ca8532,     0xc0ca8532      },
 138         {       XFER_PIO_2,     0xc0ca8542,     0xc0ca8542      },
 139         {       XFER_PIO_1,     0xc0d08572,     0xc0d08572      },
 140         {       XFER_PIO_0,     0xc0d08585,     0xc0d08585      },
 141         {       0,              0x01208585,     0x01208585      }
 142 };
 143
 144 struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
 145         {       XFER_UDMA_5,    0x1A85F442,     0x16454e31      },
 146         {       XFER_UDMA_4,    0x16454e31,     0x16454e31      },
 147         {       XFER_UDMA_3,    0x166d4e31,     0x166d4e31      },
 148         {       XFER_UDMA_2,    0x16494e31,     0x16494e31      },
 149         {       XFER_UDMA_1,    0x164d4e31,     0x164d4e31      },
 150         {       XFER_UDMA_0,    0x16514e31,     0x16514e31      },
 151
 152         {       XFER_MW_DMA_2,  0x26514e21,     0x26514e21      },
 153         {       XFER_MW_DMA_1,  0x26514e33,     0x26514e33      },
 154         {       XFER_MW_DMA_0,  0x26514e97,     0x26514e97      },
 155
 156         {       XFER_PIO_4,     0x06514e21,     0x06514e21      },
 157         {       XFER_PIO_3,     0x06514e22,     0x06514e22      },
 158         {       XFER_PIO_2,     0x06514e33,     0x06514e33      },
 159         {       XFER_PIO_1,     0x06914e43,     0x06914e43      },
 160         {       XFER_PIO_0,     0x06914e57,     0x06914e57      },
 161         {       0,              0x06514e57,     0x06514e57      }
 162 };
 163
 164 #define HPT366_DEBUG_DRIVE_INFO         0
 165 #define HPT370_ALLOW_ATA100_5           1
 166 #define HPT366_ALLOW_ATA66_4            1
 167 #define HPT366_ALLOW_ATA66_3            1
 168
 169 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
 170 static int hpt366_get_info(char *, char **, off_t, int);
 171 extern int (*hpt366_display_info)(char *, char **, off_t, int); /* ide-proc.c */
 172 extern char *ide_media_verbose(ide_drive_t *);
 173 static struct pci_dev *bmide_dev;
 174 static struct pci_dev *bmide2_dev;
 175
 176 static int hpt366_get_info (char *buffer, char **addr, off_t offset, int count)
 177 {
 178         char *p         = buffer;
 179         u32 bibma       = bmide_dev->resource[4].start;
 180         u32 bibma2      = bmide2_dev->resource[4].start;
 181         char *chipset_names[] = {"HPT366", "HPT366", "HPT368", "HPT370", "HPT370A"};
 182         u8  c0 = 0, c1 = 0;
 183         u32 class_rev;
 184
 185         pci_read_config_dword(bmide_dev, PCI_CLASS_REVISION, &class_rev);
 186         class_rev &= 0xff;
 187
 188         /*
 189          * at that point bibma+0x2 et bibma+0xa are byte registers
 190          * to investigate:
 191          */
 192         c0 = inb_p((unsigned short)bibma + 0x02);
 193         if (bmide2_dev)
 194                 c1 = inb_p((unsigned short)bibma2 + 0x02);
 195
 196         p += sprintf(p, "\n                                %s Chipset.\n", chipset_names[class_rev]);
 197         p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
 198         p += sprintf(p, "                %sabled                         %sabled\n",
 199                         (c0&0x80) ? "dis" : " en",
 200                         (c1&0x80) ? "dis" : " en");
 201         p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
 202         p += sprintf(p, "DMA enabled:    %s              %s             %s               %s\n",
 203                         (c0&0x20) ? "yes" : "no ", (c0&0x40) ? "yes" : "no ",
 204                         (c1&0x20) ? "yes" : "no ", (c1&0x40) ? "yes" : "no " );
 205
 206         p += sprintf(p, "UDMA\n");
 207         p += sprintf(p, "DMA\n");
 208         p += sprintf(p, "PIO\n");
 209
 210         return p-buffer;/* => must be less than 4k! */
 211 }
 212 #endif  /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
 213
 214 byte hpt366_proc = 0;
 215
 216 extern char *ide_xfer_verbose (byte xfer_rate);
 217 byte hpt363_shared_irq = 0;
 218 byte hpt363_shared_pin = 0;
 219
 220 static unsigned int pci_rev_check_hpt3xx (struct pci_dev *dev)
 221 {
 222         unsigned int class_rev;
 223         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 224         class_rev &= 0xff;
 225         return ((int) (class_rev > 0x02) ? 1 : 0);
 226 }
 227
 228 static unsigned int pci_rev2_check_hpt3xx (struct pci_dev *dev)
 229 {
 230         unsigned int class_rev;
 231         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 232         class_rev &= 0xff;
 233         return ((int) (class_rev > 0x01) ? 1 : 0);
 234 }
 235
 236 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
 237 {
 238         struct hd_driveid *id = drive->id;
 239
 240         if (quirk_drives == list) {
 241                 while (*list) {
 242                         if (strstr(id->model, *list++)) {
 243                                 return 1;
 244                         }
 245                 }
 246         } else {
 247                 while (*list) {
 248                         if (!strcmp(*list++,id->model)) {
 249                                 return 1;
 250                         }
 251                 }
 252         }
 253         return 0;
 254 }
 255
 256 static unsigned int pci_bus_clock_list (byte speed, int direction, struct chipset_bus_clock_list_entry * chipset_table)
 257 {
 258         for ( ; chipset_table->xfer_speed ; chipset_table++)
 259                 if (chipset_table->xfer_speed == speed) {
 260                         return (direction) ? chipset_table->chipset_settings_write : chipset_table->chipset_settings_read;
 261                 }
 262         return (direction) ? chipset_table->chipset_settings_write : chipset_table->chipset_settings_read;
 263 }
 264
 265 static void hpt366_tune_chipset (ide_drive_t *drive, byte speed, int direction)
 266 {
 267         byte regtime            = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
 268         byte regfast            = (HWIF(drive)->channel) ? 0x55 : 0x51;
 269                         /*
 270                          * since the channel is always 0 it does not matter.
 271                          */
 272
 273         unsigned int reg1       = 0;
 274         unsigned int reg2       = 0;
 275         byte drive_fast         = 0;
 276
 277         /*
 278          * Disable the "fast interrupt" prediction.
 279          */
 280         pci_read_config_byte(HWIF(drive)->pci_dev, regfast, &drive_fast);
 281         if (drive_fast & 0x02)
 282                 pci_write_config_byte(HWIF(drive)->pci_dev, regfast, drive_fast & ~0x20);
 283
 284         pci_read_config_dword(HWIF(drive)->pci_dev, regtime, &reg1);
 285         /* detect bus speed by looking at control reg timing: */
 286         switch((reg1 >> 8) & 7) {
 287                 case 5:
 288                         reg2 = pci_bus_clock_list(speed, direction, forty_base);
 289                         break;
 290                 case 9:
 291                         reg2 = pci_bus_clock_list(speed, direction, twenty_five_base);
 292                         break;
 293                 default:
 294                 case 7:
 295                         reg2 = pci_bus_clock_list(speed, direction, thirty_three_base);
 296                         break;
 297         }
 298         /*
 299          * Disable on-chip PIO FIFO/buffer (to avoid problems handling I/O errors later)
 300          */
 301         if (speed >= XFER_MW_DMA_0) {
 302                 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
 303         } else {
 304                 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
 305         }
 306         reg2 &= ~0x80000000;
 307
 308         pci_write_config_dword(HWIF(drive)->pci_dev, regtime, reg2);
 309 }
 310
 311 static void hpt370_tune_chipset (ide_drive_t *drive, byte speed, int direction)
 312 {
 313         byte regfast            = (HWIF(drive)->channel) ? 0x55 : 0x51;
 314         byte reg5bh             = (speed != XFER_UDMA_5) ? 0x22 : (direction) ? 0x20 : 0x22;
 315         unsigned int list_conf  = pci_bus_clock_list(speed, direction, thirty_three_base_hpt370);
 316         unsigned int drive_conf = 0;
 317         unsigned int conf_mask  = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 318         byte drive_pci          = 0;
 319         byte drive_fast         = 0;
 320
 321         switch (drive->dn) {
 322                 case 0: drive_pci = 0x40; break;
 323                 case 1: drive_pci = 0x44; break;
 324                 case 2: drive_pci = 0x48; break;
 325                 case 3: drive_pci = 0x4c; break;
 326                 default: return;
 327         }
 328         /*
 329          * Disable the "fast interrupt" prediction.
 330          */
 331         pci_read_config_byte(HWIF(drive)->pci_dev, regfast, &drive_fast);
 332         if (drive_fast & 0x80)
 333                 pci_write_config_byte(HWIF(drive)->pci_dev, regfast, drive_fast & ~0x80);
 334
 335         pci_read_config_dword(HWIF(drive)->pci_dev, drive_pci, &drive_conf);
 336         pci_write_config_byte(HWIF(drive)->pci_dev, 0x5b, reg5bh);
 337
 338         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 339         /*
 340          * Disable on-chip PIO FIFO/buffer (to avoid problems handling I/O errors later)
 341          */
 342         list_conf &= ~0x80000000;
 343
 344         pci_write_config_dword(HWIF(drive)->pci_dev, drive_pci, list_conf);
 345 }
 346
 347 static int hpt3xx_tune_chipset (ide_drive_t *drive, byte speed)
 348 {
 349         if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
 350                 return -1;
 351
 352         if (!drive->init_speed)
 353                 drive->init_speed = speed;
 354
 355         if (pci_rev_check_hpt3xx(HWIF(drive)->pci_dev)) {
 356                 hpt370_tune_chipset(drive, speed, 0);
 357         } else {
 358                 hpt366_tune_chipset(drive, speed, 0);
 359         }
 360         drive->current_speed = speed;
 361         return ((int) ide_config_drive_speed(drive, speed));
 362 }
 363
 364 static void config_chipset_for_pio (ide_drive_t *drive)
 365 {
 366         unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
 367         unsigned short xfer_pio = drive->id->eide_pio_modes;
 368         byte    timing, speed, pio;
 369
 370         pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
 371
 372         if (xfer_pio> 4)
 373                 xfer_pio = 0;
 374
 375         if (drive->id->eide_pio_iordy > 0) {
 376                 for (xfer_pio = 5;
 377                         xfer_pio>0 &&
 378                         drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
 379                         xfer_pio--);
 380         } else {
 381                 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
 382                            (drive->id->eide_pio_modes & 2) ? 0x04 :
 383                            (drive->id->eide_pio_modes & 1) ? 0x03 :
 384                            (drive->id->tPIO & 2) ? 0x02 :
 385                            (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
 386         }
 387
 388         timing = (xfer_pio >= pio) ? xfer_pio : pio;
 389
 390         switch(timing) {
 391                 case 4: speed = XFER_PIO_4;break;
 392                 case 3: speed = XFER_PIO_3;break;
 393                 case 2: speed = XFER_PIO_2;break;
 394                 case 1: speed = XFER_PIO_1;break;
 395                 default:
 396                         speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
 397                         break;
 398         }
 399         (void) hpt3xx_tune_chipset(drive, speed);
 400 }
 401
 402 static void hpt3xx_tune_drive (ide_drive_t *drive, byte pio)
 403 {
 404         byte speed;
 405         switch(pio) {
 406                 case 4:         speed = XFER_PIO_4;break;
 407                 case 3:         speed = XFER_PIO_3;break;
 408                 case 2:         speed = XFER_PIO_2;break;
 409                 case 1:         speed = XFER_PIO_1;break;
 410                 default:        speed = XFER_PIO_0;break;
 411         }
 412         (void) hpt3xx_tune_chipset(drive, speed);
 413 }
 414
 415 #ifdef CONFIG_BLK_DEV_IDEDMA
 416 /*
 417  * This allows the configuration of ide_pci chipset registers
 418  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 419  * after the drive is reported by the OS.  Initally for designed for
 420  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 421  *
 422  * check_in_drive_lists(drive, bad_ata66_4)
 423  * check_in_drive_lists(drive, bad_ata66_3)
 424  * check_in_drive_lists(drive, bad_ata33)
 425  *
 426  */
 427 static int config_chipset_for_dma (ide_drive_t *drive)
 428 {
 429         struct hd_driveid *id   = drive->id;
 430         byte speed              = 0x00;
 431         byte ultra66            = eighty_ninty_three(drive);
 432         int  rval;
 433
 434         if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
 435                 return ((int) ide_dma_off_quietly);
 436
 437         if ((id->dma_ultra & 0x0020) &&
 438             (!check_in_drive_lists(drive, bad_ata100_5)) &&
 439             (HPT370_ALLOW_ATA100_5) &&
 440             (pci_rev_check_hpt3xx(HWIF(drive)->pci_dev)) &&
 441             (ultra66)) {
 442                 speed = XFER_UDMA_5;
 443         } else if ((id->dma_ultra & 0x0010) &&
 444                    (!check_in_drive_lists(drive, bad_ata66_4)) &&
 445                    (HPT366_ALLOW_ATA66_4) &&
 446                    (ultra66)) {
 447                 speed = XFER_UDMA_4;
 448         } else if ((id->dma_ultra & 0x0008) &&
 449                    (!check_in_drive_lists(drive, bad_ata66_3)) &&
 450                    (HPT366_ALLOW_ATA66_3) &&
 451                    (ultra66)) {
 452                 speed = XFER_UDMA_3;
 453         } else if (id->dma_ultra && (!check_in_drive_lists(drive, bad_ata33))) {
 454                 if (id->dma_ultra & 0x0004) {
 455                         speed = XFER_UDMA_2;
 456                 } else if (id->dma_ultra & 0x0002) {
 457                         speed = XFER_UDMA_1;
 458                 } else if (id->dma_ultra & 0x0001) {
 459                         speed = XFER_UDMA_0;
 460                 }
 461         } else if (id->dma_mword & 0x0004) {
 462                 speed = XFER_MW_DMA_2;
 463         } else if (id->dma_mword & 0x0002) {
 464                 speed = XFER_MW_DMA_1;
 465         } else if (id->dma_mword & 0x0001) {
 466                 speed = XFER_MW_DMA_0;
 467         } else {
 468                 return ((int) ide_dma_off_quietly);
 469         }
 470
 471         (void) hpt3xx_tune_chipset(drive, speed);
 472
 473         rval = (int)(   ((id->dma_ultra >> 11) & 7) ? ide_dma_on :
 474                         ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
 475                         ((id->dma_mword >> 8) & 7) ? ide_dma_on :
 476                                                      ide_dma_off_quietly);
 477         return rval;
 478 }
 479
 480 int hpt3xx_quirkproc (ide_drive_t *drive)
 481 {
 482         return ((int) check_in_drive_lists(drive, quirk_drives));
 483 }
 484
 485 void hpt3xx_intrproc (ide_drive_t *drive)
 486 {
 487         if (drive->quirk_list) {
 488                 /* drives in the quirk_list may not like intr setups/cleanups */
 489         } else {
 490                 OUT_BYTE((drive)->ctl|2, HWIF(drive)->io_ports[IDE_CONTROL_OFFSET]);
 491         }
 492 }
 493
 494 void hpt3xx_maskproc (ide_drive_t *drive, int mask)
 495 {
 496         if (drive->quirk_list) {
 497                 if (pci_rev_check_hpt3xx(HWIF(drive)->pci_dev)) {
 498                         byte reg5a = 0;
 499                         pci_read_config_byte(HWIF(drive)->pci_dev, 0x5a, &reg5a);
 500                         if (((reg5a & 0x10) >> 4) != mask)
 501                                 pci_write_config_byte(HWIF(drive)->pci_dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
 502                 } else {
 503                         if (mask) {
 504                                 disable_irq(HWIF(drive)->irq);
 505                         } else {
 506                                 enable_irq(HWIF(drive)->irq);
 507                         }
 508                 }
 509         } else {
 510                 if (IDE_CONTROL_REG)
 511                         OUT_BYTE(mask ? (drive->ctl | 2) : (drive->ctl & ~2), IDE_CONTROL_REG);
 512         }
 513 }
 514
 515 void hpt370_rw_proc (ide_drive_t *drive, ide_dma_action_t func)
 516 {
 517         if ((func != ide_dma_write) || (func != ide_dma_read))
 518                 return;
 519         hpt370_tune_chipset(drive, drive->current_speed, (func == ide_dma_write));
 520 }
 521
 522 static int config_drive_xfer_rate (ide_drive_t *drive)
 523 {
 524         struct hd_driveid *id = drive->id;
 525         ide_dma_action_t dma_func = ide_dma_on;
 526
 527         if (id && (id->capability & 1) && HWIF(drive)->autodma) {
 528                 /* Consult the list of known "bad" drives */
 529                 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
 530                         dma_func = ide_dma_off;
 531                         goto fast_ata_pio;
 532                 }
 533                 dma_func = ide_dma_off_quietly;
 534                 if (id->field_valid & 4) {
 535                         if (id->dma_ultra & 0x002F) {
 536                                 /* Force if Capable UltraDMA */
 537                                 dma_func = config_chipset_for_dma(drive);
 538                                 if ((id->field_valid & 2) &&
 539                                     (dma_func != ide_dma_on))
 540                                         goto try_dma_modes;
 541                         }
 542                 } else if (id->field_valid & 2) {
 543 try_dma_modes:
 544                         if (id->dma_mword & 0x0007) {
 545                                 /* Force if Capable regular DMA modes */
 546                                 dma_func = config_chipset_for_dma(drive);
 547                                 if (dma_func != ide_dma_on)
 548                                         goto no_dma_set;
 549                         }
 550                 } else if (ide_dmaproc(ide_dma_good_drive, drive)) {
 551                         if (id->eide_dma_time > 150) {
 552                                 goto no_dma_set;
 553                         }
 554                         /* Consult the list of known "good" drives */
 555                         dma_func = config_chipset_for_dma(drive);
 556                         if (dma_func != ide_dma_on)
 557                                 goto no_dma_set;
 558                 } else {
 559                         goto fast_ata_pio;
 560                 }
 561         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 562 fast_ata_pio:
 563                 dma_func = ide_dma_off_quietly;
 564 no_dma_set:
 565
 566                 config_chipset_for_pio(drive);
 567         }
 568         return HWIF(drive)->dmaproc(dma_func, drive);
 569 }
 570
 571 /*
 572  * hpt366_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
 573  *
 574  * This is specific to the HPT366 UDMA bios chipset
 575  * by HighPoint|Triones Technologies, Inc.
 576  */
 577 int hpt366_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
 578 {
 579         byte reg50h = 0, reg52h = 0, reg5ah = 0, dma_stat = 0;
 580         unsigned long dma_base = HWIF(drive)->dma_base;
 581
 582         switch (func) {
 583                 case ide_dma_check:
 584                         return config_drive_xfer_rate(drive);
 585                 case ide_dma_test_irq:  /* returns 1 if dma irq issued, 0 otherwise */
 586                         dma_stat = inb(dma_base+2);
 587                         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 588                 case ide_dma_lostirq:
 589                         pci_read_config_byte(HWIF(drive)->pci_dev, 0x50, &reg50h);
 590                         pci_read_config_byte(HWIF(drive)->pci_dev, 0x52, &reg52h);
 591                         pci_read_config_byte(HWIF(drive)->pci_dev, 0x5a, &reg5ah);
 592                         printk("%s: (%s)  reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
 593                                 drive->name,
 594                                 ide_dmafunc_verbose(func),
 595                                 reg50h, reg52h, reg5ah);
 596                         if (reg5ah & 0x10)
 597                                 pci_write_config_byte(HWIF(drive)->pci_dev, 0x5a, reg5ah & ~0x10);
 598                         break;
 599                 case ide_dma_timeout:
 600                 default:
 601                         break;
 602         }
 603         return ide_dmaproc(func, drive);        /* use standard DMA stuff */
 604 }
 605
 606 int hpt370_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
 607 {
 608         switch (func) {
 609                 case ide_dma_check:
 610                         return config_drive_xfer_rate(drive);
 611                 default:
 612                         break;
 613         }
 614         return ide_dmaproc(func, drive);        /* use standard DMA stuff */
 615 }
 616 #endif /* CONFIG_BLK_DEV_IDEDMA */
 617
 618 unsigned int __init pci_init_hpt366 (struct pci_dev *dev, const char *name)
 619 {
 620         byte test = 0;
 621
 622         if (dev->resource[PCI_ROM_RESOURCE].start)
 623                 pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 624
 625         pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &test);
 626
 627 #if 0
 628         if (test != 0x08)
 629                 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x08);
 630 #else
 631         if (test != (L1_CACHE_BYTES / 4))
 632                 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
 633 #endif
 634
 635         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &test);
 636         if (test != 0x78)
 637                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
 638
 639         pci_read_config_byte(dev, PCI_MIN_GNT, &test);
 640         if (test != 0x08)
 641                 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
 642
 643         pci_read_config_byte(dev, PCI_MAX_LAT, &test);
 644         if (test != 0x08)
 645                 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
 646
 647 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
 648         if (!hpt366_proc) {
 649                 hpt366_proc = 1;
 650                 bmide_dev = dev;
 651                 if (pci_rev_check_hpt3xx(dev))
 652                         bmide2_dev = dev;
 653                 hpt366_display_info = &hpt366_get_info;
 654         }
 655         if ((hpt366_proc) && ((dev->devfn - bmide_dev->devfn) == 1)) {
 656                 bmide2_dev = dev;
 657         }
 658 #endif /* DISPLAY_HPT366_TIMINGS && CONFIG_PROC_FS */
 659
 660         return dev->irq;
 661 }
 662
 663 unsigned int __init ata66_hpt366 (ide_hwif_t *hwif)
 664 {
 665         byte ata66 = 0;
 666
 667         pci_read_config_byte(hwif->pci_dev, 0x5a, &ata66);
 668 #ifdef DEBUG
 669         printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
 670                 ata66, (ata66 & 0x02) ? "33" : "66",
 671                 PCI_FUNC(hwif->pci_dev->devfn));
 672 #endif /* DEBUG */
 673         return ((ata66 & 0x02) ? 0 : 1);
 674 }
 675
 676 void __init ide_init_hpt366 (ide_hwif_t *hwif)
 677 {
 678         hwif->tuneproc  = &hpt3xx_tune_drive;
 679         hwif->speedproc = &hpt3xx_tune_chipset;
 680         hwif->quirkproc = &hpt3xx_quirkproc;
 681         hwif->intrproc  = &hpt3xx_intrproc;
 682         hwif->maskproc  = &hpt3xx_maskproc;
 683
 684         if (pci_rev2_check_hpt3xx(hwif->pci_dev)) {
 685                 /* do nothing now but will split device types */
 686         }
 687
 688 #ifdef CONFIG_BLK_DEV_IDEDMA
 689         if (hwif->dma_base) {
 690                 if (pci_rev_check_hpt3xx(hwif->pci_dev)) {
 691                         byte reg5ah = 0;
 692                         pci_read_config_byte(hwif->pci_dev, 0x5a, &reg5ah);
 693                         if (reg5ah & 0x10)      /* interrupt force enable */
 694                                 pci_write_config_byte(hwif->pci_dev, 0x5a, reg5ah & ~0x10);
 695                         hwif->dmaproc = &hpt370_dmaproc;
 696                         hwif->rwproc = &hpt370_rw_proc;
 697                 } else {
 698                         hwif->dmaproc = &hpt366_dmaproc;
 699                 }
 700                 hwif->autodma = 1;
 701         } else {
 702                 hwif->autodma = 0;
 703                 hwif->drives[0].autotune = 1;
 704                 hwif->drives[1].autotune = 1;
 705         }
 706 #else /* !CONFIG_BLK_DEV_IDEDMA */
 707         hwif->drives[0].autotune = 1;
 708         hwif->drives[1].autotune = 1;
 709         hwif->autodma = 0;
 710 #endif /* CONFIG_BLK_DEV_IDEDMA */
 711 }
 712
 713 void __init ide_dmacapable_hpt366 (ide_hwif_t *hwif, unsigned long dmabase)
 714 {
 715         byte masterdma = 0, slavedma = 0;
 716         byte dma_new = 0, dma_old = inb(dmabase+2);
 717         byte primary    = hwif->channel ? 0x4b : 0x43;
 718         byte secondary  = hwif->channel ? 0x4f : 0x47;
 719         unsigned long flags;
 720
 721         __save_flags(flags);    /* local CPU only */
 722         __cli();                /* local CPU only */
 723
 724         dma_new = dma_old;
 725         pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
 726         pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
 727
 728         if (masterdma & 0x30)   dma_new |= 0x20;
 729         if (slavedma & 0x30)    dma_new |= 0x40;
 730         if (dma_new != dma_old) outb(dma_new, dmabase+2);
 731
 732         __restore_flags(flags); /* local CPU only */
 733
 734         ide_setup_dma(hwif, dmabase, 8);
 735 }