1 /* $Id: irq_ipr.c,v 1.6 2000/05/14 08:41:25 gniibe Exp $
3 * linux/arch/sh/kernel/irq_ipr.c
5 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
6 * Copyright (C) 2000 Kazumoto Kojima
8 * Interrupt handling for IPR-based IRQ.
11 * On-chip supporting modules (TMU, RTC, etc.).
12 * On-chip supporting modules for SH7709/SH7709A/SH7729.
13 * Hitachi SolutionEngine external I/O:
14 * MS7709SE01, MS7709ASE01, and MS7750SE01
18 #include <linux/config.h>
19 #include <linux/init.h>
20 #include <linux/irq.h>
22 #include <asm/system.h>
24 #include <asm/machvec.h>
27 unsigned int addr; /* Address of Interrupt Priority Register */
28 int shift; /* Shifts of the 16-bit data */
29 int priority; /* The priority */
31 static struct ipr_data ipr_data[NR_IRQS];
33 static void enable_ipr_irq(unsigned int irq);
34 static void disable_ipr_irq(unsigned int irq);
36 /* shutdown is same as "disable" */
37 #define shutdown_ipr_irq disable_ipr_irq
39 static void mask_and_ack_ipr(unsigned int);
40 static void end_ipr_irq(unsigned int irq);
42 static unsigned int startup_ipr_irq(unsigned int irq)
45 return 0; /* never anything pending */
48 static struct hw_interrupt_type ipr_irq_type = {
58 static void disable_ipr_irq(unsigned int irq)
60 unsigned long val, flags;
61 unsigned int addr = ipr_data[irq].addr;
62 unsigned short mask = 0xffff ^ (0x0f << ipr_data[irq].shift);
64 /* Set the priority in IPR to 0 */
72 static void enable_ipr_irq(unsigned int irq)
74 unsigned long val, flags;
75 unsigned int addr = ipr_data[irq].addr;
76 int priority = ipr_data[irq].priority;
77 unsigned short value = (priority << ipr_data[irq].shift);
79 /* Set priority in IPR back to original value */
87 static void mask_and_ack_ipr(unsigned int irq)
91 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
92 /* This is needed when we use edge triggered setting */
93 /* XXX: Is it really needed? */
94 if (IRQ0_IRQ <= irq && irq <= IRQ5_IRQ) {
95 /* Clear external interrupt request */
96 int a = ctrl_inb(INTC_IRR0);
97 a &= ~(1 << (irq - IRQ0_IRQ));
98 ctrl_outb(a, INTC_IRR0);
103 static void end_ipr_irq(unsigned int irq)
108 void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)
110 disable_irq_nosync(irq);
111 ipr_data[irq].addr = addr;
112 ipr_data[irq].shift = pos*4; /* POSition (0-3) x 4 means shift */
113 ipr_data[irq].priority = priority;
115 irq_desc[irq].handler = &ipr_irq_type;
116 disable_ipr_irq(irq);
119 void __init init_IRQ(void)
121 make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY);
122 make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY);
124 make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
125 make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
126 make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
129 make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
130 make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
131 make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
132 make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
136 make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
137 make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
138 make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
139 make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
142 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
144 * Initialize the Interrupt Controller (INTC)
145 * registers to their power on values
149 * XXX: I think that this is the job of boot loader. -- gniibe
151 * When Takeshi released new boot loader following setting
152 * will be removed shortly.
154 ctrl_outb(0, INTC_IRR0);
155 ctrl_outb(0, INTC_IRR1);
156 ctrl_outb(0, INTC_IRR2);
158 ctrl_outw(0, INTC_ICR0);
159 ctrl_outw(0, INTC_ICR1);/* Really? 0x4000?*/
160 ctrl_outw(0, INTC_ICR2);
161 ctrl_outw(0, INTC_INTER);
162 ctrl_outw(0, INTC_IPRA);
163 ctrl_outw(0, INTC_IPRB);
164 ctrl_outw(0, INTC_IPRC);
165 ctrl_outw(0, INTC_IPRD);
166 ctrl_outw(0, INTC_IPRE);
170 * Enable external irq (INTC IRQ mode).
171 * You should set corresponding bits of PFC to "00"
172 * to enable these interrupts.
174 make_ipr_irq(IRQ0_IRQ, IRQ0_IRP_ADDR, IRQ0_IRP_POS, IRQ0_PRIORITY);
175 make_ipr_irq(IRQ1_IRQ, IRQ1_IRP_ADDR, IRQ1_IRP_POS, IRQ1_PRIORITY);
176 make_ipr_irq(IRQ2_IRQ, IRQ2_IRP_ADDR, IRQ2_IRP_POS, IRQ2_PRIORITY);
177 make_ipr_irq(IRQ3_IRQ, IRQ3_IRP_ADDR, IRQ3_IRP_POS, IRQ3_PRIORITY);
178 make_ipr_irq(IRQ4_IRQ, IRQ4_IRP_ADDR, IRQ4_IRP_POS, IRQ4_PRIORITY);
179 make_ipr_irq(IRQ5_IRQ, IRQ5_IRP_ADDR, IRQ5_IRP_POS, IRQ5_PRIORITY);
180 #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
182 /* Perform the machine specific initialisation */
183 if (sh_mv.mv_init_irq != NULL) {