drivers/ide/pci/pdc202xx_new.c

   1 /*
   2  *  Promise TX2/TX4/TX2000/133 IDE driver
   3  *
   4  *  This program is free software; you can redistribute it and/or
   5  *  modify it under the terms of the GNU General Public License
   6  *  as published by the Free Software Foundation; either version
   7  *  2 of the License, or (at your option) any later version.
   8  *
   9  *  Split from:
  10  *  linux/drivers/ide/pdc202xx.c        Version 0.35    Mar. 30, 2002
  11  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
  12  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  13  *  Author: Frank Tiernan (frankt@promise.com)
  14  *  Released under terms of General Public License
  15  */
  16
  17 #include <linux/config.h>
  18 #include <linux/module.h>
  19 #include <linux/types.h>
  20 #include <linux/kernel.h>
  21 #include <linux/delay.h>
  22 #include <linux/timer.h>
  23 #include <linux/mm.h>
  24 #include <linux/ioport.h>
  25 #include <linux/blkdev.h>
  26 #include <linux/hdreg.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/pci.h>
  29 #include <linux/init.h>
  30 #include <linux/ide.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #include "ide_modes.h"
  36 #include "pdc202xx_new.h"
  37
  38 #define PDC202_DEBUG_CABLE      0
  39
  40 #if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
  41 #include <linux/stat.h>
  42 #include <linux/proc_fs.h>
  43
  44 static u8 pdcnew_proc = 0;
  45 #define PDC202_MAX_DEVS         5
  46 static struct pci_dev *pdc202_devs[PDC202_MAX_DEVS];
  47 static int n_pdc202_devs;
  48
  49 static char * pdcnew_info(char *buf, struct pci_dev *dev)
  50 {
  51         char *p = buf;
  52
  53         p += sprintf(p, "\n                                ");
  54         switch(dev->device) {
  55                 case PCI_DEVICE_ID_PROMISE_20277:
  56                         p += sprintf(p, "SBFastTrak 133 Lite"); break;
  57                 case PCI_DEVICE_ID_PROMISE_20276:
  58                         p += sprintf(p, "MBFastTrak 133 Lite"); break;
  59                 case PCI_DEVICE_ID_PROMISE_20275:
  60                         p += sprintf(p, "MBUltra133"); break;
  61                 case PCI_DEVICE_ID_PROMISE_20271:
  62                         p += sprintf(p, "FastTrak TX2000"); break;
  63                 case PCI_DEVICE_ID_PROMISE_20270:
  64                         p += sprintf(p, "FastTrak LP/TX2/TX4"); break;
  65                 case PCI_DEVICE_ID_PROMISE_20269:
  66                         p += sprintf(p, "Ultra133 TX2"); break;
  67                 case PCI_DEVICE_ID_PROMISE_20268:
  68                         p += sprintf(p, "Ultra100 TX2"); break;
  69                 default:
  70                         p += sprintf(p, "Ultra series"); break;
  71                         break;
  72         }
  73         p += sprintf(p, " Chipset.\n");
  74         return (char *)p;
  75 }
  76
  77 static int pdcnew_get_info (char *buffer, char **addr, off_t offset, int count)
  78 {
  79         char *p = buffer;
  80         int i, len;
  81
  82         for (i = 0; i < n_pdc202_devs; i++) {
  83                 struct pci_dev *dev     = pdc202_devs[i];
  84                 p = pdcnew_info(buffer, dev);
  85         }
  86         /* p - buffer must be less than 4k! */
  87         len = (p - buffer) - offset;
  88         *addr = buffer + offset;
  89
  90         return len > count ? count : len;
  91 }
  92 #endif  /* defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS) */
  93
  94
  95 static u8 pdcnew_ratemask (ide_drive_t *drive)
  96 {
  97         u8 mode;
  98
  99         switch(HWIF(drive)->pci_dev->device) {
 100                 case PCI_DEVICE_ID_PROMISE_20277:
 101                 case PCI_DEVICE_ID_PROMISE_20276:
 102                 case PCI_DEVICE_ID_PROMISE_20275:
 103                 case PCI_DEVICE_ID_PROMISE_20271:
 104                 case PCI_DEVICE_ID_PROMISE_20269:
 105                         mode = 4;
 106                         break;
 107                 case PCI_DEVICE_ID_PROMISE_20270:
 108                 case PCI_DEVICE_ID_PROMISE_20268:
 109                         mode = 3;
 110                         break;
 111                 default:
 112                         return 0;
 113         }
 114         if (!eighty_ninty_three(drive))
 115                 mode = min(mode, (u8)1);
 116         return mode;
 117 }
 118
 119 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
 120 {
 121         struct hd_driveid *id = drive->id;
 122
 123         if (pdc_quirk_drives == list) {
 124                 while (*list) {
 125                         if (strstr(id->model, *list++)) {
 126                                 return 2;
 127                         }
 128                 }
 129         } else {
 130                 while (*list) {
 131                         if (!strcmp(*list++,id->model)) {
 132                                 return 1;
 133                         }
 134                 }
 135         }
 136         return 0;
 137 }
 138
 139 static int pdcnew_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 140 {
 141         ide_hwif_t *hwif        = HWIF(drive);
 142         struct pci_dev *dev     = hwif->pci_dev;
 143         u8 drive_pci            = 0x60 + (drive->dn << 2);
 144         u8 speed        = ide_rate_filter(pdcnew_ratemask(drive), xferspeed);
 145
 146         u32                     drive_conf;
 147         u8                      AP, BP, CP, DP;
 148         u8                      TA = 0, TB = 0, TC = 0;
 149
 150         if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
 151                 return -1;
 152
 153         pci_read_config_dword(dev, drive_pci, &drive_conf);
 154         pci_read_config_byte(dev, (drive_pci), &AP);
 155         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 156         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 157         pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
 158
 159         if (speed < XFER_SW_DMA_0) {
 160                 if ((AP & 0x0F) || (BP & 0x07)) {
 161                         /* clear PIO modes of lower 8421 bits of A Register */
 162                         pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
 163                         pci_read_config_byte(dev, (drive_pci), &AP);
 164
 165                         /* clear PIO modes of lower 421 bits of B Register */
 166                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
 167                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 168
 169                         pci_read_config_byte(dev, (drive_pci), &AP);
 170                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 171                 }
 172         } else {
 173                 if ((BP & 0xF0) && (CP & 0x0F)) {
 174                         /* clear DMA modes of upper 842 bits of B Register */
 175                         /* clear PIO forced mode upper 1 bit of B Register */
 176                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
 177                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 178
 179                         /* clear DMA modes of lower 8421 bits of C Register */
 180                         pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
 181                         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 182                 }
 183         }
 184
 185         pci_read_config_byte(dev, (drive_pci), &AP);
 186         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 187         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 188
 189         switch(speed) {
 190                 case XFER_UDMA_6:       speed = XFER_UDMA_5;
 191                 case XFER_UDMA_5:
 192                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
 193                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
 194                 case XFER_UDMA_3:
 195                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
 196                 case XFER_UDMA_0:
 197                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
 198                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
 199                 case XFER_MW_DMA_0:
 200                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;
 201                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;
 202                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;
 203                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 204                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 205                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 206                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 207                 case XFER_PIO_0:
 208                 default:                TA = 0x09; TB = 0x13; break;
 209         }
 210
 211         if (speed < XFER_SW_DMA_0) {
 212                 pci_write_config_byte(dev, (drive_pci), AP|TA);
 213                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 214         } else {
 215                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 216                 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
 217         }
 218
 219 #if PDC202XX_DECODE_REGISTER_INFO
 220         pci_read_config_byte(dev, (drive_pci), &AP);
 221         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 222         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 223         pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
 224
 225         decode_registers(REG_A, AP);
 226         decode_registers(REG_B, BP);
 227         decode_registers(REG_C, CP);
 228         decode_registers(REG_D, DP);
 229 #endif /* PDC202XX_DECODE_REGISTER_INFO */
 230 #if PDC202XX_DEBUG_DRIVE_INFO
 231         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 232                 drive->name, ide_xfer_verbose(speed),
 233                 drive->dn, drive_conf);
 234                 pci_read_config_dword(dev, drive_pci, &drive_conf);
 235         printk("0x%08x\n", drive_conf);
 236 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
 237
 238         return (ide_config_drive_speed(drive, speed));
 239 }
 240
 241 static int pdcnew_new_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 242 {
 243         ide_hwif_t *hwif        = HWIF(drive);
 244         unsigned long indexreg  = hwif->dma_vendor1;
 245         unsigned long datareg   = hwif->dma_vendor3;
 246         u8 thold                = 0x10;
 247         u8 adj                  = (drive->dn%2) ? 0x08 : 0x00;
 248         u8 speed                = ide_rate_filter(pdcnew_ratemask(drive), xferspeed);
 249
 250         if (speed == XFER_UDMA_2) {
 251                 hwif->OUTB((thold + adj), indexreg);
 252                 hwif->OUTB((hwif->INB(datareg) & 0x7f), datareg);
 253         }
 254
 255         switch (speed) {
 256                 case XFER_UDMA_7:
 257                         speed = XFER_UDMA_6;
 258                 case XFER_UDMA_6:       set_ultra(0x1a, 0x01, 0xcb); break;
 259                 case XFER_UDMA_5:       set_ultra(0x1a, 0x02, 0xcb); break;
 260                 case XFER_UDMA_4:       set_ultra(0x1a, 0x03, 0xcd); break;
 261                 case XFER_UDMA_3:       set_ultra(0x1a, 0x05, 0xcd); break;
 262                 case XFER_UDMA_2:       set_ultra(0x2a, 0x07, 0xcd); break;
 263                 case XFER_UDMA_1:       set_ultra(0x3a, 0x0a, 0xd0); break;
 264                 case XFER_UDMA_0:       set_ultra(0x4a, 0x0f, 0xd5); break;
 265                 case XFER_MW_DMA_2:     set_ata2(0x69, 0x25); break;
 266                 case XFER_MW_DMA_1:     set_ata2(0x6b, 0x27); break;
 267                 case XFER_MW_DMA_0:     set_ata2(0xdf, 0x5f); break;
 268                 case XFER_PIO_4:        set_pio(0x23, 0x09, 0x25); break;
 269                 case XFER_PIO_3:        set_pio(0x27, 0x0d, 0x35); break;
 270                 case XFER_PIO_2:        set_pio(0x23, 0x26, 0x64); break;
 271                 case XFER_PIO_1:        set_pio(0x46, 0x29, 0xa4); break;
 272                 case XFER_PIO_0:        set_pio(0xfb, 0x2b, 0xac); break;
 273                 default:
 274                         ;
 275         }
 276
 277         return (ide_config_drive_speed(drive, speed));
 278 }
 279
 280 /*   0    1    2    3    4    5    6   7   8
 281  * 960, 480, 390, 300, 240, 180, 120, 90, 60
 282  *           180, 150, 120,  90,  60
 283  * DMA_Speed
 284  * 180, 120,  90,  90,  90,  60,  30
 285  *  11,   5,   4,   3,   2,   1,   0
 286  */
 287 static int config_chipset_for_pio (ide_drive_t *drive, u8 pio)
 288 {
 289         u8 speed = 0;
 290
 291         if (pio == 5) pio = 4;
 292         speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
 293
 294         return ((int) pdcnew_tune_chipset(drive, speed));
 295 }
 296
 297 static void pdcnew_tune_drive (ide_drive_t *drive, u8 pio)
 298 {
 299         (void) config_chipset_for_pio(drive, pio);
 300 }
 301
 302 static u8 pdcnew_new_cable_detect (ide_hwif_t *hwif)
 303 {
 304         hwif->OUTB(0x0b, hwif->dma_vendor1);
 305         return ((u8)((hwif->INB(hwif->dma_vendor3) & 0x04)));
 306 }
 307 static int config_chipset_for_dma (ide_drive_t *drive)
 308 {
 309         struct hd_driveid *id   = drive->id;
 310         ide_hwif_t *hwif        = HWIF(drive);
 311         struct pci_dev *dev     = hwif->pci_dev;
 312         u8 speed                = -1;
 313         u8 cable                = 0;
 314
 315         u8 ultra_66             = ((id->dma_ultra & 0x0010) ||
 316                                    (id->dma_ultra & 0x0008)) ? 1 : 0;
 317
 318         switch(dev->device) {
 319                 case PCI_DEVICE_ID_PROMISE_20277:
 320                 case PCI_DEVICE_ID_PROMISE_20276:
 321                 case PCI_DEVICE_ID_PROMISE_20275:
 322                 case PCI_DEVICE_ID_PROMISE_20271:
 323                 case PCI_DEVICE_ID_PROMISE_20269:
 324                 case PCI_DEVICE_ID_PROMISE_20270:
 325                 case PCI_DEVICE_ID_PROMISE_20268:
 326                         cable = pdcnew_new_cable_detect(hwif);
 327 #if PDC202_DEBUG_CABLE
 328                         printk(KERN_DEBUG "%s: %s-pin cable, %s-pin cable, %d\n",
 329                                 hwif->name, hwif->udma_four ? "80" : "40",
 330                                 cable ? "40" : "80", cable);
 331 #endif /* PDC202_DEBUG_CABLE */
 332                         break;
 333                 default:
 334                         /* If it's not one we know we should never
 335                            arrive here.. */
 336                         BUG();
 337         }
 338
 339         /*
 340          * Set the control register to use the 66Mhz system
 341          * clock for UDMA 3/4 mode operation. If one drive on
 342          * a channel is U66 capable but the other isn't we
 343          * fall back to U33 mode. The BIOS INT 13 hooks turn
 344          * the clock on then off for each read/write issued. I don't
 345          * do that here because it would require modifying the
 346          * kernel, separating the fop routines from the kernel or
 347          * somehow hooking the fops calls. It may also be possible to
 348          * leave the 66Mhz clock on and readjust the timing
 349          * parameters.
 350          */
 351
 352         if ((ultra_66) && (cable)) {
 353 #ifdef DEBUG
 354                 printk(KERN_DEBUG "ULTRA 66/100/133: %s channel of Ultra 66/100/133 "
 355                         "requires an 80-pin cable for Ultra66 operation.\n",
 356                         hwif->channel ? "Secondary" : "Primary");
 357                 printk(KERN_DEBUG "         Switching to Ultra33 mode.\n");
 358 #endif /* DEBUG */
 359                 /* Primary   : zero out second bit */
 360                 /* Secondary : zero out fourth bit */
 361                 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
 362                 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
 363         }
 364
 365         if (drive->media != ide_disk)
 366                 return 0;
 367         if (id->capability & 4) {       /* IORDY_EN & PREFETCH_EN */
 368                 hwif->OUTB((0x13 + ((drive->dn%2) ? 0x08 : 0x00)), hwif->dma_vendor1);
 369                 hwif->OUTB((hwif->INB(hwif->dma_vendor3)|0x03), hwif->dma_vendor3);
 370         }
 371
 372         speed = ide_dma_speed(drive, pdcnew_ratemask(drive));
 373
 374         if (!(speed)) {
 375                 hwif->tuneproc(drive, 5);
 376                 return 0;
 377         }
 378
 379         (void) hwif->speedproc(drive, speed);
 380         return ide_dma_enable(drive);
 381 }
 382
 383 static int pdcnew_config_drive_xfer_rate (ide_drive_t *drive)
 384 {
 385         ide_hwif_t *hwif        = HWIF(drive);
 386         struct hd_driveid *id   = drive->id;
 387
 388         drive->init_speed = 0;
 389
 390         if (id && (id->capability & 1) && drive->autodma) {
 391                 /* Consult the list of known "bad" drives */
 392                 if (hwif->ide_dma_bad_drive(drive))
 393                         goto fast_ata_pio;
 394                 if (id->field_valid & 4) {
 395                         if (id->dma_ultra & hwif->ultra_mask) {
 396                                 /* Force if Capable UltraDMA */
 397                                 int dma = config_chipset_for_dma(drive);
 398                                 if ((id->field_valid & 2) && !dma)
 399                                         goto try_dma_modes;
 400                         }
 401                 } else if (id->field_valid & 2) {
 402 try_dma_modes:
 403                         if ((id->dma_mword & hwif->mwdma_mask) ||
 404                             (id->dma_1word & hwif->swdma_mask)) {
 405                                 /* Force if Capable regular DMA modes */
 406                                 if (!config_chipset_for_dma(drive))
 407                                         goto no_dma_set;
 408                         }
 409                 } else if (hwif->ide_dma_good_drive(drive) &&
 410                             (id->eide_dma_time < 150)) {
 411                                 goto no_dma_set;
 412                         /* Consult the list of known "good" drives */
 413                         if (!config_chipset_for_dma(drive))
 414                                 goto no_dma_set;
 415                 } else {
 416                         goto fast_ata_pio;
 417                 }
 418         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 419 fast_ata_pio:
 420 no_dma_set:
 421                 hwif->tuneproc(drive, 5);
 422                 return hwif->ide_dma_off_quietly(drive);
 423         }
 424         return hwif->ide_dma_on(drive);
 425 }
 426
 427 static int pdcnew_quirkproc (ide_drive_t *drive)
 428 {
 429         return ((int) check_in_drive_lists(drive, pdc_quirk_drives));
 430 }
 431
 432 static int pdcnew_ide_dma_lostirq(ide_drive_t *drive)
 433 {
 434         if (HWIF(drive)->resetproc != NULL)
 435                 HWIF(drive)->resetproc(drive);
 436         return __ide_dma_lostirq(drive);
 437 }
 438
 439 static int pdcnew_ide_dma_timeout(ide_drive_t *drive)
 440 {
 441         if (HWIF(drive)->resetproc != NULL)
 442                 HWIF(drive)->resetproc(drive);
 443         return __ide_dma_timeout(drive);
 444 }
 445
 446 static void pdcnew_new_reset (ide_drive_t *drive)
 447 {
 448         /*
 449          * Deleted this because it is redundant from the caller.
 450          */
 451         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 452                 HWIF(drive)->channel ? "Secondary" : "Primary");
 453 }
 454
 455 static void pdcnew_reset_host (ide_hwif_t *hwif)
 456 {
 457 //      unsigned long high_16   = hwif->dma_base - (8*(hwif->channel));
 458         unsigned long high_16   = hwif->dma_master;
 459         u8 udma_speed_flag      = hwif->INB(high_16|0x001f);
 460
 461         hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f));
 462         mdelay(100);
 463         hwif->OUTB((udma_speed_flag & ~0x10), (high_16|0x001f));
 464         mdelay(2000);   /* 2 seconds ?! */
 465
 466         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 467                 hwif->channel ? "Secondary" : "Primary");
 468 }
 469
 470 void pdcnew_reset (ide_drive_t *drive)
 471 {
 472         ide_hwif_t *hwif        = HWIF(drive);
 473         ide_hwif_t *mate        = hwif->mate;
 474
 475         pdcnew_reset_host(hwif);
 476         pdcnew_reset_host(mate);
 477 #if 0
 478         /*
 479          * FIXME: Have to kick all the drives again :-/
 480          * What a pain in the ACE!
 481          */
 482         if (hwif->present) {
 483                 u16 hunit = 0;
 484                 hwif->initializing = 1;
 485                 for (hunit = 0; hunit < MAX_DRIVES; ++hunit) {
 486                         ide_drive_t *hdrive = &hwif->drives[hunit];
 487                         if (hdrive->present) {
 488                                 if (hwif->ide_dma_check)
 489                                         hwif->ide_dma_check(hdrive);
 490                                 else
 491                                         hwif->tuneproc(hdrive, 5);
 492                         }
 493                 }
 494                 hwif->initializing = 0;
 495         }
 496         if (mate->present) {
 497                 u16 munit = 0;
 498                 mate->initializing = 1;
 499                 for (munit = 0; munit < MAX_DRIVES; ++munit) {
 500                         ide_drive_t *mdrive = &mate->drives[munit];
 501                         if (mdrive->present) {
 502                                 if (mate->ide_dma_check)
 503                                         mate->ide_dma_check(mdrive);
 504                                 else
 505                                         mate->tuneproc(mdrive, 5);
 506                         }
 507                 }
 508                 mate->initializing = 0;
 509         }
 510 #else
 511         hwif->tuneproc(drive, 5);
 512 #endif
 513 }
 514
 515 static unsigned int __init init_chipset_pdcnew (struct pci_dev *dev, const char *name)
 516 {
 517         if (dev->resource[PCI_ROM_RESOURCE].start) {
 518                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
 519                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 520                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n",
 521                         name, dev->resource[PCI_ROM_RESOURCE].start);
 522         }
 523
 524 #if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
 525         pdc202_devs[n_pdc202_devs++] = dev;
 526
 527         if (!pdcnew_proc) {
 528                 pdcnew_proc = 1;
 529                 ide_pci_register_host_proc(&pdcnew_procs[0]);
 530         }
 531 #endif /* DISPLAY_PDC202XX_TIMINGS && CONFIG_PROC_FS */
 532
 533         return dev->irq;
 534 }
 535
 536 static void __init init_hwif_pdc202new (ide_hwif_t *hwif)
 537 {
 538         hwif->autodma = 0;
 539
 540         hwif->tuneproc  = &pdcnew_tune_drive;
 541         hwif->quirkproc = &pdcnew_quirkproc;
 542         hwif->speedproc = &pdcnew_new_tune_chipset;
 543         hwif->resetproc = &pdcnew_new_reset;
 544
 545         if (!hwif->dma_base) {
 546                 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 547                 return;
 548         }
 549
 550         hwif->ultra_mask = 0x7f;
 551         hwif->mwdma_mask = 0x07;
 552
 553         hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;
 554         hwif->ide_dma_lostirq = &pdcnew_ide_dma_lostirq;
 555         hwif->ide_dma_timeout = &pdcnew_ide_dma_timeout;
 556         if (!(hwif->udma_four))
 557                 hwif->udma_four = (pdcnew_new_cable_detect(hwif)) ? 0 : 1;
 558         if (!noautodma)
 559                 hwif->autodma = 1;
 560         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 561 #if PDC202_DEBUG_CABLE
 562         printk(KERN_DEBUG "%s: %s-pin cable\n",
 563                 hwif->name, hwif->udma_four ? "80" : "40");
 564 #endif /* PDC202_DEBUG_CABLE */
 565 }
 566
 567 static void __init init_dma_pdc202new (ide_hwif_t *hwif, unsigned long dmabase)
 568 {
 569         ide_setup_dma(hwif, dmabase, 8);
 570 }
 571
 572 extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
 573 extern void ide_setup_pci_devices(struct pci_dev *, struct pci_dev *, ide_pci_device_t *);
 574
 575 static void __init init_setup_pdcnew (struct pci_dev *dev, ide_pci_device_t *d)
 576 {
 577         ide_setup_pci_device(dev, d);
 578 }
 579
 580 static void __init init_setup_pdc20270 (struct pci_dev *dev, ide_pci_device_t *d)
 581 {
 582         struct pci_dev *findev = NULL;
 583
 584         if ((dev->bus->self &&
 585              dev->bus->self->vendor == PCI_VENDOR_ID_DEC) &&
 586             (dev->bus->self->device == PCI_DEVICE_ID_DEC_21150)) {
 587                 if (PCI_SLOT(dev->devfn) & 2) {
 588                         return;
 589                 }
 590                 d->extra = 0;
 591                 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
 592                         if ((findev->vendor == dev->vendor) &&
 593                             (findev->device == dev->device) &&
 594                             (PCI_SLOT(findev->devfn) & 2)) {
 595                                 if (findev->irq != dev->irq) {
 596                                         findev->irq = dev->irq;
 597                                 }
 598                                 ide_setup_pci_devices(dev, findev, d);
 599                                 return;
 600                         }
 601                 }
 602         }
 603         ide_setup_pci_device(dev, d);
 604 }
 605
 606 static void __init init_setup_pdc20276 (struct pci_dev *dev, ide_pci_device_t *d)
 607 {
 608         if ((dev->bus->self) &&
 609             (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
 610             ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
 611              (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
 612                 printk(KERN_INFO "ide: Skipping Promise PDC20276 "
 613                         "attached to I2O RAID controller.\n");
 614                 return;
 615         }
 616         ide_setup_pci_device(dev, d);
 617 }
 618
 619 /**
 620  *      pdc202new_init_one      -       called when a pdc202xx is found
 621  *      @dev: the pdc202new device
 622  *      @id: the matching pci id
 623  *
 624  *      Called when the PCI registration layer (or the IDE initialization)
 625  *      finds a device matching our IDE device tables.
 626  */
 627
 628 static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 629 {
 630         ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
 631
 632         if (dev->device != d->device)
 633                 BUG();
 634         d->init_setup(dev, d);
 635         MOD_INC_USE_COUNT;
 636         return 0;
 637 }
 638
 639 static struct pci_device_id pdc202new_pci_tbl[] __devinitdata = {
 640         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 641         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 642         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 643         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 644         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 645         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
 646         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
 647         { 0, },
 648 };
 649
 650 static struct pci_driver driver = {
 651         .name           = "Promise IDE",
 652         .id_table       = pdc202new_pci_tbl,
 653         .probe          = pdc202new_init_one,
 654 };
 655
 656 static int pdc202new_ide_init(void)
 657 {
 658         return ide_pci_register_driver(&driver);
 659 }
 660
 661 static void pdc202new_ide_exit(void)
 662 {
 663         ide_pci_unregister_driver(&driver);
 664 }
 665
 666 module_init(pdc202new_ide_init);
 667 module_exit(pdc202new_ide_exit);
 668
 669 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 670 MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
 671 MODULE_LICENSE("GPL");