2 * linux/drivers/ide/arm/icside.c
4 * Copyright (c) 1996-2002 Russell King.
7 * 08-Jun-1996 RMK Created
8 * 12-Sep-1997 RMK Added interrupt enable/disable
9 * 17-Apr-1999 RMK Added support for V6 EASI
10 * 22-May-1999 RMK Added support for V6 DMA
13 #include <linux/config.h>
14 #include <linux/string.h>
15 #include <linux/module.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/blkdev.h>
19 #include <linux/errno.h>
20 #include <linux/hdreg.h>
21 #include <linux/ide.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/device.h>
24 #include <linux/init.h>
27 #include <asm/ecard.h>
30 #define ICS_IDENT_OFFSET 0x2280
32 #define ICS_ARCIN_V5_INTRSTAT 0x000
33 #define ICS_ARCIN_V5_INTROFFSET 0x001
34 #define ICS_ARCIN_V5_IDEOFFSET 0xa00
35 #define ICS_ARCIN_V5_IDEALTOFFSET 0xae0
36 #define ICS_ARCIN_V5_IDESTEPPING 4
38 #define ICS_ARCIN_V6_IDEOFFSET_1 0x800
39 #define ICS_ARCIN_V6_INTROFFSET_1 0x880
40 #define ICS_ARCIN_V6_INTRSTAT_1 0x8a4
41 #define ICS_ARCIN_V6_IDEALTOFFSET_1 0x8e0
42 #define ICS_ARCIN_V6_IDEOFFSET_2 0xc00
43 #define ICS_ARCIN_V6_INTROFFSET_2 0xc80
44 #define ICS_ARCIN_V6_INTRSTAT_2 0xca4
45 #define ICS_ARCIN_V6_IDEALTOFFSET_2 0xce0
46 #define ICS_ARCIN_V6_IDESTEPPING 4
49 unsigned int dataoffset;
50 unsigned int ctrloffset;
51 unsigned int stepping;
54 static struct cardinfo icside_cardinfo_v5 = {
55 ICS_ARCIN_V5_IDEOFFSET,
56 ICS_ARCIN_V5_IDEALTOFFSET,
57 ICS_ARCIN_V5_IDESTEPPING
60 static struct cardinfo icside_cardinfo_v6_1 = {
61 ICS_ARCIN_V6_IDEOFFSET_1,
62 ICS_ARCIN_V6_IDEALTOFFSET_1,
63 ICS_ARCIN_V6_IDESTEPPING
66 static struct cardinfo icside_cardinfo_v6_2 = {
67 ICS_ARCIN_V6_IDEOFFSET_2,
68 ICS_ARCIN_V6_IDEALTOFFSET_2,
69 ICS_ARCIN_V6_IDESTEPPING
75 unsigned long irq_port;
76 unsigned long slot_port;
78 /* parent device... until the IDE core gets one of its own */
83 #define ICS_TYPE_A3IN 0
84 #define ICS_TYPE_A3USER 1
86 #define ICS_TYPE_V5 15
87 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
89 /* ---------------- Version 5 PCB Support Functions --------------------- */
90 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
91 * Purpose : enable interrupts from card
93 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
95 struct icside_state *state = ec->irq_data;
96 unsigned int base = state->irq_port;
98 outb(0, base + ICS_ARCIN_V5_INTROFFSET);
101 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
102 * Purpose : disable interrupts from card
104 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
106 struct icside_state *state = ec->irq_data;
107 unsigned int base = state->irq_port;
109 inb(base + ICS_ARCIN_V5_INTROFFSET);
112 static const expansioncard_ops_t icside_ops_arcin_v5 = {
113 .irqenable = icside_irqenable_arcin_v5,
114 .irqdisable = icside_irqdisable_arcin_v5,
118 /* ---------------- Version 6 PCB Support Functions --------------------- */
119 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
120 * Purpose : enable interrupts from card
122 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
124 struct icside_state *state = ec->irq_data;
125 unsigned int base = state->irq_port;
129 switch (state->channel) {
131 outb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
132 inb(base + ICS_ARCIN_V6_INTROFFSET_2);
135 outb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
136 inb(base + ICS_ARCIN_V6_INTROFFSET_1);
141 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
142 * Purpose : disable interrupts from card
144 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
146 struct icside_state *state = ec->irq_data;
150 inb (state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
151 inb (state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
154 /* Prototype: icside_irqprobe(struct expansion_card *ec)
155 * Purpose : detect an active interrupt from card
157 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
159 struct icside_state *state = ec->irq_data;
161 return inb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
162 inb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
165 static const expansioncard_ops_t icside_ops_arcin_v6 = {
166 .irqenable = icside_irqenable_arcin_v6,
167 .irqdisable = icside_irqdisable_arcin_v6,
168 .irqpending = icside_irqpending_arcin_v6,
172 * Handle routing of interrupts. This is called before
173 * we write the command to the drive.
175 static void icside_maskproc(ide_drive_t *drive, int mask)
177 ide_hwif_t *hwif = HWIF(drive);
178 struct icside_state *state = hwif->hwif_data;
181 local_irq_save(flags);
183 state->channel = hwif->channel;
185 if (state->enabled && !mask) {
186 switch (hwif->channel) {
188 outb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
189 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
192 outb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
193 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
197 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
198 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
201 local_irq_restore(flags);
204 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
208 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
209 * There is only one DMA controller per card, which means that only
210 * one drive can be accessed at one time. NOTE! We do not enforce that
211 * here, but we rely on the main IDE driver spotting that both
212 * interfaces use the same IRQ, which should guarantee this.
214 #define NR_ENTRIES 256
215 #define TABLE_SIZE (NR_ENTRIES * 8)
217 static void icside_build_sglist(ide_drive_t *drive, struct request *rq)
219 ide_hwif_t *hwif = drive->hwif;
220 struct icside_state *state = hwif->hwif_data;
221 struct scatterlist *sg = hwif->sg_table;
224 BUG_ON(hwif->sg_dma_active);
226 if (rq->flags & REQ_DRIVE_TASKFILE) {
227 ide_task_t *args = rq->special;
229 if (args->command_type == IDE_DRIVE_TASK_RAW_WRITE)
230 hwif->sg_dma_direction = DMA_TO_DEVICE;
232 hwif->sg_dma_direction = DMA_FROM_DEVICE;
234 memset(sg, 0, sizeof(*sg));
235 sg->page = virt_to_page(rq->buffer);
236 sg->offset = offset_in_page(rq->buffer);
237 sg->length = rq->nr_sectors * SECTOR_SIZE;
240 nents = blk_rq_map_sg(&drive->queue, rq, sg);
242 if (rq_data_dir(rq) == READ)
243 hwif->sg_dma_direction = DMA_FROM_DEVICE;
245 hwif->sg_dma_direction = DMA_TO_DEVICE;
248 nents = dma_map_sg(state->dev, sg, nents, hwif->sg_dma_direction);
250 hwif->sg_nents = nents;
255 * Configure the IOMD to give the appropriate timings for the transfer
256 * mode being requested. We take the advice of the ATA standards, and
257 * calculate the cycle time based on the transfer mode, and the EIDE
258 * MW DMA specs that the drive provides in the IDENTIFY command.
260 * We have the following IOMD DMA modes to choose from:
262 * Type Active Recovery Cycle
263 * A 250 (250) 312 (550) 562 (800)
265 * C 125 (125) 125 (375) 250 (500)
268 * (figures in brackets are actual measured timings)
270 * However, we also need to take care of the read/write active and
274 * Mode Active -- Recovery -- Cycle IOMD type
275 * MW0 215 50 215 480 A
279 static int icside_set_speed(ide_drive_t *drive, u8 xfer_mode)
281 int on = 0, cycle_time = 0, use_dma_info = 0;
284 * Limit the transfer speed to MW_DMA_2.
286 if (xfer_mode > XFER_MW_DMA_2)
287 xfer_mode = XFER_MW_DMA_2;
312 * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
313 * take care to note the values in the ID...
315 if (use_dma_info && drive->id->eide_dma_time > cycle_time)
316 cycle_time = drive->id->eide_dma_time;
318 drive->drive_data = cycle_time;
320 if (cycle_time && ide_config_drive_speed(drive, xfer_mode) == 0)
323 drive->drive_data = 480;
325 printk("%s: %s selected (peak %dMB/s)\n", drive->name,
326 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
328 drive->current_speed = xfer_mode;
334 * The following is a sick duplication from ide-dma.c ;(
336 * This should be defined in one place only.
338 struct drive_list_entry {
339 const char * id_model;
340 const char * id_firmware;
343 static const struct drive_list_entry drive_whitelist [] = {
344 { "Micropolis 2112A", "ALL" },
345 { "CONNER CTMA 4000", "ALL" },
346 { "CONNER CTT8000-A", "ALL" },
347 { "ST34342A", "ALL" },
351 static struct drive_list_entry drive_blacklist [] = {
352 { "WDC AC11000H", "ALL" },
353 { "WDC AC22100H", "ALL" },
354 { "WDC AC32500H", "ALL" },
355 { "WDC AC33100H", "ALL" },
356 { "WDC AC31600H", "ALL" },
357 { "WDC AC32100H", "24.09P07" },
358 { "WDC AC23200L", "21.10N21" },
359 { "Compaq CRD-8241B", "ALL" },
360 { "CRD-8400B", "ALL" },
361 { "CRD-8480B", "ALL" },
362 { "CRD-8480C", "ALL" },
363 { "CRD-8482B", "ALL" },
365 { "SanDisk SDP3B", "ALL" },
366 { "SanDisk SDP3B-64", "ALL" },
367 { "SANYO CD-ROM CRD", "ALL" },
368 { "HITACHI CDR-8", "ALL" },
369 { "HITACHI CDR-8335", "ALL" },
370 { "HITACHI CDR-8435", "ALL" },
371 { "Toshiba CD-ROM XM-6202B", "ALL" },
372 { "CD-532E-A", "ALL" },
373 { "E-IDE CD-ROM CR-840", "ALL" },
374 { "CD-ROM Drive/F5A", "ALL" },
375 { "RICOH CD-R/RW MP7083A", "ALL" },
376 { "WPI CDD-820", "ALL" },
377 { "SAMSUNG CD-ROM SC-148C", "ALL" },
378 { "SAMSUNG CD-ROM SC-148F", "ALL" },
379 { "SAMSUNG CD-ROM SC", "ALL" },
380 { "SanDisk SDP3B-64", "ALL" },
381 { "SAMSUNG CD-ROM SN-124", "ALL" },
382 { "PLEXTOR CD-R PX-W8432T", "ALL" },
383 { "ATAPI CD-ROM DRIVE 40X MAXIMUM", "ALL" },
384 { "_NEC DV5800A", "ALL" },
389 in_drive_list(struct hd_driveid *id, const struct drive_list_entry *drive_table)
391 for ( ; drive_table->id_model ; drive_table++)
392 if ((!strcmp(drive_table->id_model, id->model)) &&
393 ((!strstr(drive_table->id_firmware, id->fw_rev)) ||
394 (!strcmp(drive_table->id_firmware, "ALL"))))
399 static int icside_dma_host_off(ide_drive_t *drive)
404 static int icside_dma_off_quietly(ide_drive_t *drive)
406 drive->using_dma = 0;
407 return icside_dma_host_off(drive);
410 static int icside_dma_off(ide_drive_t *drive)
412 printk("%s: DMA disabled\n", drive->name);
413 return icside_dma_off_quietly(drive);
416 static int icside_dma_host_on(ide_drive_t *drive)
421 static int icside_dma_on(ide_drive_t *drive)
423 drive->using_dma = 1;
424 return icside_dma_host_on(drive);
427 static int icside_dma_check(ide_drive_t *drive)
429 struct hd_driveid *id = drive->id;
430 ide_hwif_t *hwif = HWIF(drive);
431 int xfer_mode = XFER_PIO_2;
434 if (!(id->capability & 1) || !hwif->autodma)
438 * Consult the list of known "bad" drives
440 if (in_drive_list(id, drive_blacklist)) {
441 printk("%s: Disabling DMA for %s (blacklisted)\n",
442 drive->name, id->model);
447 * Enable DMA on any drive that has multiword DMA
449 if (id->field_valid & 2) {
450 xfer_mode = ide_dma_speed(drive, 0);
455 * Consult the list of known "good" drives
457 if (in_drive_list(id, drive_whitelist)) {
458 if (id->eide_dma_time > 150)
460 xfer_mode = XFER_MW_DMA_1;
464 on = icside_set_speed(drive, xfer_mode);
467 return icside_dma_on(drive);
469 return icside_dma_off_quietly(drive);
472 static int icside_dma_end(ide_drive_t *drive)
474 ide_hwif_t *hwif = HWIF(drive);
475 struct icside_state *state = hwif->hwif_data;
477 drive->waiting_for_dma = 0;
479 disable_dma(hwif->hw.dma);
481 /* Teardown mappings after DMA has completed. */
482 dma_unmap_sg(state->dev, hwif->sg_table, hwif->sg_nents,
483 hwif->sg_dma_direction);
485 hwif->sg_dma_active = 0;
487 return get_dma_residue(hwif->hw.dma) != 0;
490 static int icside_dma_begin(ide_drive_t *drive)
492 ide_hwif_t *hwif = HWIF(drive);
494 /* We can not enable DMA on both channels simultaneously. */
495 BUG_ON(dma_channel_active(hwif->hw.dma));
496 enable_dma(hwif->hw.dma);
500 static int icside_dma_count(ide_drive_t *drive)
502 return icside_dma_begin(drive);
506 * dma_intr() is the handler for disk read/write DMA interrupts
508 static ide_startstop_t icside_dmaintr(ide_drive_t *drive)
513 dma_stat = icside_dma_end(drive);
514 stat = HWIF(drive)->INB(IDE_STATUS_REG);
515 if (OK_STAT(stat, DRIVE_READY, drive->bad_wstat | DRQ_STAT)) {
517 struct request *rq = HWGROUP(drive)->rq;
520 for (i = rq->nr_sectors; i > 0; ) {
521 i -= rq->current_nr_sectors;
522 DRIVER(drive)->end_request(drive, 1, rq->nr_sectors);
527 printk(KERN_ERR "%s: bad DMA status (dma_stat=%x)\n",
528 drive->name, dma_stat);
531 return DRIVER(drive)->error(drive, __FUNCTION__, stat);
535 icside_dma_common(ide_drive_t *drive, struct request *rq,
536 unsigned int dma_mode)
538 ide_hwif_t *hwif = HWIF(drive);
541 * We can not enable DMA on both channels.
543 BUG_ON(hwif->sg_dma_active);
544 BUG_ON(dma_channel_active(hwif->hw.dma));
546 icside_build_sglist(drive, rq);
549 * Ensure that we have the right interrupt routed.
551 icside_maskproc(drive, 0);
554 * Route the DMA signals to the correct interface.
556 outb(hwif->select_data, hwif->config_data);
559 * Select the correct timing for this drive.
561 set_dma_speed(hwif->hw.dma, drive->drive_data);
564 * Tell the DMA engine about the SG table and
567 set_dma_sg(hwif->hw.dma, hwif->sg_table, hwif->sg_nents);
568 set_dma_mode(hwif->hw.dma, dma_mode);
573 static int icside_dma_read(ide_drive_t *drive)
575 struct request *rq = HWGROUP(drive)->rq;
576 task_ioreg_t cmd = WIN_NOP;
578 if (icside_dma_common(drive, rq, DMA_MODE_READ))
581 drive->waiting_for_dma = 1;
583 if (drive->media != ide_disk)
586 BUG_ON(HWGROUP(drive)->handler != NULL);
588 ide_set_handler(drive, icside_dmaintr, 2*WAIT_CMD, NULL);
591 * FIX ME to use only ACB ide_task_t args Struct
595 ide_task_t *args = rq->special;
596 command = args->tfRegister[IDE_COMMAND_OFFSET];
599 if (rq->flags & REQ_DRIVE_TASKFILE) {
600 ide_task_t *args = rq->special;
601 cmd = args->tfRegister[IDE_COMMAND_OFFSET];
602 } else if (drive->addressing == 1) {
603 cmd = WIN_READDMA_EXT;
608 /* issue cmd to drive */
609 HWIF(drive)->OUTB(cmd, IDE_COMMAND_REG);
611 return icside_dma_begin(drive);
614 int icside_dma_write(ide_drive_t *drive)
616 struct request *rq = HWGROUP(drive)->rq;
617 task_ioreg_t cmd = WIN_NOP;
619 if (icside_dma_common(drive, rq, DMA_MODE_WRITE))
622 drive->waiting_for_dma = 1;
624 if (drive->media != ide_disk)
627 BUG_ON(HWGROUP(drive)->handler != NULL);
629 ide_set_handler(drive, icside_dmaintr, 2*WAIT_CMD, NULL);
632 * FIX ME to use only ACB ide_task_t args Struct
636 ide_task_t *args = rq->special;
637 command = args->tfRegister[IDE_COMMAND_OFFSET];
640 if (rq->flags & REQ_DRIVE_TASKFILE) {
641 ide_task_t *args = rq->special;
642 cmd = args->tfRegister[IDE_COMMAND_OFFSET];
643 } else if (drive->addressing == 1) {
644 cmd = WIN_WRITEDMA_EXT;
649 /* issue cmd to drive */
650 HWIF(drive)->OUTB(cmd, IDE_COMMAND_REG);
652 return icside_dma_begin(drive);
655 static int icside_dma_test_irq(ide_drive_t *drive)
657 ide_hwif_t *hwif = HWIF(drive);
658 struct icside_state *state = hwif->hwif_data;
660 return inb(state->irq_port +
662 ICS_ARCIN_V6_INTRSTAT_2 :
663 ICS_ARCIN_V6_INTRSTAT_1)) & 1;
666 static int icside_dma_verbose(ide_drive_t *drive)
668 printk(", %s (peak %dMB/s)",
669 ide_xfer_verbose(drive->current_speed),
670 2000 / drive->drive_data);
674 static int icside_dma_timeout(ide_drive_t *drive)
676 printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
678 if (icside_dma_test_irq(drive))
681 ide_dump_status(drive, "DMA timeout",
682 HWIF(drive)->INB(IDE_STATUS_REG));
684 return icside_dma_end(drive);
687 static int icside_dma_lostirq(ide_drive_t *drive)
689 printk(KERN_ERR "%s: IRQ lost\n", drive->name);
693 static int icside_dma_init(ide_hwif_t *hwif)
697 #ifdef CONFIG_IDEDMA_ICS_AUTO
701 printk(" %s: SG-DMA", hwif->name);
703 hwif->sg_table = kmalloc(sizeof(struct scatterlist) * NR_ENTRIES,
709 hwif->mwdma_mask = 7; /* MW0..2 */
710 hwif->swdma_mask = 7; /* SW0..2 */
712 hwif->dmatable_cpu = NULL;
713 hwif->dmatable_dma = 0;
714 hwif->speedproc = icside_set_speed;
715 hwif->autodma = autodma;
717 hwif->ide_dma_check = icside_dma_check;
718 hwif->ide_dma_host_off = icside_dma_host_off;
719 hwif->ide_dma_off_quietly = icside_dma_off_quietly;
720 hwif->ide_dma_off = icside_dma_off;
721 hwif->ide_dma_host_on = icside_dma_host_on;
722 hwif->ide_dma_on = icside_dma_on;
723 hwif->ide_dma_read = icside_dma_read;
724 hwif->ide_dma_write = icside_dma_write;
725 hwif->ide_dma_count = icside_dma_count;
726 hwif->ide_dma_begin = icside_dma_begin;
727 hwif->ide_dma_end = icside_dma_end;
728 hwif->ide_dma_test_irq = icside_dma_test_irq;
729 hwif->ide_dma_verbose = icside_dma_verbose;
730 hwif->ide_dma_timeout = icside_dma_timeout;
731 hwif->ide_dma_lostirq = icside_dma_lostirq;
733 hwif->drives[0].autodma = hwif->autodma;
734 hwif->drives[1].autodma = hwif->autodma;
736 printk(" capable%s\n", hwif->autodma ? ", auto-enable" : "");
741 printk(" disabled, unable to allocate DMA table\n");
745 static void icside_dma_exit(ide_hwif_t *hwif)
747 if (hwif->sg_table) {
748 kfree(hwif->sg_table);
749 hwif->sg_table = NULL;
753 #define icside_dma_init(hwif) (0)
754 #define icside_dma_exit(hwif) do { } while (0)
757 static ide_hwif_t *icside_find_hwif(unsigned long dataport)
762 for (index = 0; index < MAX_HWIFS; ++index) {
763 hwif = &ide_hwifs[index];
764 if (hwif->io_ports[IDE_DATA_OFFSET] == dataport)
768 for (index = 0; index < MAX_HWIFS; ++index) {
769 hwif = &ide_hwifs[index];
770 if (!hwif->io_ports[IDE_DATA_OFFSET])
780 icside_setup(unsigned long base, struct cardinfo *info, struct expansion_card *ec)
782 unsigned long port = base + info->dataoffset;
785 hwif = icside_find_hwif(base);
789 memset(&hwif->hw, 0, sizeof(hw_regs_t));
791 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
792 hwif->hw.io_ports[i] = port;
793 hwif->io_ports[i] = port;
794 port += 1 << info->stepping;
796 hwif->hw.io_ports[IDE_CONTROL_OFFSET] = base + info->ctrloffset;
797 hwif->io_ports[IDE_CONTROL_OFFSET] = base + info->ctrloffset;
798 hwif->hw.irq = ec->irq;
801 hwif->chipset = ide_acorn;
802 hwif->gendev.parent = &ec->dev;
809 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
811 unsigned long slot_port;
814 slot_port = ecard_address(ec, ECARD_MEMC, 0);
816 state->irq_port = slot_port;
818 ec->irqaddr = (unsigned char *)ioaddr(slot_port + ICS_ARCIN_V5_INTRSTAT);
820 ec->irq_data = state;
821 ec->ops = &icside_ops_arcin_v5;
824 * Be on the safe side - disable interrupts
826 inb(slot_port + ICS_ARCIN_V5_INTROFFSET);
828 hwif = icside_setup(slot_port, &icside_cardinfo_v5, ec);
830 state->hwif[0] = hwif;
832 return hwif ? 0 : -ENODEV;
836 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
838 unsigned long slot_port, port;
839 ide_hwif_t *hwif, *mate;
840 unsigned int sel = 0;
842 slot_port = ecard_address(ec, ECARD_IOC, ECARD_FAST);
843 port = ecard_address(ec, ECARD_EASI, ECARD_FAST);
850 outb(sel, slot_port);
853 * Be on the safe side - disable interrupts
855 inb(port + ICS_ARCIN_V6_INTROFFSET_1);
856 inb(port + ICS_ARCIN_V6_INTROFFSET_2);
859 * Find and register the interfaces.
861 hwif = icside_setup(port, &icside_cardinfo_v6_1, ec);
862 mate = icside_setup(port, &icside_cardinfo_v6_2, ec);
867 state->irq_port = port;
868 state->slot_port = slot_port;
869 state->hwif[0] = hwif;
870 state->hwif[1] = mate;
872 ec->irq_data = state;
873 ec->ops = &icside_ops_arcin_v6;
875 hwif->maskproc = icside_maskproc;
877 hwif->hwif_data = state;
879 hwif->serialized = 1;
880 hwif->config_data = slot_port;
881 hwif->select_data = sel;
882 hwif->hw.dma = ec->dma;
884 mate->maskproc = icside_maskproc;
886 mate->hwif_data = state;
888 mate->serialized = 1;
889 mate->config_data = slot_port;
890 mate->select_data = sel | 1;
891 mate->hw.dma = ec->dma;
893 if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
894 icside_dma_init(hwif);
895 icside_dma_init(mate);
902 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
904 struct icside_state *state;
908 state = kmalloc(sizeof(struct icside_state), GFP_KERNEL);
914 memset(state, 0, sizeof(state));
915 state->type = ICS_TYPE_NOTYPE;
916 state->dev = &ec->dev;
918 idmem = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST),
919 ecard_resource_len(ec, ECARD_RES_IOCFAST));
923 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
924 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
925 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
926 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
932 switch (state->type) {
934 printk(KERN_WARNING "icside: A3IN unsupported\n");
938 case ICS_TYPE_A3USER:
939 printk(KERN_WARNING "icside: A3USER unsupported\n");
944 ret = icside_register_v5(state, ec);
948 ret = icside_register_v6(state, ec);
952 printk(KERN_WARNING "icside: unknown interface type\n");
958 ecard_set_drvdata(ec, state);
961 * this locks the driver in-core - remove this
962 * comment and the line below when we can
963 * safely remove interfaces.
973 static void __devexit icside_remove(struct expansion_card *ec)
975 struct icside_state *state = ecard_get_drvdata(ec);
977 switch (state->type) {
979 /* FIXME: tell IDE to stop using the interface */
981 /* Disable interrupts */
982 inb(state->slot_port + ICS_ARCIN_V5_INTROFFSET);
986 /* FIXME: tell IDE to stop using the interface */
987 icside_dma_exit(state->hwif[1]);
988 icside_dma_exit(state->hwif[0]);
990 if (ec->dma != NO_DMA)
993 /* Disable interrupts */
994 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
995 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
997 /* Reset the ROM pointer/EASI selection */
998 outb(0, state->slot_port);
1002 ecard_set_drvdata(ec, NULL);
1004 ec->irq_data = NULL;
1009 static void icside_shutdown(struct expansion_card *ec)
1011 struct icside_state *state = ecard_get_drvdata(ec);
1013 switch (state->type) {
1015 /* Disable interrupts */
1016 inb(state->slot_port + ICS_ARCIN_V5_INTROFFSET);
1020 /* Disable interrupts */
1021 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
1022 inb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
1024 /* Reset the ROM pointer/EASI selection */
1025 outb(0, state->slot_port);
1030 static const struct ecard_id icside_ids[] = {
1031 { MANU_ICS, PROD_ICS_IDE },
1032 { MANU_ICS2, PROD_ICS2_IDE },
1036 static struct ecard_driver icside_driver = {
1037 .probe = icside_probe,
1038 .remove = __devexit_p(icside_remove),
1039 .shutdown = icside_shutdown,
1040 .id_table = icside_ids,
1046 static int __init icside_init(void)
1048 return ecard_register_driver(&icside_driver);
1051 static void __exit icside_exit(void)
1053 ecard_remove_driver(&icside_driver);
1056 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
1057 MODULE_LICENSE("GPL");
1058 MODULE_DESCRIPTION("ICS IDE driver");
1060 module_init(icside_init);
1061 module_exit(icside_exit);