1 /******************************************************************************
4 * Project: GEnesis, PCI Gigabit Ethernet Adapter
5 * Version: $Revision: 1.63 $
6 * Date: $Date: 2001/04/05 11:02:09 $
7 * Purpose: Contains functions to initialize the GE HW
9 ******************************************************************************/
11 /******************************************************************************
13 * (C)Copyright 1998-2001 SysKonnect GmbH.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * The information in this file is provided "AS IS" without warranty.
22 ******************************************************************************/
24 /******************************************************************************
28 * $Log: skgeinit.c,v $
29 * Revision 1.63 2001/04/05 11:02:09 rassmann
30 * Stop Port check of the STOP bit did not take 2/18 sec as wanted.
32 * Revision 1.62 2001/02/07 07:54:21 rassmann
33 * Corrected copyright.
35 * Revision 1.61 2001/01/31 15:31:40 gklug
36 * fix: problem with autosensing an SR8800 switch
38 * Revision 1.60 2000/10/18 12:22:21 cgoos
39 * Added workaround for half duplex hangup.
41 * Revision 1.59 2000/10/10 11:22:06 gklug
42 * add: in manual half duplex mode ignore carrier extension errors
44 * Revision 1.58 2000/10/02 14:10:27 rassmann
45 * Reading BCOM PHY after releasing reset until it returns a valid value.
47 * Revision 1.57 2000/08/03 14:55:28 rassmann
48 * Waiting for I2C to be ready before de-initializing adapter
49 * (prevents sensors from hanging up).
51 * Revision 1.56 2000/07/27 12:16:48 gklug
52 * fix: Stop Port check of the STOP bit does now take 2/18 sec as wanted
54 * Revision 1.55 1999/11/22 13:32:26 cgoos
55 * Changed license header to GPL.
57 * Revision 1.54 1999/10/26 07:32:54 malthoff
58 * Initialize PHWLinkUp with SK_FALSE. Required for Diagnostics.
60 * Revision 1.53 1999/08/12 19:13:50 malthoff
61 * Fix for 1000BT. Do not owerwrite XM_MMU_CMD when
62 * disabling receiver and transmitter. Other bits
65 * Revision 1.52 1999/07/01 09:29:54 gklug
66 * fix: DoInitRamQueue needs pAC
68 * Revision 1.51 1999/07/01 08:42:21 gklug
69 * chg: use Store & forward for RAM buffer when Jumbos are used
71 * Revision 1.50 1999/05/27 13:19:38 cgoos
72 * Added Tx PCI watermark initialization.
73 * Removed Tx RAM queue Store & Forward setting.
75 * Revision 1.49 1999/05/20 14:32:45 malthoff
76 * SkGeLinkLED() is completly removed now.
78 * Revision 1.48 1999/05/19 07:28:24 cgoos
79 * SkGeLinkLED no more available for drivers.
80 * Changes for 1000Base-T.
82 * Revision 1.47 1999/04/08 13:57:45 gklug
83 * add: Init of new port struct fiels PLinkResCt
84 * chg: StopPort Timer check
86 * Revision 1.46 1999/03/25 07:42:15 malthoff
87 * SkGeStopPort(): Add workaround for cache incoherency.
88 * Create error log entry, disable port, and
89 * exit loop if it does not terminate.
90 * Add XM_RX_LENERR_OK to the default value for the
91 * XMAC receive command register.
93 * Revision 1.45 1999/03/12 16:24:47 malthoff
94 * Remove PPollRxD and PPollTxD.
95 * Add check for GIPollTimerVal.
97 * Revision 1.44 1999/03/12 13:40:23 malthoff
98 * Fix: SkGeXmitLED(), SK_LED_TST mode does not work.
99 * Add: Jumbo frame support.
100 * Chg: Resolution of parameter IntTime in SkGeCfgSync().
102 * Revision 1.43 1999/02/09 10:29:46 malthoff
103 * Bugfix: The previous modification again also for the second location.
105 * Revision 1.42 1999/02/09 09:35:16 malthoff
106 * Bugfix: The bits '66 MHz Capable' and 'NEWCAP are reset while
107 * clearing the error bits in the PCI status register.
109 * Revision 1.41 1999/01/18 13:07:02 malthoff
110 * Bugfix: Do not use CFG cycles after during Init- or Runtime, because
111 * they may not be available after Boottime.
113 * Revision 1.40 1999/01/11 12:40:49 malthoff
114 * Bug fix: PCI_STATUS: clearing error bits sets the UDF bit.
116 * Revision 1.39 1998/12/11 15:17:33 gklug
117 * chg: Init LipaAutoNeg with Unknown
119 * Revision 1.38 1998/12/10 11:02:57 malthoff
120 * Disable Error Log Message when calling SkGeInit(level 2)
123 * Revision 1.37 1998/12/07 12:18:25 gklug
124 * add: refinement of autosense mode: take into account the autoneg cap of LiPa
126 * Revision 1.36 1998/12/07 07:10:39 gklug
127 * fix: init values of LinkBroken/ Capabilities for management
129 * Revision 1.35 1998/12/02 10:56:20 gklug
130 * fix: do NOT init LoinkSync Counter.
132 * Revision 1.34 1998/12/01 10:53:21 gklug
133 * add: init of additional Counters for workaround
135 * Revision 1.33 1998/12/01 10:00:49 gklug
136 * add: init PIsave var in Port struct
138 * Revision 1.32 1998/11/26 14:50:40 gklug
139 * chg: Default is autosensing with AUTOFULL mode
141 * Revision 1.31 1998/11/25 15:36:16 gklug
142 * fix: do NOT stop LED Timer when port should be stoped
144 * Revision 1.30 1998/11/24 13:15:28 gklug
145 * add: Init PCkeckPar struct member
147 * Revision 1.29 1998/11/18 13:19:27 malthoff
148 * Disable packet arbiter timeouts on receive side.
149 * Use maximum timeout value for packet arbiter
151 * Add TestStopBit() function to handle stop RX/TX
152 * problem with active descriptor poll timers.
153 * Bug Fix: Descriptor Poll Timer not started, beacuse
154 * GIPollTimerVal was initilaized with 0.
156 * Revision 1.28 1998/11/13 14:24:26 malthoff
157 * Bug Fix: SkGeStopPort() may hang if a Packet Arbiter Timout
158 * is pending or occurs while waiting for TX_STOP and RX_STOP.
159 * The PA timeout is cleared now while waiting for TX- or RX_STOP.
161 * Revision 1.27 1998/11/02 11:04:36 malthoff
164 * Revision 1.26 1998/11/02 10:37:03 malthoff
165 * Fix: SkGePollTxD() enables always the synchronounous poll timer.
167 * Revision 1.25 1998/10/28 07:12:43 cgoos
168 * Fixed "LED_STOP" in SkGeLnkSyncCnt, "== SK_INIT_IO" in SkGeInit.
169 * Removed: Reset of RAM Interface in SkGeStopPort.
171 * Revision 1.24 1998/10/27 08:13:12 malthoff
172 * Remove temporary code.
174 * Revision 1.23 1998/10/26 07:45:03 malthoff
175 * Add Address Calculation Workaround: If the EPROM byte
176 * Id is 3, the address offset is 512 kB.
177 * Initialize default values for PLinkMode and PFlowCtrlMode.
179 * Revision 1.22 1998/10/22 09:46:47 gklug
180 * fix SysKonnectFileId typo
182 * Revision 1.21 1998/10/20 12:11:56 malthoff
183 * Don't dendy the Queue config if the size of the unused
186 * Revision 1.20 1998/10/19 07:27:58 malthoff
187 * SkGeInitRamIface() is public to be called by diagnostics.
189 * Revision 1.19 1998/10/16 13:33:45 malthoff
190 * Fix: enabling descriptor polling is not allowed until
191 * the descriptor addresses are set. Descriptor polling
192 * must be handled by the driver.
194 * Revision 1.18 1998/10/16 10:58:27 malthoff
195 * Remove temp. code for Diag prototype.
196 * Remove lint warning for dummy reads.
197 * Call SkGeLoadLnkSyncCnt() during SkGeInitPort().
199 * Revision 1.17 1998/10/14 09:16:06 malthoff
200 * Change parameter LimCount and programming of
201 * the limit counter in SkGeCfgSync().
203 * Revision 1.16 1998/10/13 09:21:16 malthoff
204 * Don't set XM_RX_SELF_RX in RxCmd Reg, because it's
205 * like a Loopback Mode in half duplex.
207 * Revision 1.15 1998/10/09 06:47:40 malthoff
208 * SkGeInitMacArb(): set recovery counters init value
209 * to zero although this counters are not uesd.
210 * Bug fix in Rx Upper/Lower Pause Threshold calculation.
211 * Add XM_RX_SELF_RX to RxCmd.
213 * Revision 1.14 1998/10/06 15:15:53 malthoff
214 * Make sure no pending IRQ is cleared in SkGeLoadLnkSyncCnt().
216 * Revision 1.13 1998/10/06 14:09:36 malthoff
217 * Add SkGeLoadLnkSyncCnt(). Modify
218 * the 'port stopped' condition according
219 * to the current problem report.
221 * Revision 1.12 1998/10/05 08:17:21 malthoff
222 * Add functions: SkGePollRxD(), SkGePollTxD(),
223 * DoCalcAddr(), SkGeCheckQSize(),
224 * DoInitRamQueue(), and SkGeCfgSync().
225 * Add coding for SkGeInitMacArb(), SkGeInitPktArb(),
226 * SkGeInitMacFifo(), SkGeInitRamBufs(),
227 * SkGeInitRamIface(), and SkGeInitBmu().
229 * Revision 1.11 1998/09/29 08:26:29 malthoff
230 * bug fix: SkGeInit0() 'i' should be increment.
232 * Revision 1.10 1998/09/28 13:19:01 malthoff
233 * Coding time: Save the done work.
234 * Modify SkGeLinkLED(), add SkGeXmitLED(),
235 * define SkGeCheckQSize(), SkGeInitMacArb(),
236 * SkGeInitPktArb(), SkGeInitMacFifo(),
237 * SkGeInitRamBufs(), SkGeInitRamIface(),
238 * and SkGeInitBmu(). Do coding for SkGeStopPort(),
239 * SkGeInit1(), SkGeInit2(), and SkGeInit3().
240 * Do coding for SkGeDinit() and SkGeInitPort().
242 * Revision 1.9 1998/09/16 14:29:05 malthoff
243 * Some minor changes.
245 * Revision 1.8 1998/09/11 05:29:14 gklug
246 * add: init state of a port
248 * Revision 1.7 1998/09/04 09:26:25 malthoff
249 * Short temporary modification.
251 * Revision 1.6 1998/09/04 08:27:59 malthoff
252 * Remark the do-while in StopPort() because it never ends
253 * without a GE adapter.
255 * Revision 1.5 1998/09/03 14:05:45 malthoff
256 * Change comment for SkGeInitPort(). Do not
257 * repair the queue sizes if invalid.
259 * Revision 1.4 1998/09/03 10:03:19 malthoff
260 * Implement the new interface according to the
261 * reviewed interface specification.
263 * Revision 1.3 1998/08/19 09:11:25 gklug
264 * fix: struct are removed from c-source (see CCC)
266 * Revision 1.2 1998/07/28 12:33:58 malthoff
267 * Add 'IoC' parameter in function declaration and SK IO macros.
269 * Revision 1.1 1998/07/23 09:48:57 malthoff
270 * Creation. First dummy 'C' file.
271 * SkGeInit(Level 0) is card_start for ML.
272 * SkGeDeInit() is card_stop for ML.
275 ******************************************************************************/
277 #include "h/skdrv1st.h"
278 #include "h/xmac_ii.h"
279 #include "h/skdrv2nd.h"
281 /* defines ********************************************************************/
283 /* defines for SkGeXmitLed() */
284 #define XMIT_LED_INI 0
285 #define XMIT_LED_CNT (RX_LED_VAL - RX_LED_INI)
286 #define XMIT_LED_CTRL (RX_LED_CTRL- RX_LED_INI)
287 #define XMIT_LED_TST (RX_LED_TST - RX_LED_INI)
289 /* Queue Size units */
292 /* Types of RAM Buffer Queues */
293 #define SK_RX_SRAM_Q 1 /* small receive queue */
294 #define SK_RX_BRAM_Q 2 /* big receive queue */
295 #define SK_TX_RAM_Q 3 /* small or big transmit queue */
297 /* typedefs *******************************************************************/
298 /* global variables ***********************************************************/
300 /* local variables ************************************************************/
302 static const char SysKonnectFileId[] =
303 "@(#)$Id: skgeinit.c,v 1.63 2001/04/05 11:02:09 rassmann Exp $ (C) SK ";
306 int RxQOff; /* Receive Queue Address Offset */
307 int XsQOff; /* Sync Tx Queue Address Offset */
308 int XaQOff; /* Async Tx Queue Address Offset */
310 static struct s_QOffTab QOffTab[] = {
311 {Q_R1, Q_XS1, Q_XA1}, {Q_R2, Q_XS2, Q_XA2}
315 /******************************************************************************
317 * SkGePollRxD() - Enable/Disable Descriptor Polling of RxD Ring
320 * Enable or disable the descriptor polling the receive descriptor
321 * ring (RxD) of port 'port'.
322 * The new configuration is *not* saved over any SkGeStopPort() and
323 * SkGeInitPort() calls.
329 SK_AC *pAC, /* adapter context */
330 SK_IOC IoC, /* IO context */
331 int Port, /* Port Index (MAC_1 + n) */
332 SK_BOOL PollRxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
336 pPrt = &pAC->GIni.GP[Port];
339 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_ENA_POL);
342 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_DIS_POL);
347 /******************************************************************************
349 * SkGePollTxD() - Enable/Disable Descriptor Polling of TxD Rings
352 * Enable or disable the descriptor polling the transmit descriptor
353 * ring(s) (RxD) of port 'port'.
354 * The new configuration is *not* saved over any SkGeStopPort() and
355 * SkGeInitPort() calls.
361 SK_AC *pAC, /* adapter context */
362 SK_IOC IoC, /* IO context */
363 int Port, /* Port Index (MAC_1 + n) */
364 SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
369 pPrt = &pAC->GIni.GP[Port];
378 if (pPrt->PXSQSize != 0) {
379 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord);
381 if (pPrt->PXAQSize != 0) {
382 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), DWord);
387 /******************************************************************************
389 * SkGeYellowLED() - Switch the yellow LED on or off.
392 * Switch the yellow LED on or off.
395 * This function may be called any time after SkGeInit(Level 1).
401 SK_AC *pAC, /* adapter context */
402 SK_IOC IoC, /* IO context */
403 int State) /* yellow LED state, 0 = OFF, 0 != ON */
406 /* Switch yellow LED OFF */
407 SK_OUT8(IoC, B0_LED, LED_STAT_OFF);
410 /* Switch yellow LED ON */
411 SK_OUT8(IoC, B0_LED, LED_STAT_ON);
413 } /* SkGeYellowLED */
416 /******************************************************************************
418 * SkGeXmitLED() - Modify the Operational Mode of a transmission LED.
421 * The Rx or Tx LED which is specified by 'Led' will be
422 * enabled, disabled or switched on in test mode.
425 * 'Led' must contain the address offset of the LEDs INI register.
428 * SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
434 SK_AC *pAC, /* adapter context */
435 SK_IOC IoC, /* IO context */
436 int Led, /* offset to the LED Init Value register */
437 int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */
443 LedIni = SK_XMIT_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100;
444 SK_OUT32(IoC, Led + XMIT_LED_INI, LedIni);
445 SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START);
448 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_ON);
449 SK_OUT32(IoC, Led + XMIT_LED_CNT, 100);
450 SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START);
455 * Do NOT stop the LED Timer here. The LED might be
456 * in on state. But it needs to go off.
458 SK_OUT32(IoC, Led + XMIT_LED_CNT, 0);
459 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_OFF);
464 * 1000BT: The Transmit LED is driven by the PHY.
465 * But the default LED configuration is used for
466 * Level One and Broadcom PHYs.
467 * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.)
468 * (In this case it has to be added here. But we will see. XXX)
473 /******************************************************************************
475 * DoCalcAddr() - Calculates the start and the end address of a queue.
478 * This function calculates the start- end the end address
479 * of a queue. Afterwards the 'StartVal' is incremented to the
480 * next start position.
481 * If the port is already initialized the calculated values
482 * will be checked against the configured values and an
483 * error will be returned, if they are not equal.
484 * If the port is not initialized the values will be written to
485 * *StartAdr and *EndAddr.
489 * 1: configuration error
491 static int DoCalcAddr(
492 SK_AC *pAC, /* adapter context */
493 SK_GEPORT *pPrt, /* port index */
494 int QuSize, /* size of the queue to configure in kB */
495 SK_U32 *StartVal, /* start value for address calculation */
496 SK_U32 *QuStartAddr, /* start addr to calculate */
497 SK_U32 *QuEndAddr) /* end address to calculate */
509 EndVal = *StartVal + ((SK_U32)QuSize * 1024) - 1;
510 NextStart = EndVal + 1;
513 if (pPrt->PState >= SK_PRT_INIT) {
514 if (*StartVal != *QuStartAddr || EndVal != *QuEndAddr) {
519 *QuStartAddr = *StartVal;
523 *StartVal = NextStart;
528 /******************************************************************************
530 * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration
533 * This function verifies the Queue Size Configuration specified
534 * in the variabels PRxQSize, PXSQSize, and PXAQSize of all
536 * This requirements must be fullfilled to have a valid configuration:
537 * - The size of all queues must not exceed GIRamSize.
538 * - The queue sizes must be specified in units of 8 kB.
539 * - The size of rx queues of available ports must not be
541 * - The RAM start and end addresses must not be changed
542 * for ports which are already initialized.
543 * Furthermore SkGeCheckQSize() defines the Start and End
544 * Addresses of all ports and stores them into the HWAC port
548 * 0: Queue Size Configuration valid
549 * 1: Queue Size Configuration invalid
551 static int SkGeCheckQSize(
552 SK_AC *pAC, /* adapter context */
553 int Port) /* port index */
564 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
565 pPrt = &pAC->GIni.GP[i];
567 if (( pPrt->PRxQSize & QZ_UNITS) ||
568 (pPrt->PXSQSize & QZ_UNITS) ||
569 (pPrt->PXAQSize & QZ_UNITS)) {
571 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
576 UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize;
578 if (i == Port && pPrt->PRxQSize < SK_MIN_RXQ_SIZE) {
579 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG);
584 if (UsedMem > pAC->GIni.GIRamSize) {
585 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
590 /* Now start address calculation */
591 StartAddr = pAC->GIni.GIRamOffs;
592 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
593 pPrt = &pAC->GIni.GP[i];
595 /* Calculate/Check values for the receive queue */
596 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr,
597 &pPrt->PRxQRamStart, &pPrt->PRxQRamEnd);
600 /* Calculate/Check values for the synchronous tx queue */
601 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXSQSize, &StartAddr,
602 &pPrt->PXsQRamStart, &pPrt->PXsQRamEnd);
605 /* Calculate/Check values for the asynchronous tx queue */
606 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXAQSize, &StartAddr,
607 &pPrt->PXaQRamStart, &pPrt->PXaQRamEnd);
611 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E013, SKERR_HWI_E013MSG);
618 } /* SkGeCheckQSize */
621 /******************************************************************************
623 * SkGeInitMacArb() - Initialize the MAC Arbiter
626 * This function initializes the MAC Arbiter.
627 * It must not be called if there is still an
628 * initilaized or active port.
633 static void SkGeInitMacArb(
634 SK_AC *pAC, /* adapter context */
635 SK_IOC IoC) /* IO context */
637 /* release local reset */
638 SK_OUT16(IoC, B3_MA_TO_CTRL, MA_RST_CLR);
640 /* configure timeout values */
641 SK_OUT8(IoC, B3_MA_TOINI_RX1, SK_MAC_TO_53);
642 SK_OUT8(IoC, B3_MA_TOINI_RX2, SK_MAC_TO_53);
643 SK_OUT8(IoC, B3_MA_TOINI_TX1, SK_MAC_TO_53);
644 SK_OUT8(IoC, B3_MA_TOINI_TX2, SK_MAC_TO_53);
646 SK_OUT8(IoC, B3_MA_RCINI_RX1, 0);
647 SK_OUT8(IoC, B3_MA_RCINI_RX2, 0);
648 SK_OUT8(IoC, B3_MA_RCINI_TX1, 0);
649 SK_OUT8(IoC, B3_MA_RCINI_TX2, 0);
651 /* recovery values are needed for XMAC II Rev. B2 only */
652 /* Fast Output Enable Mode was intended to use with Rev. B2, but now? */
655 * There is not start or enable buttom to push, therefore
656 * the MAC arbiter is configured and enabled now.
658 } /* SkGeInitMacArb */
661 /******************************************************************************
663 * SkGeInitPktArb() - Initialize the Packet Arbiter
666 * This function initializes the Packet Arbiter.
667 * It must not be called if there is still an
668 * initilaized or active port.
673 static void SkGeInitPktArb(
674 SK_AC *pAC, /* adapter context */
675 SK_IOC IoC) /* IO context */
677 /* release local reset */
678 SK_OUT16(IoC, B3_PA_CTRL, PA_RST_CLR);
680 /* configure timeout values */
681 SK_OUT16(IoC, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
682 SK_OUT16(IoC, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
683 SK_OUT16(IoC, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
684 SK_OUT16(IoC, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
687 * enable timeout timers if jumbo frames not used
688 * NOTE: the packet arbiter timeout interrupt is needed for
689 * half duplex hangup workaround
691 if (pAC->GIni.GIPortUsage != SK_JUMBO_LINK) {
692 if (pAC->GIni.GIMacsFound == 1) {
693 SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1);
696 SK_OUT16(IoC, B3_PA_CTRL,(PA_ENA_TO_TX1 | PA_ENA_TO_TX2));
699 } /* SkGeInitPktArb */
702 /******************************************************************************
704 * SkGeInitMacFifo() - Initialize the MAC FIFOs
707 * Initialize all MAC FIFOs of the specified port
712 static void SkGeInitMacFifo(
713 SK_AC *pAC, /* adapter context */
714 SK_IOC IoC, /* IO context */
715 int Port) /* Port Index (MAC_1 + n) */
719 * - release local reset
720 * - use default value for MAC FIFO size
721 * - setup defaults for the control register
724 /* Configure RX MAC FIFO */
725 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR);
726 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF);
727 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
729 /* Configure TX MAC FIFO */
730 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR);
731 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
732 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
734 /* Enable frame flushing if jumbo frames used */
735 if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
736 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
738 } /* SkGeInitMacFifo */
741 /******************************************************************************
743 * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting
746 * This function starts the Link Sync Counter of the specified
747 * port and enables the generation of an Link Sync IRQ.
748 * The Link Sync Counter may be used to detect an active link,
749 * if autonegotiation is not used.
752 * o To ensure receiving the Link Sync Event the LinkSyncCounter
753 * should be initialized BEFORE clearing the XMACs reset!
754 * o Enable IS_LNK_SYNC_M1 and IS_LNK_SYNC_M2 after calling this
760 void SkGeLoadLnkSyncCnt(
761 SK_AC *pAC, /* adapter context */
762 SK_IOC IoC, /* IO context */
763 int Port, /* Port Index (MAC_1 + n) */
764 SK_U32 CntVal) /* Counter value */
772 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_STOP);
776 * Each time starting the Link Sync Counter an IRQ is generated
777 * by the adapter. See problem report entry from 21.07.98
779 * Workaround: Disable Link Sync IRQ and clear the unexpeced IRQ
780 * if no IRQ is already pending.
783 SK_IN32(IoC, B0_ISRC, &ISrc);
784 SK_IN32(IoC, B0_IMSK, &OrgIMsk);
786 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M1;
787 if (ISrc & IS_LNK_SYNC_M1) {
792 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M2;
793 if (ISrc & IS_LNK_SYNC_M2) {
798 SK_OUT32(IoC, B0_IMSK, NewIMsk);
802 SK_OUT32(IoC, MR_ADDR(Port, LNK_SYNC_INI), CntVal);
805 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_START);
808 /* clear the unexpected IRQ, and restore the interrupt mask */
809 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_CLR_IRQ);
810 SK_OUT32(IoC, B0_IMSK, OrgIMsk);
812 } /* SkGeLoadLnkSyncCnt*/
815 /******************************************************************************
817 * SkGeCfgSync() - Configure synchronous bandwidth for this port.
820 * This function may be used to configure synchronous bandwidth
821 * to the specified port. This may be done any time after
822 * initializing the port. The configuration values are NOT saved
823 * in the HWAC port structure and will be overwritten any
824 * time when stopping and starting the port.
825 * Any values for the synchronous configuration will be ignored
826 * if the size of the synchronous queue is zero!
828 * The default configuration for the synchronous service is
829 * TXA_ENA_FSYNC. This means if the size of
830 * the synchronous queue is unequal zero but no specific
831 * synchronous bandwidth is configured, the synchronous queue
832 * will always have the 'unlimitted' transmit priority!
834 * This mode will be restored if the synchronous bandwidth is
835 * deallocated ('IntTime' = 0 and 'LimCount' = 0).
839 * 1: paramter configuration error
840 * 2: try to configure quality of service although no
841 * synchronous queue is configured
844 SK_AC *pAC, /* adapter context */
845 SK_IOC IoC, /* IO context */
846 int Port, /* Port Index (MAC_1 + n) */
847 SK_U32 IntTime, /* Interval Timer Value in units of 8ns */
848 SK_U32 LimCount, /* Number of bytes to transfer during IntTime */
849 int SyncMode) /* Sync Mode: TXA_ENA_ALLOC | TXA_DIS_ALLOC | 0 */
855 /* check the parameters */
856 if (LimCount > IntTime ||
857 (LimCount == 0 && IntTime != 0) ||
858 (LimCount !=0 && IntTime == 0)) {
860 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
864 if (pAC->GIni.GP[Port].PXSQSize != 0) {
865 /* calculate register values */
866 IntTime = (IntTime / 2) * pAC->GIni.GIHstClkFact / 100;
867 LimCount = LimCount / 8;
868 if (IntTime > TXA_MAX_VAL || LimCount > TXA_MAX_VAL) {
869 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
875 * - Enable 'Force Sync' to ensure the synchronous queue
876 * has the priority while configuring the new values.
877 * - Also 'disable alloc' to ensure the settings complies
878 * to the SyncMode parameter.
879 * - Disable 'Rate Control' to configure the new values.
880 * - write IntTime and Limcount
881 * - start 'Rate Control' and disable 'Force Sync'
882 * if Interval Timer or Limit Counter not zero.
884 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
885 TXA_ENA_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
886 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), IntTime);
887 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), LimCount);
888 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
889 (SyncMode & (TXA_ENA_ALLOC|TXA_DIS_ALLOC)));
890 if (IntTime != 0 || LimCount != 0) {
891 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
892 TXA_DIS_FSYNC|TXA_START_RC);
896 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E009, SKERR_HWI_E009MSG);
905 /******************************************************************************
907 * DoInitRamQueue() - Initilaize the RAM Buffer Address of a single Queue
910 * If the queue is used, enable and initilaize it.
911 * Make sure the queue is still reset, if it is not used.
916 static void DoInitRamQueue(
917 SK_AC *pAC, /* adapter context */
918 SK_IOC IoC, /* IO context */
919 int QuIoOffs, /* Queue IO Address Offset */
920 SK_U32 QuStartAddr, /* Queue Start Address */
921 SK_U32 QuEndAddr, /* Queue End Address */
922 int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */
927 if (QuStartAddr != QuEndAddr) {
928 /* calculate thresholds, assume we have a big Rx queue */
929 RxUpThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_ULPP) / 8;
930 RxLoThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_LLPP_B)/8;
932 /* build HW address format */
933 QuStartAddr = QuStartAddr / 8;
934 QuEndAddr = QuEndAddr / 8;
936 /* release local reset */
937 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_CLR);
939 /* configure addresses */
940 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_START), QuStartAddr);
941 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_END), QuEndAddr);
942 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_WP), QuStartAddr);
943 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RP), QuStartAddr);
947 /* configure threshold for small Rx Queue */
948 RxLoThresVal += (SK_RB_LLPP_B - SK_RB_LLPP_S) / 8;
950 /* continue with SK_RX_BRAM_Q */
952 /* write threshold for Rx Queue */
954 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_UTPP), RxUpThresVal);
955 SK_OUT32(IoC, RB_ADDR(QuIoOffs,RB_RX_LTPP), RxLoThresVal);
957 /* the high priority threshold not used */
961 * Do NOT use Store and forward under normal
962 * operation due to performance optimization.
963 * But if Jumbo frames are configured we NEED
964 * the store and forward of the RAM buffer.
966 if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
968 * enable Store & Forward Mode for the
971 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_STFWD);
976 /* set queue operational */
977 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_OP_MD);
980 /* ensure the queue is still disabled */
981 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_SET);
983 } /* DoInitRamQueue*/
986 /******************************************************************************
988 * SkGeInitRamBufs() - Initialize the RAM Buffer Queues
991 * Initialize all RAM Buffer Queues of the specified port
996 static void SkGeInitRamBufs(
997 SK_AC *pAC, /* adapter context */
998 SK_IOC IoC, /* IO context */
999 int Port) /* Port Index (MAC_1 + n) */
1004 pPrt = &pAC->GIni.GP[Port];
1006 if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) {
1007 RxQType = SK_RX_SRAM_Q; /* small Rx Queue */
1010 RxQType = SK_RX_BRAM_Q; /* big Rx Queue */
1013 DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart,
1014 pPrt->PRxQRamEnd, RxQType);
1015 DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart,
1016 pPrt->PXsQRamEnd, SK_TX_RAM_Q);
1017 DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart,
1018 pPrt->PXaQRamEnd, SK_TX_RAM_Q);
1019 } /* SkGeInitRamBufs */
1022 /******************************************************************************
1024 * SkGeInitRamIface() - Initialize the RAM Interface
1027 * This function initializes the Adapbers RAM Interface.
1030 * This function is used in the diagnostics.
1035 void SkGeInitRamIface(
1036 SK_AC *pAC, /* adapter context */
1037 SK_IOC IoC) /* IO context */
1039 /* release local reset */
1040 SK_OUT16(IoC, B3_RI_CTRL, RI_RST_CLR);
1042 /* configure timeout values */
1043 SK_OUT8(IoC, B3_RI_WTO_R1, SK_RI_TO_53);
1044 SK_OUT8(IoC, B3_RI_WTO_XA1, SK_RI_TO_53);
1045 SK_OUT8(IoC, B3_RI_WTO_XS1, SK_RI_TO_53);
1046 SK_OUT8(IoC, B3_RI_RTO_R1, SK_RI_TO_53);
1047 SK_OUT8(IoC, B3_RI_RTO_XA1, SK_RI_TO_53);
1048 SK_OUT8(IoC, B3_RI_RTO_XS1, SK_RI_TO_53);
1049 SK_OUT8(IoC, B3_RI_WTO_R2, SK_RI_TO_53);
1050 SK_OUT8(IoC, B3_RI_WTO_XA2, SK_RI_TO_53);
1051 SK_OUT8(IoC, B3_RI_WTO_XS2, SK_RI_TO_53);
1052 SK_OUT8(IoC, B3_RI_RTO_R2, SK_RI_TO_53);
1053 SK_OUT8(IoC, B3_RI_RTO_XA2, SK_RI_TO_53);
1054 SK_OUT8(IoC, B3_RI_RTO_XS2, SK_RI_TO_53);
1055 } /* SkGeInitRamIface */
1058 /******************************************************************************
1060 * SkGeInitBmu() - Initialize the BMU state machines
1063 * Initialize all BMU state machines of the specified port
1068 static void SkGeInitBmu(
1069 SK_AC *pAC, /* adapter context */
1070 SK_IOC IoC, /* IO context */
1071 int Port) /* Port Index (MAC_1 + n) */
1075 pPrt = &pAC->GIni.GP[Port];
1077 /* Rx Queue: Release all local resets and set the watermark */
1078 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET);
1079 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), SK_BMU_RX_WM);
1082 * Tx Queue: Release all local resets if the queue is used!
1085 if (pPrt->PXSQSize != 0) {
1086 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET);
1087 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), SK_BMU_TX_WM);
1089 if (pPrt->PXAQSize != 0) {
1090 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET);
1091 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), SK_BMU_TX_WM);
1094 * Do NOT enable the descriptor poll timers here, because
1095 * the descriptor addresses are not specified yet.
1100 /******************************************************************************
1102 * TestStopBit() - Test the stop bit of the queue
1105 * Stopping a queue is not as simple as it seems to be.
1106 * If descriptor polling is enabled, it may happen
1107 * that RX/TX stop is done and SV idle is NOT set.
1108 * In this case we have to issue another stop command.
1111 * The queues control status register
1113 static SK_U32 TestStopBit(
1114 SK_AC *pAC, /* Adapter Context */
1115 SK_IOC IoC, /* IO Context */
1116 int QuIoOffs) /* Queue IO Address Offset */
1118 SK_U32 QuCsr; /* CSR contents */
1120 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
1121 if ((QuCsr & (CSR_STOP|CSR_SV_IDLE)) == 0) {
1122 SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP);
1123 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
1129 /******************************************************************************
1131 * SkGeStopPort() - Stop the Rx/Tx activity of the port 'Port'.
1134 * After calling this function the descriptor rings and rx and tx
1135 * queues of this port may be reconfigured.
1137 * It is possible to stop the receive and transmit path separate or
1140 * Dir = SK_STOP_TX Stops the transmit path only and resets
1141 * the XMAC. The receive queue is still and
1142 * the pending rx frames may still transfered
1144 * SK_STOP_RX Stop the receive path. The tansmit path
1145 * has to be stoped once before.
1146 * SK_STOP_ALL SK_STOP_TX + SK_STOP_RX
1148 * RstMode=SK_SOFT_RST Resets the XMAC. The PHY is still alive.
1149 * SK_HARD_RST Resets the XMAC and the PHY.
1152 * 1) A Link Down event was signaled for a port. Therefore the activity
1153 * of this port should be stoped and a hardware reset should be issued
1154 * to enable the workaround of XMAC errata #2. But the received frames
1155 * should not be discarded.
1157 * SkGeStopPort(pAC, IoC, Port, SK_STOP_TX, SK_HARD_RST);
1158 * (transfer all pending rx frames)
1159 * SkGeStopPort(pAC, IoC, Port, SK_STOP_RX, SK_HARD_RST);
1162 * 2) An event was issued which request the driver to switch
1163 * the 'virtual active' link to an other already active port
1164 * as soon as possible. The frames in the receive queue of this
1165 * port may be lost. But the PHY must not be reset during this
1168 * SkGeStopPort(pAC, IoC, Port, SK_STOP_ALL, SK_SOFT_RST);
1171 * Extended Description:
1172 * If SK_STOP_TX is set,
1173 * o disable the XMACs receive and transmiter to prevent
1174 * from sending incomplete frames
1175 * o stop the port's transmit queues before terminating the
1176 * BMUs to prevent from performing incomplete PCI cycles
1178 * - The network rx and tx activity and PCI tx transfer is
1180 * o reset the XMAC depending on the RstMode
1181 * o Stop Interval Timer and Limit Counter of Tx Arbiter,
1182 * also disable Force Sync bit and Enable Alloc bit.
1183 * o perform a local reset of the port's tx path
1184 * - reset the PCI FIFO of the async tx queue
1185 * - reset the PCI FIFO of the sync tx queue
1186 * - reset the RAM Buffer async tx queue
1187 * - reset the RAM Butter sync tx queue
1188 * - reset the MAC Tx FIFO
1189 * o switch Link and Tx LED off, stop the LED counters
1191 * If SK_STOP_RX is set,
1192 * o stop the port's receive queue
1193 * - The path data transfer activity is fully stopped now.
1194 * o perform a local reset of the port's rx path
1195 * - reset the PCI FIFO of the rx queue
1196 * - reset the RAM Buffer receive queue
1197 * - reset the MAC Rx FIFO
1198 * o switch Rx LED off, stop the LED counter
1200 * If all ports are stopped,
1201 * o reset the RAM Interface.
1204 * o This function may be called during the driver states RESET_PORT and
1208 SK_AC *pAC, /* adapter context */
1209 SK_IOC IoC, /* I/O context */
1210 int Port, /* port to stop (MAC_1 + n) */
1211 int Dir, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
1212 int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */
1216 #endif /* !SK_DIAG */
1223 SK_BOOL AllPortsDis;
1227 pPrt = &pAC->GIni.GP[Port];
1229 if (Dir & SK_STOP_TX) {
1230 /* disable the XMACs receiver and transmitter */
1231 XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
1232 XM_OUT16(IoC, Port, XM_MMU_CMD, Word & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1234 /* dummy read to ensure writing */
1235 XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
1237 /* stop both transmit queues */
1239 * If the BMU is in the reset state CSR_STOP will terminate
1242 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_STOP);
1243 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_STOP);
1245 ToutStart = SkOsGetTime(pAC);
1249 * Clear packet arbiter timeout to make sure
1250 * this loop will terminate.
1252 if (Port == MAC_1) {
1253 Word = PA_CLR_TO_TX1;
1256 Word = PA_CLR_TO_TX2;
1258 SK_OUT16(IoC, B3_PA_CTRL, Word);
1261 * If the transfer stucks at the XMAC the STOP command will not
1262 * terminate if we don't flush the XMAC's transmit FIFO!
1264 XM_IN32(IoC, Port, XM_MODE, &DWord);
1266 XM_OUT32(IoC, Port, XM_MODE, DWord);
1268 XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
1269 XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
1271 if (SkOsGetTime(pAC) - ToutStart > (SK_TICKS_PER_SEC / 18)) {
1273 * Timeout of 1/18 second reached.
1274 * This needs to be checked at 1/18 sec only.
1280 * Cache Incoherency workaround: Assume a start command
1281 * has been lost while sending the frame.
1283 ToutStart = SkOsGetTime(pAC);
1284 if (XsCsr & CSR_STOP) {
1285 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_START);
1287 if (XaCsr & CSR_STOP) {
1288 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_START);
1293 /* Might be a problem when the driver event handler
1294 * calls StopPort again.
1298 /* Fatal Error, Loop aborted */
1299 /* Create an Error Log Entry */
1307 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
1308 #endif /* !SK_DIAG */
1314 * Because of the ASIC problem report entry from 21.08.1998 it is
1315 * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set.
1317 } while ((XsCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE ||
1318 (XaCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
1320 /* reset the XMAC depending on the RstMode */
1321 if (RstMode == SK_SOFT_RST) {
1322 SkXmSoftRst(pAC, IoC, Port);
1325 SkXmHardRst(pAC, IoC, Port);
1329 * Stop Interval Timer and Limit Counter of Tx Arbiter,
1330 * also disable Force Sync bit and Enable Alloc bit.
1332 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
1333 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1334 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0x00000000L);
1335 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0x00000000L);
1338 * perform a local reset of the port's tx path
1339 * - reset the PCI FIFO of the async tx queue
1340 * - reset the PCI FIFO of the sync tx queue
1341 * - reset the RAM Buffer async tx queue
1342 * - reset the RAM Butter sync tx queue
1343 * - reset the MAC Tx FIFO
1345 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET);
1346 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET);
1347 SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET);
1348 SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET);
1349 /* Note: MFF_RST_SET does NOT reset the XMAC! */
1350 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_SET);
1352 /* switch Link and Tx LED off, stop the LED counters */
1353 /* Link LED is switched off by the RLMT and the Diag itself */
1354 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_DIS);
1357 if (Dir & SK_STOP_RX) {
1359 * The RX Stop Command will not terminate if no buffers
1360 * are queued in the RxD ring. But it will always reach
1361 * the Idle state. Therefore we can use this feature to
1362 * stop the transfer of received packets.
1364 /* stop the port's receive queue */
1365 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_STOP);
1369 * Clear packet arbiter timeout to make sure
1370 * this loop will terminate
1372 if (Port == MAC_1) {
1373 Word = PA_CLR_TO_RX1;
1376 Word = PA_CLR_TO_RX2;
1378 SK_OUT16(IoC, B3_PA_CTRL, Word);
1380 DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff);
1385 /* finish if CSR_STOP is done or CSR_SV_IDLE is true and i==0 */
1387 * because of the ASIC problem report entry from 21.08.98
1388 * it is required to wait until CSR_STOP is reset and
1389 * CSR_SV_IDLE is set.
1391 } while ((DWord & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE &&
1392 ((DWord & CSR_SV_IDLE) == 0 || i != 0));
1394 /* The path data transfer activity is fully stopped now. */
1397 * perform a local reset of the port's rx path
1398 * - reset the PCI FIFO of the rx queue
1399 * - reset the RAM Buffer receive queue
1400 * - reset the MAC Rx FIFO
1402 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET);
1403 SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_RST_SET);
1404 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_SET);
1406 /* switch Rx LED off, stop the LED counter */
1407 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_DIS);
1412 * If all ports are stopped reset the RAM Interface.
1414 for (i = 0, AllPortsDis = SK_TRUE; i < pAC->GIni.GIMacsFound; i++) {
1415 if (pAC->GIni.GP[i].PState != SK_PRT_RESET &&
1416 pAC->GIni.GP[i].PState != SK_PRT_STOP) {
1418 AllPortsDis = SK_FALSE;
1423 pAC->GIni.GIAnyPortAct = SK_FALSE;
1425 } /* SkGeStopPort */
1428 /******************************************************************************
1430 * SkGeInit0() - Level 0 Initialization
1433 * - Initialize the BMU address offsets
1438 static void SkGeInit0(
1439 SK_AC *pAC, /* adapter context */
1440 SK_IOC IoC) /* IO context */
1445 for (i = 0; i < SK_MAX_MACS; i++) {
1446 pPrt = &pAC->GIni.GP[i];
1447 pPrt->PState = SK_PRT_RESET;
1448 pPrt->PRxQOff = QOffTab[i].RxQOff;
1449 pPrt->PXsQOff = QOffTab[i].XsQOff;
1450 pPrt->PXaQOff = QOffTab[i].XaQOff;
1451 pPrt->PCheckPar = SK_FALSE;
1452 pPrt->PRxCmd = XM_RX_STRIP_FCS | XM_RX_LENERR_OK;
1454 pPrt->PPrevShorts = 0;
1455 pPrt->PLinkResCt = 0;
1456 pPrt->PAutoNegTOCt = 0;
1459 pPrt->PRxLim = SK_DEF_RX_WA_LIM;
1460 pPrt->PLinkMode = SK_LMODE_AUTOFULL;
1461 pPrt->PLinkModeConf = SK_LMODE_AUTOSENSE;
1462 pPrt->PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM;
1463 pPrt->PLinkBroken = SK_TRUE; /* See WA code */
1464 pPrt->PLinkCap = (SK_LMODE_CAP_HALF | SK_LMODE_CAP_FULL |
1465 SK_LMODE_CAP_AUTOHALF | SK_LMODE_CAP_AUTOFULL);
1466 pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN;
1467 pPrt->PFlowCtrlCap = SK_FLOW_MODE_SYM_OR_REM;
1468 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
1469 pPrt->PMSCap = (SK_MS_CAP_AUTO | SK_MS_CAP_MASTER |
1471 pPrt->PMSMode = SK_MS_MODE_AUTO;
1472 pPrt->PMSStatus = SK_MS_STAT_UNSET;
1473 pPrt->PAutoNegFail = SK_FALSE;
1474 pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN;
1475 pPrt->PHWLinkUp = SK_FALSE;
1478 pAC->GIni.GIPortUsage = SK_RED_LINK;
1479 pAC->GIni.GIAnyPortAct = SK_FALSE;
1484 /******************************************************************************
1486 * SkGePciReset() - Reset PCI interface
1489 * o Read PCI configuration.
1490 * o Change power state to 3.
1491 * o Change power state to 0.
1492 * o Restore PCI configuration.
1496 * 1: Power state could not be changed to 3.
1498 static int SkGePciReset(
1499 SK_AC *pAC, /* adapter context */
1500 SK_IOC IoC) /* IO context */
1509 SK_U8 ConfigSpace[PCI_CFG_SIZE];
1512 * Note: Switching to D3 state is like a software reset.
1513 * Switching from D3 to D0 is a hardware reset.
1514 * We have to save and restore the configuration space.
1516 for (i = 0; i < PCI_CFG_SIZE; i++) {
1517 SkPciReadCfgDWord(pAC, i*4, &ConfigSpace[i]);
1520 /* We know the RAM Interface Arbiter is enabled. */
1521 SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D3);
1522 SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
1523 if ((PmCtlSts & PCI_PM_STATE) != PCI_PM_STATE_D3) {
1528 * Return to D0 state.
1530 SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D0);
1532 /* Check for D0 state. */
1533 SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
1534 if ((PmCtlSts & PCI_PM_STATE) != PCI_PM_STATE_D0) {
1539 * Check PCI Config Registers.
1541 SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd);
1542 SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls);
1543 SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1);
1544 SkPciReadCfgDWord(pAC, PCI_BASE_2ND, &Bp2);
1545 SkPciReadCfgByte(pAC, PCI_LAT_TIM, &lat);
1546 if (PciCmd != 0 || Cls != 0 || (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1 ||
1552 * Restore Config Space.
1554 for (i = 0; i < PCI_CFG_SIZE; i++) {
1555 SkPciWriteCfgDWord(pAC, i*4, ConfigSpace[i]);
1559 } /* SkGePciReset */
1561 #endif /* SK_PCI_RESET */
1563 /******************************************************************************
1565 * SkGeInit1() - Level 1 Initialization
1568 * o Do a software reset.
1569 * o Clear all reset bits.
1570 * o Verify that the detected hardware is present.
1571 * Return an error if not.
1572 * o Get the hardware configuration
1573 * + Read the number of MACs/Ports.
1574 * + Read the RAM size.
1575 * + Read the PCI Revision ID.
1576 * + Find out the adapters host clock speed
1577 * + Read and check the PHY type
1581 * 5: Unexpected PHY type detected
1583 static int SkGeInit1(
1584 SK_AC *pAC, /* adapter context */
1585 SK_IOC IoC) /* IO context */
1595 (void)SkGePciReset(pAC, IoC);
1596 #endif /* SK_PCI_RESET */
1599 SK_OUT8(IoC, B0_CTST, CS_RST_SET);
1601 /* Release the reset */
1602 SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
1604 /* Reset all error bits in the PCI STATUS register */
1606 * Note: Cfg cycles cannot be used, because they are not
1607 * available on some platforms after 'boot time'.
1609 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1610 SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
1611 SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS);
1612 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1614 /* Release Master_Reset */
1615 SK_OUT8(IoC, B0_CTST, CS_MRST_CLR);
1617 /* Read number of MACs */
1618 SK_IN8(IoC, B2_MAC_CFG, &Byte);
1619 if (Byte & CFG_SNG_MAC) {
1620 pAC->GIni.GIMacsFound = 1;
1623 pAC->GIni.GIMacsFound = 2;
1625 SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte);
1626 pAC->GIni.GIPciHwRev = (int) Byte;
1628 /* Read the adapters RAM size */
1629 SK_IN8(IoC, B2_E_0, &Byte);
1631 pAC->GIni.GIRamSize = (int)(Byte-1) * 512;
1632 pAC->GIni.GIRamOffs = (SK_U32)512 * 1024;
1635 pAC->GIni.GIRamSize = (int)Byte * 512;
1636 pAC->GIni.GIRamOffs = 0;
1639 /* All known GE Adapters works with 53.125 MHz host clock */
1640 pAC->GIni.GIHstClkFact = SK_FACT_53;
1641 pAC->GIni.GIPollTimerVal =
1642 SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100;
1644 /* Read the PHY type */
1645 SK_IN8(IoC, B2_E_1, &Byte);
1646 Byte &= 0x0f; /* the PHY type is stored in the lower nibble */
1647 for (i=0; i<pAC->GIni.GIMacsFound; i++) {
1648 pAC->GIni.GP[i].PhyType = Byte;
1651 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC;
1654 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM;
1657 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE;
1660 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT;
1663 /* ERROR: unexpected PHY typ detected */
1668 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
1669 ("PHY type: %d PHY addr: %x\n", pAC->GIni.GP[i].PhyType,
1670 pAC->GIni.GP[i].PhyAddr));
1676 /******************************************************************************
1678 * SkGeInit2() - Level 2 Initialization
1681 * - start the Blink Source Counter
1682 * - start the Descriptor Poll Timer
1683 * - configure the MAC-Arbiter
1684 * - configure the Packet-Arbiter
1685 * - enable the Tx Arbiters
1686 * - enable the RAM Interface Arbiter
1691 static void SkGeInit2(
1692 SK_AC *pAC, /* adapter context */
1693 SK_IOC IoC) /* IO context */
1699 /* start the Blink Source Counter */
1700 DWord = SK_BLK_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100;
1701 SK_OUT32(IoC, B2_BSC_INI, DWord);
1702 SK_OUT8(IoC, B2_BSC_CTRL, BSC_START);
1704 /* start the Descriptor Poll Timer */
1705 if (pAC->GIni.GIPollTimerVal != 0) {
1706 if (pAC->GIni.GIPollTimerVal > SK_DPOLL_MAX) {
1707 pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX;
1709 /* Create an Error Log Entry */
1710 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E017, SKERR_HWI_E017MSG);
1712 SK_OUT32(IoC, B28_DPT_INI, pAC->GIni.GIPollTimerVal);
1713 SK_OUT8(IoC, B28_DPT_CTRL, DPT_START);
1718 * - the MAC-Arbiter and
1719 * - the Paket Arbiter
1721 * The MAC and the packet arbiter will be started once
1722 * and never be stopped.
1724 SkGeInitMacArb(pAC, IoC);
1725 SkGeInitPktArb(pAC, IoC);
1727 /* enable the Tx Arbiters */
1728 SK_OUT8(IoC, MR_ADDR(MAC_1, TXA_CTRL), TXA_ENA_ARB);
1729 if (pAC->GIni.GIMacsFound > 1) {
1730 SK_OUT8(IoC, MR_ADDR(MAC_2, TXA_CTRL), TXA_ENA_ARB);
1733 /* enable the RAM Interface Arbiter */
1734 SkGeInitRamIface(pAC, IoC);
1736 for (i = 0; i < SK_MAX_MACS; i++) {
1737 pPrt = &pAC->GIni.GP[i];
1738 if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
1739 pPrt->PRxCmd |= XM_RX_BIG_PK_OK;
1742 if (pPrt->PLinkModeConf == SK_LMODE_HALF) {
1744 * If in manual half duplex mode
1745 * the other side might be in full duplex mode
1746 * so ignore if a carrier extension is not seen on
1749 pPrt->PRxCmd |= XM_RX_DIS_CEXT;
1755 /******************************************************************************
1757 * SkGeInit() - Initialize the GE Adapter with the specified level.
1760 * Level 0: Initialize the Module structures.
1761 * Level 1: Generic Hardware Initialization. The
1762 * IOP/MemBase pointer has to be set before
1763 * calling this level.
1765 * o Do a software reset.
1766 * o Clear all reset bits.
1767 * o Verify that the detected hardware is present.
1768 * Return an error if not.
1769 * o Get the hardware configuration
1770 * + Set GIMacsFound with the number of MACs.
1771 * + Store the RAM size in GIRamSize.
1772 * + Save the PCI Revision ID in GIPciHwRev.
1774 * if Number of MACs > SK_MAX_MACS
1776 * After returning from Level 0 the adapter
1777 * may be accessed with IO operations.
1779 * Level 2: start the Blink Source Counter
1783 * 1: Number of MACs exceeds SK_MAX_MACS ( after level 1)
1784 * 2: Adapter not present or not accessible
1785 * 3: Illegal initialization level
1786 * 4: Initialization Level 1 Call missing
1787 * 5: Unexpected PHY type detected
1790 SK_AC *pAC, /* adapter context */
1791 SK_IOC IoC, /* IO context */
1792 int Level) /* initialization level */
1794 int RetVal; /* return value */
1798 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
1799 ("SkGeInit(Level %d)\n", Level));
1803 /* Initialization Level 0 */
1804 SkGeInit0(pAC, IoC);
1805 pAC->GIni.GILevel = SK_INIT_DATA;
1808 /* Initialization Level 1 */
1809 RetVal = SkGeInit1(pAC, IoC);
1811 /* Check if the adapter seems to be accessible */
1812 SK_OUT32(IoC, B2_IRQM_INI, 0x11335577L);
1813 SK_IN32(IoC, B2_IRQM_INI, &DWord);
1814 SK_OUT32(IoC, B2_IRQM_INI, 0x00000000L);
1815 if (DWord != 0x11335577L) {
1820 /* Check if the number of GIMacsFound matches SK_MAX_MACS */
1821 if (pAC->GIni.GIMacsFound > SK_MAX_MACS) {
1826 /* Level 1 successfully passed */
1827 pAC->GIni.GILevel = SK_INIT_IO;
1830 /* Initialization Level 2 */
1831 if (pAC->GIni.GILevel != SK_INIT_IO) {
1833 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E002, SKERR_HWI_E002MSG);
1838 SkGeInit2(pAC, IoC);
1840 /* Level 2 successfully passed */
1841 pAC->GIni.GILevel = SK_INIT_RUN;
1844 /* Create an Error Log Entry */
1845 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG);
1854 /******************************************************************************
1856 * SkGeDeInit() - Deinitialize the adapter.
1859 * All ports of the adapter will be stopped if not already done.
1860 * Do a software reset and switch off all LEDs.
1866 SK_AC *pAC, /* adapter context */
1867 SK_IOC IoC) /* IO context */
1872 /* Ensure I2C is ready. */
1873 SkI2cWaitIrq(pAC, IoC);
1875 /* Stop all current transfer activity */
1876 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
1877 if (pAC->GIni.GP[i].PState != SK_PRT_STOP &&
1878 pAC->GIni.GP[i].PState != SK_PRT_RESET) {
1880 SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST);
1884 /* Reset all bits in the PCI STATUS register */
1886 * Note: Cfg cycles cannot be used, because they are not
1887 * available on some platforms after 'boot time'.
1889 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1890 SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
1891 SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS);
1892 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1894 /* Do the reset, all LEDs are switched off now */
1895 SK_OUT8(IoC, B0_CTST, CS_RST_SET);
1899 /******************************************************************************
1901 * SkGeInitPort() Initialize the specified prot.
1904 * PRxQSize, PXSQSize, and PXAQSize has to be
1905 * configured for the specified port before calling this
1906 * function. The descriptor rings has to be initialized, too.
1908 * o (Re)configure queues of the specified port.
1909 * o configure the XMAC of the specified port.
1910 * o put ASIC and XMAC(s) in operational mode.
1911 * o initialize Rx/Tx and Sync LED
1912 * o initialize RAM Buffers and MAC FIFOs
1914 * The port is ready to connect when returning.
1917 * The XMACs Rx and Tx state machine is still disabled when
1922 * 1: Queue size initialization error. The configured values
1923 * for PRxQSize, PXSQSize, or PXAQSize are invalid for one
1924 * or more queues. The specified port was NOT initialized.
1925 * An error log entry was generated.
1926 * 2: The port has to be stopped before it can be initialized again.
1929 SK_AC *pAC, /* adapter context */
1930 SK_IOC IoC, /* IO context */
1931 int Port) /* Port to configure */
1935 pPrt = &pAC->GIni.GP[Port];
1937 if (SkGeCheckQSize(pAC, Port) != 0) {
1938 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG);
1941 if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) {
1942 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG);
1946 /* Configuration ok, initialize the Port now */
1948 /* Initialize Rx, Tx and Link LED */
1950 * If 1000BT Phy needs LED initialization than swap
1951 * LED and XMAC initialization order
1953 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
1954 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_ENA);
1955 /* The Link LED is initialized by RLMT or Diagnostics itself */
1957 /* Do NOT initialize the Link Sync Counter */
1964 * - enable Force Sync bit if synchronous queue available
1967 SkXmInitMac(pAC, IoC, Port);
1968 SkGeInitMacFifo(pAC, IoC, Port);
1969 SkGeInitRamBufs(pAC, IoC, Port);
1970 if (pPrt->PXSQSize != 0) {
1971 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC);
1973 SkGeInitBmu(pAC, IoC, Port);
1975 /* Mark port as initialized. */
1976 pPrt->PState = SK_PRT_INIT;
1977 pAC->GIni.GIAnyPortAct = SK_TRUE;
1980 } /* SkGeInitPort */