include/asm-ia64/sn/sn1/ip27config.h

   1 /* $Id$
   2  *
   3  * This file is subject to the terms and conditions of the GNU General Public
   4  * License.  See the file "COPYING" in the main directory of this archive
   5  * for more details.
   6  *
   7  * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
   8  */
   9
  10 #ifndef _ASM_IA64_SN_SN1_IP27CONFIG_H
  11 #define _ASM_IA64_SN_SN1_IP27CONFIG_H
  12
  13
  14 /*
  15  * Structure:   ip27config_s
  16  * Typedef:     ip27config_t
  17  * Purpose:     Maps out the region of the boot prom used to define
  18  *              configuration information.
  19  * Notes:       Corresponds to ip27config structure found in start.s.
  20  *              Fields are ulong where possible to facilitate IP27 PROM fetches.
  21  */
  22
  23 #define CONFIG_INFO_OFFSET              0x60
  24
  25 #define IP27CONFIG_ADDR                 (LBOOT_BASE         + \
  26                                          CONFIG_INFO_OFFSET)
  27 #define IP27CONFIG_ADDR_NODE(n)         (NODE_RBOOT_BASE(n) + \
  28                                          CONFIG_INFO_OFFSET)
  29
  30 /* Offset to the config_type field within local ip27config structure */
  31 #define CONFIG_FLAGS_ADDR                       (IP27CONFIG_ADDR + 72)
  32 /* Offset to the config_type field in the ip27config structure on
  33  * node with nasid n
  34  */
  35 #define CONFIG_FLAGS_ADDR_NODE(n)               (IP27CONFIG_ADDR_NODE(n) + 72)
  36
  37 /* Meaning of each valid bit in the config flags
  38  * None are currently defined
  39  */
  40
  41 /* Meaning of each mach_type value
  42  */
  43 #define SN1_MACH_TYPE 0
  44
  45 /*
  46  * Since 800 ns works well with various HUB frequencies, (such as 360,
  47  * 380, 390, and 400 MHZ), we now use 800ns rtc cycle time instead of
  48  * 1 microsec.
  49  */
  50 #define IP27_RTC_FREQ                   1250    /* 800ns cycle time */
  51
  52 #ifndef __ASSEMBLY__
  53
  54 typedef struct ip27config_s {           /* KEEP IN SYNC w/ start.s & below  */
  55     uint                time_const;     /* Time constant                    */
  56     uint                r10k_mode;      /* R10k boot mode bits              */
  57
  58     uint64_t            magic;          /* CONFIG_MAGIC                     */
  59
  60     uint64_t            freq_cpu;       /* Hz                               */
  61     uint64_t            freq_hub;       /* Hz                               */
  62     uint64_t            freq_rtc;       /* Hz                               */
  63
  64     uint                ecc_enable;     /* ECC enable flag                  */
  65     uint                fprom_cyc;      /* FPROM_CYC speed control          */
  66
  67     uint                mach_type;      /* Inidicate IP27 (0) or Sn00 (1)    */
  68
  69     uint                check_sum_adj;  /* Used after config hdr overlay    */
  70                                         /* to make the checksum 0 again     */
  71     uint                flash_count;    /* Value incr'd on each PROM flash  */
  72     uint                fprom_wr;       /* FPROM_WR speed control           */
  73
  74     uint                pvers_vers;     /* Prom version number              */
  75     uint                pvers_rev;      /* Prom revision number             */
  76     uint                config_type;    /* To support special configurations
  77                                          * (none currently defined)
  78                                          */
  79 } ip27config_t;
  80
  81 typedef struct {
  82     uint                r10k_mode;      /* R10k boot mode bits              */
  83     uint                freq_cpu;       /* Hz                               */
  84     uint                freq_hub;       /* Hz                               */
  85     char                fprom_cyc;      /* FPROM_CYC speed control          */
  86     char                mach_type;      /* IP35(0) is only type defined      */
  87     char                fprom_wr;       /* FPROM_WR speed control           */
  88 } config_modifiable_t;
  89
  90 #define IP27CONFIG              (*(ip27config_t *) IP27CONFIG_ADDR)
  91 #define IP27CONFIG_NODE(n)      (*(ip27config_t *) IP27CONFIG_ADDR_NODE(n))
  92 #define SN00                    0 /* IP35 has no Speedo equivalent */
  93
  94 /* Get the config flags from local ip27config */
  95 #define CONFIG_FLAGS            (*(uint *) (CONFIG_FLAGS_ADDR))
  96
  97 /* Get the config flags from ip27config on the node
  98  * with nasid n
  99  */
 100 #define CONFIG_FLAGS_NODE(n)    (*(uint *) (CONFIG_FLAGS_ADDR_NODE(n)))
 101
 102 /* Macro to check if the local ip27config indicates a config
 103  * of 12 p 4io
 104  */
 105 #define CONFIG_12P4I            (0) /* IP35 has no 12p4i equivalent */
 106
 107 /* Macro to check if the ip27config on node with nasid n
 108  * indicates a config of 12 p 4io
 109  */
 110 #define CONFIG_12P4I_NODE(n)    (0)
 111
 112 #endif /* __ASSEMBLY__ */
 113
 114 #if __ASSEMBLY__
 115         .struct         0               /* KEEP IN SYNC WITH C structure */
 116
 117 ip27c_time_const:       .word   0
 118 ip27c_r10k_mode:        .word   0
 119
 120 ip27c_magic:            .dword  0
 121
 122 ip27c_freq_cpu:         .dword  0
 123 ip27c_freq_hub:         .dword  0
 124 ip27c_freq_rtc:         .dword  0
 125
 126 ip27c_ecc_enable:       .word   1
 127 ip27c_fprom_cyc:        .word   0
 128
 129 ip27c_mach_type:        .word   0
 130 ip27c_check_sum_adj:    .word   0
 131
 132 ip27c_flash_count:      .word   0
 133 ip27c_fprom_wr:         .word   0
 134
 135 ip27c_pvers_vers:       .word   0
 136 ip27c_pvers_rev:        .word   0
 137
 138 ip27c_config_type:      .word   0       /* To recognize special configs */
 139 #endif /* __ASSEMBLY__ */
 140
 141 /*
 142  * R10000 Configuration Cycle - These define the SYSAD values used
 143  * during the reset cycle.
 144  */
 145
 146 #define IP27C_R10000_KSEG0CA_SHFT       0
 147 #define IP27C_R10000_KSEG0CA_MASK       (7 << IP27C_R10000_KSEG0CA_SHFT)
 148 #define IP27C_R10000_KSEG0CA(_B)         ((_B) << IP27C_R10000_KSEG0CA_SHFT)
 149
 150 #define IP27C_R10000_DEVNUM_SHFT        3
 151 #define IP27C_R10000_DEVNUM_MASK        (3 << IP27C_R10000_DEVNUM_SHFT)
 152 #define IP27C_R10000_DEVNUM(_B)         ((_B) << IP27C_R10000_DEVNUM_SHFT)
 153
 154 #define IP27C_R10000_CRPT_SHFT          5
 155 #define IP27C_R10000_CRPT_MASK          (1 << IP27C_R10000_CRPT_SHFT)
 156 #define IP27C_R10000_CPRT(_B)           ((_B)<<IP27C_R10000_CRPT_SHFT)
 157
 158 #define IP27C_R10000_PER_SHFT           6
 159 #define IP27C_R10000_PER_MASK           (1 << IP27C_R10000_PER_SHFT)
 160 #define IP27C_R10000_PER(_B)            ((_B) << IP27C_R10000_PER_SHFT)
 161
 162 #define IP27C_R10000_PRM_SHFT           7
 163 #define IP27C_R10000_PRM_MASK           (3 << IP27C_R10000_PRM_SHFT)
 164 #define IP27C_R10000_PRM(_B)            ((_B) << IP27C_R10000_PRM_SHFT)
 165
 166 #define IP27C_R10000_SCD_SHFT           9
 167 #define IP27C_R10000_SCD_MASK           (0xf << IP27C_R10000_SCD_MASK)
 168 #define IP27C_R10000_SCD(_B)            ((_B) << IP27C_R10000_SCD_SHFT)
 169
 170 #define IP27C_R10000_SCBS_SHFT          13
 171 #define IP27C_R10000_SCBS_MASK          (1 << IP27C_R10000_SCBS_SHFT)
 172 #define IP27C_R10000_SCBS(_B)           (((_B)) << IP27C_R10000_SCBS_SHFT)
 173
 174 #define IP27C_R10000_SCCE_SHFT          14
 175 #define IP27C_R10000_SCCE_MASK          (1 << IP27C_R10000_SCCE_SHFT)
 176 #define IP27C_R10000_SCCE(_B)           ((_B) << IP27C_R10000_SCCE_SHFT)
 177
 178 #define IP27C_R10000_ME_SHFT            15
 179 #define IP27C_R10000_ME_MASK            (1 << IP27C_R10000_ME_SHFT)
 180 #define IP27C_R10000_ME(_B)             ((_B) << IP27C_R10000_ME_SHFT)
 181
 182 #define IP27C_R10000_SCS_SHFT           16
 183 #define IP27C_R10000_SCS_MASK           (7 << IP27C_R10000_SCS_SHFT)
 184 #define IP27C_R10000_SCS(_B)            ((_B) << IP27C_R10000_SCS_SHFT)
 185
 186 #define IP27C_R10000_SCCD_SHFT          19
 187 #define IP27C_R10000_SCCD_MASK          (7 << IP27C_R10000_SCCD_SHFT)
 188 #define IP27C_R10000_SCCD(_B)           ((_B) << IP27C_R10000_SCCD_SHFT)
 189
 190 #define IP27C_R10000_DDR_SHFT           23
 191 #define IP27C_R10000_DDR_MASK           (1 << IP27C_R10000_DDR_SHFT)
 192 #define IP27C_R10000_DDR(_B)            ((_B) << IP27C_R10000_DDR_SHFT)
 193
 194 #define IP27C_R10000_SCCT_SHFT          25
 195 #define IP27C_R10000_SCCT_MASK          (0xf << IP27C_R10000_SCCT_SHFT)
 196 #define IP27C_R10000_SCCT(_B)           ((_B) << IP27C_R10000_SCCT_SHFT)
 197
 198 #define IP27C_R10000_ODSC_SHFT          29
 199 #define IP27C_R10000_ODSC_MASK          (1 << IP27C_R10000_ODSC_SHFT)
 200 #define IP27C_R10000_ODSC(_B)           ((_B) << IP27C_R10000_ODSC_SHFT)
 201
 202 #define IP27C_R10000_ODSYS_SHFT         30
 203 #define IP27C_R10000_ODSYS_MASK         (1 << IP27C_R10000_ODSYS_SHFT)
 204 #define IP27C_R10000_ODSYS(_B)          ((_B) << IP27C_R10000_ODSYS_SHFT)
 205
 206 #define IP27C_R10000_CTM_SHFT           31
 207 #define IP27C_R10000_CTM_MASK           (1 << IP27C_R10000_CTM_SHFT)
 208 #define IP27C_R10000_CTM(_B)            ((_B) << IP27C_R10000_CTM_SHFT)
 209
 210 #define IP27C_MHZ(x)                    (1000000 * (x))
 211 #define IP27C_KHZ(x)                    (1000 * (x))
 212 #define IP27C_MB(x)                     ((x) << 20)
 213
 214 /*
 215  * PROM Configurations
 216  */
 217
 218 #define CONFIG_MAGIC            0x69703237636f6e66
 219
 220 /* The high 32 bits of the "mode bits".  Bits 7..0 contain one more
 221  * than the number of 5ms clocks in the 100ms "long delay" intervals
 222  * of the TRex reset sequence.  Bit 8 is the "synergy mode" bit.
 223  */
 224 #define CONFIG_TIME_CONST       0x15
 225
 226 #define CONFIG_ECC_ENABLE       1
 227 #define CONFIG_CHECK_SUM_ADJ    0
 228 #define CONFIG_DEFAULT_FLASH_COUNT    0
 229
 230 /*
 231  * Some promICEs have trouble if CONFIG_FPROM_SETUP is too low.
 232  * The nominal value for 100 MHz hub is 5, for 200MHz bedrock is 16.
 233  * any update to the below should also reflected in the logic in
 234  *   IO7prom/flashprom.c function _verify_config_info and _fill_in_config_info
 235  */
 236
 237 /* default junk bus timing values to use */
 238 #define CONFIG_SYNERGY_ENABLE   0xff
 239 #define CONFIG_SYNERGY_SETUP    0xff
 240 #define CONFIG_UART_ENABLE      0x0c
 241 #define CONFIG_UART_SETUP       0x02
 242 #define CONFIG_FPROM_ENABLE     0x10
 243 #define CONFIG_FPROM_SETUP      0x10
 244
 245 #define CONFIG_FREQ_RTC IP27C_KHZ(IP27_RTC_FREQ)
 246
 247 #ifndef __ASSEMBLY__
 248
 249 /* we are going to define all the known configs is a table
 250  * for building hex images we will pull out the particular
 251  * slice we care about by using the IP27_CONFIG_XX_XX as
 252  * entries into the table
 253  * to keep the table of reasonable size we only include the
 254  * values that differ across configurations
 255  * please note then that this makes assumptions about what
 256  * will and will not change across configurations
 257  */
 258
 259 /* these numbers are as the are ordered in the table below */
 260 #define IP27_CONFIG_UNKNOWN (-1)
 261 #define IP27_CONFIG_SN1_1MB_200_400_200_TABLE 0
 262 #define IP27_CONFIG_SN00_4MB_100_200_133_TABLE 1
 263 #define IP27_CONFIG_SN1_4MB_200_400_267_TABLE 2
 264 #define IP27_CONFIG_SN1_8MB_200_500_250_TABLE 3
 265 #define IP27_CONFIG_SN1_8MB_200_400_267_TABLE 4
 266 #define IP27_CONFIG_SN1_4MB_180_360_240_TABLE 5
 267 #define NUMB_IP_CONFIGS 6
 268
 269 #ifdef DEF_IP_CONFIG_TABLE
 270 /*
 271  * N.B.: A new entry needs to be added here everytime a new config is added
 272  * The table is indexed by the PIMM PSC value
 273  */
 274
 275 static int psc_to_flash_config[] = {
 276         IP27_CONFIG_SN1_4MB_200_400_267_TABLE,  /* 0x0 */
 277         IP27_CONFIG_SN1_8MB_200_500_250_TABLE,  /* 0x1 */
 278         IP27_CONFIG_SN1_8MB_200_400_267_TABLE,  /* 0x2 */
 279         IP27_CONFIG_UNKNOWN,    /* 0x3 */
 280         IP27_CONFIG_UNKNOWN,    /* 0x4 */
 281         IP27_CONFIG_UNKNOWN,    /* 0x5 */
 282         IP27_CONFIG_UNKNOWN,    /* 0x6 */
 283         IP27_CONFIG_UNKNOWN,    /* 0x7 */
 284         IP27_CONFIG_SN1_4MB_180_360_240_TABLE,  /* 0x8 */
 285         IP27_CONFIG_UNKNOWN,    /* 0x9 */
 286         IP27_CONFIG_UNKNOWN,    /* 0xa */
 287         IP27_CONFIG_UNKNOWN,    /* 0xb */
 288         IP27_CONFIG_UNKNOWN,    /* 0xc */
 289         IP27_CONFIG_UNKNOWN,    /* 0xd */
 290         IP27_CONFIG_SN00_4MB_100_200_133_TABLE, /* 0xe  O200 PIMM for bringup */
 291         IP27_CONFIG_UNKNOWN     /* 0xf == PIMM not installed */
 292 };
 293
 294 static config_modifiable_t ip_config_table[NUMB_IP_CONFIGS] = {
 295 /* the 1MB_200_400_200 values (Generic settings, will work for any config.) */
 296 {
 297         (IP27C_R10000_KSEG0CA(5) + \
 298          IP27C_R10000_DEVNUM(0)  + \
 299          IP27C_R10000_CPRT(0)    + \
 300          IP27C_R10000_PER(0)     + \
 301          IP27C_R10000_PRM(3)     + \
 302          IP27C_R10000_SCD(3)     + \
 303          IP27C_R10000_SCBS(1)    + \
 304          IP27C_R10000_SCCE(0)    + \
 305          IP27C_R10000_ME(1)      + \
 306          IP27C_R10000_SCS(1)     + \
 307          IP27C_R10000_SCCD(3)    + \
 308          IP27C_R10000_SCCT(9)    + \
 309          IP27C_R10000_ODSC(0)    + \
 310          IP27C_R10000_ODSYS(1)   + \
 311          IP27C_R10000_CTM(0)),
 312         IP27C_MHZ(400),
 313         IP27C_MHZ(200),
 314         CONFIG_FPROM_SETUP,
 315         SN1_MACH_TYPE,
 316         CONFIG_FPROM_ENABLE
 317 },
 318
 319 /* the 4MB_100_200_133 values (O200 PIMM w/translation board, PSC 0xe)
 320  * (SysAD at 100MHz (SCD=3), and bedrock core at 200 MHz) */
 321 {
 322  /* ODSYS == 0 means HSTL1 on SysAD bus; other PIMMs use HSTL2 */
 323         (IP27C_R10000_KSEG0CA(5) + \
 324          IP27C_R10000_DEVNUM(0)  + \
 325          IP27C_R10000_CPRT(0)    + \
 326          IP27C_R10000_PER(0)     + \
 327          IP27C_R10000_PRM(3)     + \
 328          IP27C_R10000_SCD(3)     + \
 329          IP27C_R10000_SCBS(1)    + \
 330          IP27C_R10000_SCCE(0)    + \
 331          IP27C_R10000_ME(1)      + \
 332          IP27C_R10000_SCS(3)     + \
 333          IP27C_R10000_SCCD(2)    + \
 334          IP27C_R10000_SCCT(9)    + \
 335          IP27C_R10000_ODSC(0)    + \
 336          IP27C_R10000_ODSYS(0)   + \
 337          IP27C_R10000_CTM(0)),
 338         IP27C_MHZ(200),
 339         IP27C_MHZ(200),
 340         CONFIG_FPROM_SETUP,
 341         SN1_MACH_TYPE,
 342         CONFIG_FPROM_ENABLE
 343 },
 344
 345 /* 4MB_200_400_267 values (R12KS, 3.7ns, LWR, 030-1602-001, PSC 0x0) */
 346 {
 347         (IP27C_R10000_KSEG0CA(5) + \
 348          IP27C_R10000_DEVNUM(0)  + \
 349          IP27C_R10000_CPRT(0)    + \
 350          IP27C_R10000_PER(0)     + \
 351          IP27C_R10000_PRM(3)     + \
 352          IP27C_R10000_SCD(3)     + \
 353          IP27C_R10000_SCBS(1)    + \
 354          IP27C_R10000_SCCE(0)    + \
 355          IP27C_R10000_ME(1)      + \
 356          IP27C_R10000_SCS(3)     + \
 357          IP27C_R10000_SCCD(2)    + \
 358          IP27C_R10000_SCCT(0xa)  + \
 359          IP27C_R10000_ODSC(0)    + \
 360          IP27C_R10000_ODSYS(1)   + \
 361          IP27C_R10000_CTM(0)),
 362         IP27C_MHZ(400),
 363         IP27C_MHZ(200),
 364         CONFIG_FPROM_SETUP,
 365         SN1_MACH_TYPE,
 366         CONFIG_FPROM_ENABLE
 367 },
 368
 369 /* 8MB_200_500_250 values (R14K, 4.0ns, DDR1, 030-1520-001, PSC 0x1) */
 370 {
 371         (IP27C_R10000_KSEG0CA(5) + \
 372          IP27C_R10000_DEVNUM(0)  + \
 373          IP27C_R10000_CPRT(0)    + \
 374          IP27C_R10000_PER(0)     + \
 375          IP27C_R10000_PRM(3)     + \
 376          IP27C_R10000_SCD(4)     + \
 377          IP27C_R10000_SCBS(1)    + \
 378          IP27C_R10000_SCCE(0)    + \
 379          IP27C_R10000_ME(1)      + \
 380          IP27C_R10000_SCS(4)     + \
 381          IP27C_R10000_DDR(1)     + \
 382          IP27C_R10000_SCCD(3)    + \
 383          IP27C_R10000_SCCT(0xa)  + \
 384          IP27C_R10000_ODSC(0)    + \
 385          IP27C_R10000_ODSYS(1)   + \
 386          IP27C_R10000_CTM(0)),
 387         IP27C_MHZ(500),
 388         IP27C_MHZ(200),
 389         CONFIG_FPROM_SETUP,
 390         SN1_MACH_TYPE,
 391         CONFIG_FPROM_ENABLE
 392 },
 393
 394 /* 8MB_200_400_267 values (R12KS, 3.7ns, LWR, 030-1616-001, PSC 0x2) */
 395 {
 396         (IP27C_R10000_KSEG0CA(5) + \
 397          IP27C_R10000_DEVNUM(0)  + \
 398          IP27C_R10000_CPRT(0)    + \
 399          IP27C_R10000_PER(0)     + \
 400          IP27C_R10000_PRM(3)     + \
 401          IP27C_R10000_SCD(3)     + \
 402          IP27C_R10000_SCBS(1)    + \
 403          IP27C_R10000_SCCE(0)    + \
 404          IP27C_R10000_ME(1)      + \
 405          IP27C_R10000_SCS(4)     + \
 406          IP27C_R10000_SCCD(2)    + \
 407          IP27C_R10000_SCCT(0xa)  + \
 408          IP27C_R10000_ODSC(0)    + \
 409          IP27C_R10000_ODSYS(1)   + \
 410          IP27C_R10000_CTM(0)),
 411         IP27C_MHZ(400),
 412         IP27C_MHZ(200),
 413         CONFIG_FPROM_SETUP,
 414         SN1_MACH_TYPE,
 415         CONFIG_FPROM_ENABLE
 416 },
 417
 418 /* 4MB_180_360_240 values (R12KS, 3.7ns, LWR, 030-1627-001, PSC 0x8)
 419  * (SysAD at 180 MHz (SCD=3, the fastest possible), bedrock core at 200MHz) */
 420 {
 421         (IP27C_R10000_KSEG0CA(5) + \
 422          IP27C_R10000_DEVNUM(0)  + \
 423          IP27C_R10000_CPRT(0)    + \
 424          IP27C_R10000_PER(0)     + \
 425          IP27C_R10000_PRM(3)     + \
 426          IP27C_R10000_SCD(3)     + \
 427          IP27C_R10000_SCBS(1)    + \
 428          IP27C_R10000_SCCE(0)    + \
 429          IP27C_R10000_ME(1)      + \
 430          IP27C_R10000_SCS(3)     + \
 431          IP27C_R10000_SCCD(2)    + \
 432          IP27C_R10000_SCCT(9)    + \
 433          IP27C_R10000_ODSC(0)    + \
 434          IP27C_R10000_ODSYS(1)   + \
 435          IP27C_R10000_CTM(0)),
 436         IP27C_MHZ(360),
 437         IP27C_MHZ(200),
 438         CONFIG_FPROM_SETUP,
 439         SN1_MACH_TYPE,
 440         CONFIG_FPROM_ENABLE
 441 },
 442
 443 };
 444 #else
 445 extern  config_modifiable_t     ip_config_table[];
 446 #endif /* DEF_IP27_CONFIG_TABLE */
 447
 448 #ifdef IP27_CONFIG_SN00_4MB_100_200_133
 449 #define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].r10k_mode
 450 #define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].freq_cpu
 451 #define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].freq_hub
 452 #define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].fprom_cyc
 453 #define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].mach_type
 454 #define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].fprom_wr
 455 #endif /* IP27_CONFIG_SN00_4MB_100_200_133 */
 456
 457 #ifdef IP27_CONFIG_SN1_1MB_200_400_200
 458 #define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].r10k_mode
 459 #define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].freq_cpu
 460 #define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].freq_hub
 461 #define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].fprom_cyc
 462 #define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].mach_type
 463 #define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].fprom_wr
 464 #endif /* IP27_CONFIG_SN1_1MB_200_400_200 */
 465
 466 #ifdef IP27_CONFIG_SN1_4MB_200_400_267
 467 #define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].r10k_mode
 468 #define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].freq_cpu
 469 #define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].freq_hub
 470 #define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].fprom_cyc
 471 #define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].mach_type
 472 #define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].fprom_wr
 473 #endif /* IP27_CONFIG_SN1_4MB_200_400_267 */
 474
 475 #ifdef IP27_CONFIG_SN1_8MB_200_500_250
 476 #define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].r10k_mode
 477 #define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].freq_cpu
 478 #define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].freq_hub
 479 #define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].fprom_cyc
 480 #define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].mach_type
 481 #define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].fprom_wr
 482 #endif /* IP27_CONFIG_SN1_8MB_200_500_250 */
 483
 484 #ifdef IP27_CONFIG_SN1_8MB_200_400_267
 485 #define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].r10k_mode
 486 #define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].freq_cpu
 487 #define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].freq_hub
 488 #define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].fprom_cyc
 489 #define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].mach_type
 490 #define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].fprom_wr
 491 #endif /* IP27_CONFIG_SN1_8MB_200_400_267 */
 492
 493 #ifdef IP27_CONFIG_SN1_4MB_180_360_240
 494 #define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].r10k_mode
 495 #define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].freq_cpu
 496 #define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].freq_hub
 497 #define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].fprom_cyc
 498 #define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].mach_type
 499 #define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].fprom_wr
 500 #endif /* IP27_CONFIG_SN1_4MB_180_360_240 */
 501
 502 #endif /* __ASSEMBLY__ */
 503
 504 #if __ASSEMBLY__
 505
 506 /* these need to be in here since we need assembly definitions
 507  * for building hex images (as required by start.s)
 508  */
 509 #ifdef IP27_CONFIG_SN00_4MB_100_200_133
 510 #define BRINGUP_PRM_VAL 3
 511 #define CONFIG_CPU_MODE \
 512         (IP27C_R10000_KSEG0CA(5) + \
 513          IP27C_R10000_DEVNUM(0)  + \
 514          IP27C_R10000_CPRT(0)    + \
 515          IP27C_R10000_PER(0)     + \
 516          IP27C_R10000_PRM(BRINGUP_PRM_VAL)       + \
 517          IP27C_R10000_SCD(3)     + \
 518          IP27C_R10000_SCBS(1)    + \
 519          IP27C_R10000_SCCE(0)    + \
 520          IP27C_R10000_ME(1)      + \
 521          IP27C_R10000_SCS(3)     + \
 522          IP27C_R10000_SCCD(2)    + \
 523          IP27C_R10000_SCCT(9)    + \
 524          IP27C_R10000_ODSC(0)    + \
 525          IP27C_R10000_ODSYS(0)   + \
 526          IP27C_R10000_CTM(0))
 527 #define CONFIG_FREQ_CPU IP27C_MHZ(200)
 528 #define CONFIG_FREQ_HUB IP27C_MHZ(200)
 529 #define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
 530 #define CONFIG_MACH_TYPE SN1_MACH_TYPE
 531 #define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
 532 #endif /* IP27_CONFIG_SN00_4MB_100_200_133 */
 533
 534 #ifdef IP27_CONFIG_SN1_1MB_200_400_200
 535 #define CONFIG_CPU_MODE \
 536         (IP27C_R10000_KSEG0CA(5) + \
 537          IP27C_R10000_DEVNUM(0)  + \
 538          IP27C_R10000_CPRT(0)    + \
 539          IP27C_R10000_PER(0)     + \
 540          IP27C_R10000_PRM(3)     + \
 541          IP27C_R10000_SCD(3)     + \
 542          IP27C_R10000_SCBS(1)    + \
 543          IP27C_R10000_SCCE(0)    + \
 544          IP27C_R10000_ME(1)      + \
 545          IP27C_R10000_SCS(1)     + \
 546          IP27C_R10000_SCCD(3)    + \
 547          IP27C_R10000_SCCT(9)    + \
 548          IP27C_R10000_ODSC(0)    + \
 549          IP27C_R10000_ODSYS(1)   + \
 550          IP27C_R10000_CTM(0))
 551 #define CONFIG_FREQ_CPU IP27C_MHZ(400)
 552 #define CONFIG_FREQ_HUB IP27C_MHZ(200)
 553 #define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
 554 #define CONFIG_MACH_TYPE SN1_MACH_TYPE
 555 #define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
 556 #endif /* IP27_CONFIG_SN1_1MB_200_400_200 */
 557
 558 #ifdef IP27_CONFIG_SN1_4MB_200_400_267
 559 #define CONFIG_CPU_MODE \
 560         (IP27C_R10000_KSEG0CA(5) + \
 561          IP27C_R10000_DEVNUM(0)  + \
 562          IP27C_R10000_CPRT(0)    + \
 563          IP27C_R10000_PER(0)     + \
 564          IP27C_R10000_PRM(3)     + \
 565          IP27C_R10000_SCD(3)     + \
 566          IP27C_R10000_SCBS(1)    + \
 567          IP27C_R10000_SCCE(0)    + \
 568          IP27C_R10000_ME(1)      + \
 569          IP27C_R10000_SCS(3)     + \
 570          IP27C_R10000_SCCD(2)    + \
 571          IP27C_R10000_SCCT(0xa)  + \
 572          IP27C_R10000_ODSC(0)    + \
 573          IP27C_R10000_ODSYS(1)   + \
 574          IP27C_R10000_CTM(0))
 575 #define CONFIG_FREQ_CPU IP27C_MHZ(400)
 576 #define CONFIG_FREQ_HUB IP27C_MHZ(200)
 577 #define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
 578 #define CONFIG_MACH_TYPE SN1_MACH_TYPE
 579 #define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
 580 #endif /* IP27_CONFIG_SN1_4MB_200_400_267 */
 581
 582 #ifdef IP27_CONFIG_SN1_8MB_200_500_250
 583 #define CONFIG_CPU_MODE \
 584         (IP27C_R10000_KSEG0CA(5) + \
 585          IP27C_R10000_DEVNUM(0)  + \
 586          IP27C_R10000_CPRT(0)    + \
 587          IP27C_R10000_PER(0)     + \
 588          IP27C_R10000_PRM(3)     + \
 589          IP27C_R10000_SCD(4)     + \
 590          IP27C_R10000_SCBS(1)    + \
 591          IP27C_R10000_SCCE(0)    + \
 592          IP27C_R10000_ME(1)      + \
 593          IP27C_R10000_SCS(4)     + \
 594          IP27C_R10000_SCCD(3)    + \
 595          IP27C_R10000_DDR(1)     + \
 596          IP27C_R10000_SCCT(0xa)  + \
 597          IP27C_R10000_ODSC(0)    + \
 598          IP27C_R10000_ODSYS(1)   + \
 599          IP27C_R10000_CTM(0))
 600 #define CONFIG_FREQ_CPU IP27C_MHZ(500)
 601 #define CONFIG_FREQ_HUB IP27C_MHZ(200)
 602 #define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
 603 #define CONFIG_MACH_TYPE SN1_MACH_TYPE
 604 #define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
 605 #endif /* IP27_CONFIG_SN1_8MB_200_500_250 */
 606
 607 #ifdef IP27_CONFIG_SN1_8MB_200_400_267
 608 #define CONFIG_CPU_MODE \
 609         (IP27C_R10000_KSEG0CA(5) + \
 610          IP27C_R10000_DEVNUM(0)  + \
 611          IP27C_R10000_CPRT(0)    + \
 612          IP27C_R10000_PER(0)     + \
 613          IP27C_R10000_PRM(3)     + \
 614          IP27C_R10000_SCD(3)     + \
 615          IP27C_R10000_SCBS(1)    + \
 616          IP27C_R10000_SCCE(0)    + \
 617          IP27C_R10000_ME(1)      + \
 618          IP27C_R10000_SCS(4)     + \
 619          IP27C_R10000_SCCD(2)    + \
 620          IP27C_R10000_SCCT(0xa)  + \
 621          IP27C_R10000_ODSC(0)    + \
 622          IP27C_R10000_ODSYS(1)   + \
 623          IP27C_R10000_CTM(0))
 624 #define CONFIG_FREQ_CPU IP27C_MHZ(400)
 625 #define CONFIG_FREQ_HUB IP27C_MHZ(200)
 626 #define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
 627 #define CONFIG_MACH_TYPE SN1_MACH_TYPE
 628 #define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
 629 #endif /* IP27_CONFIG_SN1_8MB_200_400_267 */
 630
 631 #ifdef IP27_CONFIG_SN1_4MB_180_360_240
 632 #define CONFIG_CPU_MODE \
 633         (IP27C_R10000_KSEG0CA(5) + \
 634          IP27C_R10000_DEVNUM(0)  + \
 635          IP27C_R10000_CPRT(0)    + \
 636          IP27C_R10000_PER(0)     + \
 637          IP27C_R10000_PRM(3)     + \
 638          IP27C_R10000_SCD(3)     + \
 639          IP27C_R10000_SCBS(1)    + \
 640          IP27C_R10000_SCCE(0)    + \
 641          IP27C_R10000_ME(1)      + \
 642          IP27C_R10000_SCS(3)     + \
 643          IP27C_R10000_SCCD(2)    + \
 644          IP27C_R10000_SCCT(9)    + \
 645          IP27C_R10000_ODSC(0)    + \
 646          IP27C_R10000_ODSYS(1)   + \
 647          IP27C_R10000_CTM(0))
 648 #define CONFIG_FREQ_CPU IP27C_MHZ(360)
 649 #define CONFIG_FREQ_HUB IP27C_MHZ(200)
 650 #define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
 651 #define CONFIG_MACH_TYPE SN1_MACH_TYPE
 652 #define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
 653 #endif /* IP27_CONFIG_SN1_4MB_180_360_240 */
 654
 655 #endif /* __ASSEMBLY__ */
 656
 657 #endif /* _ASM_IA64_SN_SN1_IP27CONFIG_H */