1 #ifndef _ASM_IA64_SN_SN1_SYNERGY_H
2 #define _ASM_IA64_SN_SN1_SYNERGY_H
5 #include <asm/sn/hcl.h>
6 #include <asm/sn/addrs.h>
7 #include <asm/sn/intr_public.h>
11 * Definitions for the synergy asic driver
13 * These are for SGI platforms only.
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
19 * Copyright (c) 2000-2002 Silicon Graphics, Inc. All rights reserved.
23 #define SYNERGY_L4_BYTES (64UL*1024*1024)
24 #define SYNERGY_L4_WAYS 8
25 #define SYNERGY_L4_BYTES_PER_WAY (SYNERGY_L4_BYTES/SYNERGY_L4_WAYS)
26 #define SYNERGY_BLOCK_SIZE 512UL
29 #define SSPEC_BASE (0xe0000000000UL)
30 #define LB_REG_BASE (SSPEC_BASE + 0x0)
32 #define VEC_MASK3A_ADDR (0x2a0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
33 #define VEC_MASK3B_ADDR (0x2a8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
34 #define VEC_MASK3A (0x2a0)
35 #define VEC_MASK3B (0x2a8)
37 #define VEC_MASK2A_ADDR (0x2b0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
38 #define VEC_MASK2B_ADDR (0x2b8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
39 #define VEC_MASK2A (0x2b0)
40 #define VEC_MASK2B (0x2b8)
42 #define VEC_MASK1A_ADDR (0x2c0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
43 #define VEC_MASK1B_ADDR (0x2c8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
44 #define VEC_MASK1A (0x2c0)
45 #define VEC_MASK1B (0x2c8)
47 #define VEC_MASK0A_ADDR (0x2d0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
48 #define VEC_MASK0B_ADDR (0x2d8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
49 #define VEC_MASK0A (0x2d0)
50 #define VEC_MASK0B (0x2d8)
52 #define GBL_PERF_A_ADDR (0x330 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
53 #define GBL_PERF_B_ADDR (0x338 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
55 #define WRITE_LOCAL_SYNERGY_REG(addr, value) __synergy_out(addr, value)
57 #define HSPEC_SYNERGY0_0 0x04000000 /* Synergy0 Registers */
58 #define HSPEC_SYNERGY1_0 0x05000000 /* Synergy1 Registers */
59 #define HS_SYNERGY_STRIDE (HSPEC_SYNERGY1_0 - HSPEC_SYNERGY0_0)
60 #define REMOTE_HSPEC(_n, _x) (HUBREG_CAST (RREG_BASE(_n) + (_x)))
62 #define RREG_BASE(_n) (NODE_LREG_BASE(_n))
63 #define NODE_LREG_BASE(_n) (NODE_HSPEC_BASE(_n) + 0x30000000)
64 #define NODE_HSPEC_BASE(_n) (HSPEC_BASE + NODE_OFFSET(_n))
66 #define HSPEC_BASE (SYN_UNCACHED_SPACE | HSPEC_BASE_SYN)
68 #define SYN_UNCACHED_SPACE 0xc000000000000000
69 #define HSPEC_BASE_SYN 0x00000b0000000000
70 #define NODE_OFFSET(_n) (UINT64_CAST (_n) << NODE_SIZE_BITS)
71 #define NODE_SIZE_BITS 33
73 #define SYN_TAG_DISABLE_WAY (SSPEC_BASE+0xae0)
76 #define RSYN_REG_OFFSET(fsb, reg) (((fsb) ? HSPEC_SYNERGY1_0 : HSPEC_SYNERGY0_0) | (reg))
78 #define REMOTE_SYNERGY_LOAD(nasid, fsb, reg) __remote_synergy_in(nasid, fsb, reg)
79 #define REMOTE_SYNERGY_STORE(nasid, fsb, reg, val) __remote_synergy_out(nasid, fsb, reg, val)
81 static inline uint64_t
82 __remote_synergy_in(int nasid, int fsb, uint64_t reg) {
83 volatile uint64_t *addr;
85 addr = (uint64_t *)(RREG_BASE(nasid) + RSYN_REG_OFFSET(fsb, reg));
90 __remote_synergy_out(int nasid, int fsb, uint64_t reg, uint64_t value) {
91 volatile uint64_t *addr;
93 addr = (uint64_t *)(RREG_BASE(nasid) + RSYN_REG_OFFSET(fsb, (reg<<2)));
94 *(addr+0) = value >> 48;
95 *(addr+1) = value >> 32;
96 *(addr+2) = value >> 16;
101 /* XX this doesn't make a lot of sense. Which fsb? */
103 __synergy_out(unsigned long addr, unsigned long value)
105 volatile unsigned long *adr = (unsigned long *)
106 (addr | __IA64_UNCACHED_OFFSET);
112 #define READ_LOCAL_SYNERGY_REG(addr) __synergy_in(addr)
114 /* XX this doesn't make a lot of sense. Which fsb? */
115 static inline unsigned long
116 __synergy_in(unsigned long addr)
118 unsigned long ret, *adr = (unsigned long *)
119 (addr | __IA64_UNCACHED_OFFSET);
126 struct sn1_intr_action {
127 void (*handler)(int, void *, struct pt_regs *);
130 struct sn1_intr_action * next;
133 typedef struct synergy_da_s {
134 hub_intmasks_t s_intmasks;
137 struct sn1_cnode_action_list {
138 spinlock_t action_list_lock;
139 struct sn1_intr_action *action_list;
143 * ioctl cmds for node/hub/synergy/[01]/mon for synergy
144 * perf monitoring are defined in sndrv.h
147 /* multiplex the counters every 10 timer interrupts */
148 #define SYNERGY_PERF_FREQ_DEFAULT 10
150 /* macros for synergy "mon" device ioctl handler */
151 #define SYNERGY_PERF_INFO(_s, _f) (arbitrary_info_t)(((_s) << 16)|(_f))
152 #define SYNERGY_PERF_INFO_CNODE(_x) (cnodeid_t)(((uint64_t)_x) >> 16)
153 #define SYNERGY_PERF_INFO_FSB(_x) (((uint64_t)_x) & 1)
155 /* synergy perf control registers */
156 #define PERF_CNTL0_A 0xab0UL /* control A on FSB0 */
157 #define PERF_CNTL0_B 0xab8UL /* control B on FSB0 */
158 #define PERF_CNTL1_A 0xac0UL /* control A on FSB1 */
159 #define PERF_CNTL1_B 0xac8UL /* control B on FSB1 */
161 /* synergy perf counters */
162 #define PERF_CNTR0_A 0xad0UL /* counter A on FSB0 */
163 #define PERF_CNTR0_B 0xad8UL /* counter B on FSB0 */
164 #define PERF_CNTR1_A 0xaf0UL /* counter A on FSB1 */
165 #define PERF_CNTR1_B 0xaf8UL /* counter B on FSB1 */
167 /* Synergy perf data. Each nodepda keeps a list of these */
168 struct synergy_perf_s {
169 uint64_t intervals; /* count of active intervals for this event */
170 uint64_t total_intervals;/* snapshot of total intervals */
171 uint64_t modesel; /* mode and sel bits, both A and B registers */
172 struct synergy_perf_s *next; /* next in circular linked list */
173 uint64_t counts[2]; /* [0] is synergy-A counter, [1] synergy-B counter */
176 typedef struct synergy_perf_s synergy_perf_t;
178 typedef struct synergy_info_s synergy_info_t;
180 extern void synergy_perf_init(void);
181 extern void synergy_perf_update(int);
182 extern struct file_operations synergy_mon_fops;
184 #endif /* _ASM_IA64_SN_SN1_SYNERGY_H */