1 /* $Id: intr.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
9 #ifndef _ASM_IA64_SN_SN1_INTR_H
10 #define _ASM_IA64_SN_SN1_INTR_H
12 /* Subnode wildcard */
13 #define SUBNODE_ANY (-1)
15 /* Number of interrupt levels associated with each interrupt register. */
16 #define N_INTPEND_BITS 64
18 #define INT_PEND0_BASELVL 0
19 #define INT_PEND1_BASELVL 64
21 #define N_INTPENDJUNK_BITS 8
22 #define INTPENDJUNK_CLRBIT 0x80
24 #include <asm/sn/intr_public.h>
25 #include <asm/sn/driver.h>
26 #include <asm/sn/xtalk/xtalk.h>
27 #include <asm/sn/hack.h>
33 * Dispatch table entry - contains information needed to call an interrupt
36 typedef struct intr_vector_s {
37 intr_func_t iv_func; /* Interrupt handler function */
38 intr_func_t iv_prefunc; /* Interrupt handler prologue func */
39 void *iv_arg; /* Argument to pass to handler */
40 cpuid_t iv_mustruncpu; /* Where we must run. */
43 /* Interrupt information table. */
44 typedef struct intr_info_s {
45 xtalk_intr_setfunc_t ii_setfunc; /* Function to set the interrupt
46 * destination and level register.
47 * It returns 0 (success) or an
50 void *ii_cookie; /* arg passed to setfunc */
51 devfs_handle_t ii_owner_dev; /* device that owns this intr */
52 char ii_name[II_NAMELEN]; /* Name of this intr. */
53 int ii_flags; /* informational flags */
57 #define THD_CREATED 0x00000001 /*
58 * We've created a thread for this
65 #define II_UNRESERVE 0
66 #define II_RESERVE 1 /* Interrupt reserved. */
67 #define II_INUSE 2 /* Interrupt connected */
68 #define II_ERRORINT 4 /* INterrupt is an error condition */
69 #define II_THREADED 8 /* Interrupt handler is threaded. */
72 * Interrupt level wildcard
74 #define INTRCONNECT_ANYBIT (-1)
77 * This structure holds information needed both to call and to maintain
78 * interrupts. The two are in separate arrays for the locality benefits.
79 * Since there's only one set of vectors per hub chip (but more than one
80 * CPU, the lock to change the vector tables must be here rather than in
84 typedef struct intr_vecblk_s {
85 intr_vector_t vectors[N_INTPEND_BITS]; /* information needed to
86 call an intr routine. */
87 intr_info_t info[N_INTPEND_BITS]; /* information needed only
88 to maintain interrupts. */
89 spinlock_t vector_lock; /* Lock for this and the
91 splfunc_t vector_spl; /* vector_lock req'd spl */
92 int vector_state; /* Initialized to zero.
96 int vector_count; /* Number of vectors
99 int cpu_count[CPUS_PER_SUBNODE]; /* How many interrupts are
100 * connected to each CPU
102 int ithreads_enabled; /* Are interrupt threads
103 * initialized on this node.
108 /* Possible values for vector_state: */
109 #define VECTOR_UNINITED 0
110 #define VECTOR_INITED 1
113 #define hub_intrvect0 private.p_intmasks.dispatch0->vectors
114 #define hub_intrvect1 private.p_intmasks.dispatch1->vectors
115 #define hub_intrinfo0 private.p_intmasks.dispatch0->info
116 #define hub_intrinfo1 private.p_intmasks.dispatch1->info
119 * Macros to manipulate the interrupt register on the calling hub chip.
122 #define LOCAL_HUB_SEND_INTR(_level) LOCAL_HUB_S(PI_INT_PEND_MOD, \
124 #define REMOTE_HUB_PI_SEND_INTR(_hub, _sn, _level) \
125 REMOTE_HUB_PI_S((_hub), _sn, PI_INT_PEND_MOD, (0x100|(_level)))
127 #define REMOTE_CPU_SEND_INTR(_cpuid, _level) \
128 REMOTE_HUB_PI_S(cpuid_to_nasid(_cpuid), \
129 SUBNODE(cpuid_to_slice(_cpuid)), \
130 PI_INT_PEND_MOD, (0x100|(_level)))
133 * When clearing the interrupt, make sure this clear does make it
134 * to the hub. Otherwise we could end up losing interrupts.
135 * We do an uncached load of the int_pend0 register to ensure this.
138 #define LOCAL_HUB_CLR_INTR(_level) \
139 LOCAL_HUB_S(PI_INT_PEND_MOD, (_level)), \
140 LOCAL_HUB_L(PI_INT_PEND0)
141 #define REMOTE_HUB_PI_CLR_INTR(_hub, _sn, _level) \
142 REMOTE_HUB_PI_S((_hub), (_sn), PI_INT_PEND_MOD, (_level)), \
143 REMOTE_HUB_PI_L((_hub), (_sn), PI_INT_PEND0)
145 /* Special support for use by gfx driver only. Supports special gfx hub interrupt. */
146 extern void install_gfxintr(cpuid_t cpu, ilvl_t swlevel, intr_func_t intr_func, void *intr_arg);
148 void setrtvector(intr_func_t func);
153 extern void intr_block_bit(cpuid_t cpu, int bit);
154 extern void intr_unblock_bit(cpuid_t cpu, int bit);
156 #endif /* __ASSEMBLY__ */
159 * Hard-coded interrupt levels:
168 * L5 = Profiling Timer
170 * L7 = Count/Compare (T5 counters)
174 /* INT_PEND0 hard-coded bits. */
175 #ifdef DEBUG_INTR_TSTAMP
176 /* hard coded interrupt level for interrupt latency test interrupt */
177 #define CPU_INTRLAT_B 62
178 #define CPU_INTRLAT_A 61
181 /* Hardcoded bits required by software. */
182 #define MSC_MESG_INTR 9
183 #define CPU_ACTION_B 8
184 #define CPU_ACTION_A 7
186 /* These are determined by hardware: */
190 #define PG_MIG_INTR 3
193 #define RESERVED_INTR 0
195 /* INT_PEND1 hard-coded bits: */
196 #define MSC_PANIC_INTR 63
197 #define NI_ERROR_INTR 62
198 #define MD_COR_ERR_INTR 61
199 #define COR_ERR_INTR_B 60
200 #define COR_ERR_INTR_A 59
201 #define CLK_ERR_INTR 58
203 # define NACK_INT_B 57
204 # define NACK_INT_A 56
208 #define BRIDGE_ERROR_INTR 53 /* Setup by PROM to catch Bridge Errors */
210 #define IP27_INTR_0 52 /* Reserved for PROM use */
211 #define IP27_INTR_1 51 /* (do not use in Kernel) */
212 #define IP27_INTR_2 50
213 #define IP27_INTR_3 49
214 #define IP27_INTR_4 48
215 #define IP27_INTR_5 47
216 #define IP27_INTR_6 46
217 #define IP27_INTR_7 45
219 #define TLB_INTR_B 44 /* used for tlb flush random */
220 #define TLB_INTR_A 43
222 #define LLP_PFAIL_INTR_B 42 /* see ml/SN/SN0/sysctlr.c */
223 #define LLP_PFAIL_INTR_A 41
225 #define NI_BRDCAST_ERR_B 40
226 #define NI_BRDCAST_ERR_A 39
228 # define IO_ERROR_INTR 38 /* set up by prom */
229 # define DEBUG_INTR_B 37 /* used by symmon to stop all cpus */
230 # define DEBUG_INTR_A 36
232 // These aren't strictly accurate or complete. See the
233 // Synergy Spec. for details.
234 #define SGI_UART_IRQ (65)
235 #define SGI_HUB_ERROR_IRQ (182)
237 #endif /* _ASM_IA64_SN_SN1_INTR_H */