arch/ia64/sn/io/pci_bus_cvlink.c

   1 /* $Id$
   2  *
   3  * This file is subject to the terms and conditions of the GNU General Public
   4  * License.  See the file "COPYING" in the main directory of this archive
   5  * for more details.
   6  *
   7  * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
   8  */
   9
  10 #include <linux/config.h>
  11 #include <linux/init.h>
  12 #include <linux/types.h>
  13 #include <linux/pci.h>
  14 #include <linux/pci_ids.h>
  15 #include <linux/sched.h>
  16 #include <linux/ioport.h>
  17 #include <asm/sn/types.h>
  18 #include <asm/sn/hack.h>
  19 #include <asm/sn/sgi.h>
  20 #include <asm/sn/io.h>
  21 #include <asm/sn/driver.h>
  22 #include <asm/sn/iograph.h>
  23 #include <asm/param.h>
  24 #include <asm/sn/pio.h>
  25 #include <asm/sn/xtalk/xwidget.h>
  26 #include <asm/sn/sn_private.h>
  27 #include <asm/sn/addrs.h>
  28 #include <asm/sn/invent.h>
  29 #include <asm/sn/hcl.h>
  30 #include <asm/sn/hcl_util.h>
  31 #include <asm/sn/intr.h>
  32 #include <asm/sn/xtalk/xtalkaddrs.h>
  33 #include <asm/sn/klconfig.h>
  34 #include <asm/sn/nodepda.h>
  35 #include <asm/sn/pci/pciio.h>
  36 #include <asm/sn/pci/pcibr.h>
  37 #include <asm/sn/pci/pcibr_private.h>
  38 #include <asm/sn/pci/pci_bus_cvlink.h>
  39 #include <asm/sn/simulator.h>
  40 #include <asm/sn/sn_cpuid.h>
  41
  42 extern int bridge_rev_b_data_check_disable;
  43
  44 devfs_handle_t busnum_to_pcibr_vhdl[MAX_PCI_XWIDGET];
  45 nasid_t busnum_to_nid[MAX_PCI_XWIDGET];
  46 void * busnum_to_atedmamaps[MAX_PCI_XWIDGET];
  47 unsigned char num_bridges;
  48 static int done_probing = 0;
  49
  50 static int pci_bus_map_create(devfs_handle_t xtalk);
  51 devfs_handle_t devfn_to_vertex(unsigned char busnum, unsigned int devfn);
  52
  53 #define SN1_IOPORTS_UNIT 256
  54 #define MAX_IOPORTS 0xffff
  55 #define MAX_IOPORTS_CHUNKS (MAX_IOPORTS / SN1_IOPORTS_UNIT)
  56 struct ioports_to_tlbs_s ioports_to_tlbs[MAX_IOPORTS_CHUNKS];
  57 unsigned long sn1_allocate_ioports(unsigned long pci_address);
  58
  59 extern void sn1_init_irq_desc(void);
  60
  61
  62
  63 /*
  64  * pci_bus_cvlink_init() - To be called once during initialization before
  65  *      SGI IO Infrastructure init is called.
  66  */
  67 void
  68 pci_bus_cvlink_init(void)
  69 {
  70         memset(busnum_to_pcibr_vhdl, 0x0, sizeof(devfs_handle_t) * MAX_PCI_XWIDGET);
  71         memset(busnum_to_nid, 0x0, sizeof(nasid_t) * MAX_PCI_XWIDGET);
  72
  73         memset(busnum_to_atedmamaps, 0x0, sizeof(void *) * MAX_PCI_XWIDGET);
  74
  75         memset(ioports_to_tlbs, 0x0, sizeof(ioports_to_tlbs));
  76
  77         num_bridges = 0;
  78 }
  79
  80 /*
  81  * pci_bus_to_vertex() - Given a logical Linux Bus Number returns the associated
  82  *      pci bus vertex from the SGI IO Infrastructure.
  83  */
  84 devfs_handle_t
  85 pci_bus_to_vertex(unsigned char busnum)
  86 {
  87
  88         devfs_handle_t  pci_bus = NULL;
  89
  90
  91         /*
  92          * First get the xwidget vertex.
  93          */
  94         pci_bus = busnum_to_pcibr_vhdl[busnum];
  95         return(pci_bus);
  96 }
  97
  98 /*
  99  * devfn_to_vertex() - returns the vertex of the device given the bus, slot,
 100  *      and function numbers.
 101  */
 102 devfs_handle_t
 103 devfn_to_vertex(unsigned char busnum, unsigned int devfn)
 104 {
 105
 106         int slot = 0;
 107         int func = 0;
 108         char    name[16];
 109         devfs_handle_t  pci_bus = NULL;
 110         devfs_handle_t  device_vertex = (devfs_handle_t)NULL;
 111
 112         /*
 113          * Go get the pci bus vertex.
 114          */
 115         pci_bus = pci_bus_to_vertex(busnum);
 116         if (!pci_bus) {
 117                 /*
 118                  * During probing, the Linux pci code invents non-existent
 119                  * bus numbers and pci_dev structures and tries to access
 120                  * them to determine existence. Don't crib during probing.
 121                  */
 122                 if (done_probing)
 123                         printk("devfn_to_vertex: Invalid bus number %d given.\n", busnum);
 124                 return(NULL);
 125         }
 126
 127
 128         /*
 129          * Go get the slot&function vertex.
 130          * Should call pciio_slot_func_to_name() when ready.
 131          */
 132         slot = PCI_SLOT(devfn);
 133         func = PCI_FUNC(devfn);
 134
 135         /*
 136          * For a NON Multi-function card the name of the device looks like:
 137          * ../pci/1, ../pci/2 ..
 138          */
 139         if (func == 0) {
 140                 sprintf(name, "%d", slot);
 141                 if (hwgraph_traverse(pci_bus, name, &device_vertex) ==
 142                         GRAPH_SUCCESS) {
 143                         if (device_vertex) {
 144                                 return(device_vertex);
 145                         }
 146                 }
 147         }
 148
 149         /*
 150          * This maybe a multifunction card.  It's names look like:
 151          * ../pci/1a, ../pci/1b, etc.
 152          */
 153         sprintf(name, "%d%c", slot, 'a'+func);
 154         if (hwgraph_traverse(pci_bus, name, &device_vertex) != GRAPH_SUCCESS) {
 155                 if (!device_vertex) {
 156                         return(NULL);
 157                 }
 158         }
 159
 160         return(device_vertex);
 161 }
 162
 163 /*
 164  * For the given device, initialize the addresses for both the Device(x) Flush
 165  * Write Buffer register and the Xbow Flush Register for the port the PCI bus
 166  * is connected.
 167  */
 168 static void
 169 set_flush_addresses(struct pci_dev *device_dev,
 170         struct sn1_device_sysdata *device_sysdata)
 171 {
 172         pciio_info_t pciio_info = pciio_info_get(device_sysdata->vhdl);
 173         pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info);
 174         pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
 175         bridge_t               *bridge = pcibr_soft->bs_base;
 176
 177         device_sysdata->dma_buf_sync = (volatile unsigned int *)
 178                 &(bridge->b_wr_req_buf[pciio_slot].reg);
 179         device_sysdata->xbow_buf_sync = (volatile unsigned int *)
 180                 XBOW_PRIO_LINKREGS_PTR(NODE_SWIN_BASE(get_nasid(), 0),
 181                 pcibr_soft->bs_xid);
 182 #ifdef DEBUG
 183
 184         printk("set_flush_addresses: dma_buf_sync %p xbow_buf_sync %p\n",
 185                 device_sysdata->dma_buf_sync, device_sysdata->xbow_buf_sync);
 186
 187         while((volatile unsigned int )*device_sysdata->dma_buf_sync);
 188         while((volatile unsigned int )*device_sysdata->xbow_buf_sync);
 189 #endif
 190
 191 }
 192
 193 /*
 194  * Most drivers currently do not properly tell the arch specific pci dma
 195  * interfaces whether they can handle A64. Here is where we privately
 196  * keep track of this.
 197  */
 198 static void __init
 199 set_sn1_pci64(struct pci_dev *dev)
 200 {
 201         unsigned short vendor = dev->vendor;
 202         unsigned short device = dev->device;
 203
 204         if (vendor == PCI_VENDOR_ID_QLOGIC) {
 205                 if ((device == PCI_DEVICE_ID_QLOGIC_ISP2100) ||
 206                                 (device == PCI_DEVICE_ID_QLOGIC_ISP2200)) {
 207                         SET_PCIA64(dev);
 208                         return;
 209                 }
 210         }
 211
 212         if (vendor == PCI_VENDOR_ID_SGI) {
 213                 if (device == PCI_DEVICE_ID_SGI_IOC3) {
 214                         SET_PCIA64(dev);
 215                         return;
 216                 }
 217         }
 218
 219 }
 220
 221 /*
 222  * sn1_allocate_ioports() - This routine provides the allocation and
 223  *      mappings between Linux style IOPORTs management.
 224  *
 225  *      For simplicity sake, SN1 will allocate IOPORTs in chunks of
 226  *      256bytes .. irrespective of what the card desires.  This may
 227  *      have to change when we understand how to deal with legacy ioports
 228  *      which are hardcoded in some drivers e.g. SVGA.
 229  *
 230  *      Ofcourse, the SN1 IO Infrastructure has no concept of IOPORT numbers.
 231  *      It will remain so.  The IO Infrastructure will continue to map
 232  *      IO Resource just like IRIX.  When this is done, we map IOPORT
 233  *      chunks to these resources.  The Linux drivers will see and use real
 234  *      IOPORT numbers.  The various IOPORT access macros e.g. inb/outb etc.
 235  *      does the munging of these IOPORT numbers to make a Uncache Virtual
 236  *      Address.  This address via the tlb entries generates the PCI Address
 237  *      allocated by the SN1 IO Infrastructure Layer.
 238  */
 239 static unsigned long sn1_ioport_num = 0x1000; /* Reserve room for Legacy stuff */
 240 unsigned long
 241 sn1_allocate_ioports(unsigned long pci_address)
 242 {
 243
 244         unsigned long ioport_index;
 245
 246         /*
 247          * Just some idiot checking ..
 248          */
 249         if ( sn1_ioport_num > 0xffff ) {
 250                 printk("sn1_allocate_ioports: No more IO PORTS available\n");
 251                 return(-1);
 252         }
 253
 254         /*
 255          * See Section 4.1.1.5 of Intel IA-64 Acrchitecture Software Developer's
 256          * Manual for details.
 257          */
 258         ioport_index = sn1_ioport_num / SN1_IOPORTS_UNIT;
 259
 260         ioports_to_tlbs[ioport_index].p = 1; /* Present Bit */
 261         ioports_to_tlbs[ioport_index].rv_1 = 0; /* 1 Bit */
 262         ioports_to_tlbs[ioport_index].ma = 4; /* Memory Attributes 3 bits*/
 263         ioports_to_tlbs[ioport_index].a = 1; /* Set Data Access Bit Fault 1 Bit*/
 264         ioports_to_tlbs[ioport_index].d = 1; /* Dirty Bit */
 265         ioports_to_tlbs[ioport_index].pl = 0;/* Privilege Level - All levels can R/W*/
 266         ioports_to_tlbs[ioport_index].ar = 3; /* Access Rights - R/W only*/
 267         ioports_to_tlbs[ioport_index].ppn = pci_address >> 12; /* 4K page size */
 268         ioports_to_tlbs[ioport_index].ed = 0; /* Exception Deferral Bit */
 269         ioports_to_tlbs[ioport_index].ig = 0; /* Ignored */
 270
 271         /* printk("sn1_allocate_ioports: ioport_index 0x%x ioports_to_tlbs 0x%p\n", ioport_index, ioports_to_tlbs[ioport_index]); */
 272
 273         sn1_ioport_num += SN1_IOPORTS_UNIT;
 274
 275         return(sn1_ioport_num - SN1_IOPORTS_UNIT);
 276 }
 277
 278 /*
 279  * sn1_pci_fixup() - This routine is called when platform_pci_fixup() is
 280  *      invoked at the end of pcibios_init() to link the Linux pci
 281  *      infrastructure to SGI IO Infrasturcture - ia64/kernel/pci.c
 282  *
 283  *      Other platform specific fixup can also be done here.
 284  */
 285 void
 286 sn1_pci_fixup(int arg)
 287 {
 288         struct list_head *ln;
 289         struct pci_bus *pci_bus = NULL;
 290         struct pci_dev *device_dev = NULL;
 291         struct sn1_widget_sysdata *widget_sysdata;
 292         struct sn1_device_sysdata *device_sysdata;
 293 #ifdef SN1_IOPORTS
 294         unsigned long ioport;
 295 #endif
 296         pciio_intr_t intr_handle;
 297         int cpuid, bit;
 298         devfs_handle_t device_vertex;
 299         pciio_intr_line_t lines;
 300         extern void sn1_pci_find_bios(void);
 301 #ifdef CONFIG_IA64_SGI_SN2
 302         extern int numnodes;
 303         int cnode;
 304 #endif /* CONFIG_IA64_SGI_SN2 */
 305
 306
 307         if (arg == 0) {
 308                 sn1_init_irq_desc();
 309                 sn1_pci_find_bios();
 310 #ifdef CONFIG_IA64_SGI_SN2
 311                 for (cnode = 0; cnode < numnodes; cnode++) {
 312                                 extern void intr_init_vecblk(nodepda_t *npda, cnodeid_t, int);
 313                                 intr_init_vecblk(NODEPDA(cnode), cnode, 0);
 314                 }
 315 #endif /* CONFIG_IA64_SGI_SN2 */
 316                 return;
 317         }
 318
 319 #if 0
 320 {
 321         devfs_handle_t  bridge_vhdl = pci_bus_to_vertex(0);
 322         pcibr_soft_t    pcibr_soft = (pcibr_soft_t) hwgraph_fastinfo_get(bridge_vhdl);
 323         bridge_t        *bridge = pcibr_soft->bs_base;
 324         printk("pci_fixup_ioc3: Before devreg fixup\n");
 325         printk("pci_fixup_ioc3: Devreg 0 0x%x\n", bridge->b_device[0].reg);
 326         printk("pci_fixup_ioc3: Devreg 1 0x%x\n", bridge->b_device[1].reg);
 327         printk("pci_fixup_ioc3: Devreg 2 0x%x\n", bridge->b_device[2].reg);
 328         printk("pci_fixup_ioc3: Devreg 3 0x%x\n", bridge->b_device[3].reg);
 329         printk("pci_fixup_ioc3: Devreg 4 0x%x\n", bridge->b_device[4].reg);
 330         printk("pci_fixup_ioc3: Devreg 5 0x%x\n", bridge->b_device[5].reg);
 331         printk("pci_fixup_ioc3: Devreg 6 0x%x\n", bridge->b_device[6].reg);
 332         printk("pci_fixup_ioc3: Devreg 7 0x%x\n", bridge->b_device[7].reg);
 333 }
 334 #endif
 335         done_probing = 1;
 336
 337         /*
 338          * Initialize the pci bus vertex in the pci_bus struct.
 339          */
 340         for( ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
 341                 pci_bus = pci_bus_b(ln);
 342                 widget_sysdata = kmalloc(sizeof(struct sn1_widget_sysdata),
 343                                         GFP_KERNEL);
 344                 widget_sysdata->vhdl = pci_bus_to_vertex(pci_bus->number);
 345                 pci_bus->sysdata = (void *)widget_sysdata;
 346         }
 347
 348         /*
 349          * set the root start and end so that drivers calling check_region()
 350          * won't see a conflict
 351          */
 352 #ifdef SN1_IOPORTS
 353         ioport_resource.start  = sn1_ioport_num;
 354         ioport_resource.end = 0xffff;
 355 #else
 356 #if defined(CONFIG_IA64_SGI_SN1)
 357         if ( IS_RUNNING_ON_SIMULATOR() ) {
 358                 /*
 359                  * IDE legacy IO PORTs are supported in Medusa.
 360                  * Just open up IO PORTs from 0 .. ioport_resource.end.
 361                  */
 362                 ioport_resource.start = 0;
 363         } else {
 364                 /*
 365                  * We do not support Legacy IO PORT numbers.
 366                  */
 367                 ioport_resource.start |= IO_SWIZ_BASE | __IA64_UNCACHED_OFFSET;
 368         }
 369         ioport_resource.end |= (HSPEC_SWIZ_BASE-1) | __IA64_UNCACHED_OFFSET;
 370 #else
 371         // Need something here for sn2.... ZXZXZX
 372 #endif
 373 #endif
 374
 375         /*
 376          * Initialize the device vertex in the pci_dev struct.
 377          */
 378         while ((device_dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, device_dev)) != NULL) {
 379                 unsigned int irq;
 380                 int idx;
 381                 u16 cmd;
 382                 devfs_handle_t vhdl;
 383                 unsigned long size;
 384                 extern int bit_pos_to_irq(int);
 385
 386                 if (device_dev->vendor == PCI_VENDOR_ID_SGI &&
 387                                 device_dev->device == PCI_DEVICE_ID_SGI_IOC3) {
 388                         extern void pci_fixup_ioc3(struct pci_dev *d);
 389                         pci_fixup_ioc3(device_dev);
 390                 }
 391
 392                 /* Set the device vertex */
 393
 394                 device_sysdata = kmalloc(sizeof(struct sn1_device_sysdata),
 395                                         GFP_KERNEL);
 396                 device_sysdata->vhdl = devfn_to_vertex(device_dev->bus->number, device_dev->devfn);
 397                 device_sysdata->isa64 = 0;
 398                 /*
 399                  * Set the xbridge Device(X) Write Buffer Flush and Xbow Flush
 400                  * register addresses.
 401                  */
 402                 (void) set_flush_addresses(device_dev, device_sysdata);
 403
 404                 device_dev->sysdata = (void *) device_sysdata;
 405                 set_sn1_pci64(device_dev);
 406                 pci_read_config_word(device_dev, PCI_COMMAND, &cmd);
 407
 408                 /*
 409                  * Set the resources address correctly.  The assumption here
 410                  * is that the addresses in the resource structure has been
 411                  * read from the card and it was set in the card by our
 412                  * Infrastructure ..
 413                  */
 414                 vhdl = device_sysdata->vhdl;
 415                 for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
 416                         size = 0;
 417                         size = device_dev->resource[idx].end -
 418                                 device_dev->resource[idx].start;
 419                         if (size) {
 420                                 device_dev->resource[idx].start = (unsigned long)pciio_pio_addr(vhdl, 0, PCIIO_SPACE_WIN(idx), 0, size, 0, PCIIO_BYTE_STREAM);
 421                                 device_dev->resource[idx].start |= __IA64_UNCACHED_OFFSET;
 422                         }
 423                         else
 424                                 continue;
 425
 426                         device_dev->resource[idx].end =
 427                                 device_dev->resource[idx].start + size;
 428
 429 #ifdef CONFIG_IA64_SGI_SN1
 430                         /*
 431                          * Adjust the addresses to go to the SWIZZLE ..
 432                          */
 433                         device_dev->resource[idx].start =
 434                                 device_dev->resource[idx].start & 0xfffff7ffffffffff;
 435                         device_dev->resource[idx].end =
 436                                 device_dev->resource[idx].end & 0xfffff7ffffffffff;
 437 #endif
 438
 439                         if (device_dev->resource[idx].flags & IORESOURCE_IO) {
 440                                 cmd |= PCI_COMMAND_IO;
 441 #ifdef SN1_IOPORTS
 442                                 ioport = sn1_allocate_ioports(device_dev->resource[idx].start);
 443                                 if (ioport < 0) {
 444                                         printk("sn1_pci_fixup: PCI Device 0x%x on PCI Bus %d not mapped to IO PORTs .. IO PORTs exhausted\n", device_dev->devfn, device_dev->bus->number);
 445                                         continue;
 446                                 }
 447                                 pciio_config_set(vhdl, (unsigned) PCI_BASE_ADDRESS_0 + (idx * 4), 4, (res + (ioport & 0xfff)));
 448
 449 printk("sn1_pci_fixup: ioport number %d mapped to pci address 0x%lx\n", ioport, (res + (ioport & 0xfff)));
 450
 451                                 device_dev->resource[idx].start = ioport;
 452                                 device_dev->resource[idx].end = ioport + SN1_IOPORTS_UNIT;
 453 #endif
 454                         }
 455                         if (device_dev->resource[idx].flags & IORESOURCE_MEM)
 456                                 cmd |= PCI_COMMAND_MEMORY;
 457                 }
 458                 /*
 459                  * Now handle the ROM resource ..
 460                  */
 461                 size = device_dev->resource[PCI_ROM_RESOURCE].end -
 462                         device_dev->resource[PCI_ROM_RESOURCE].start;
 463
 464                 if (size) {
 465                         device_dev->resource[PCI_ROM_RESOURCE].start =
 466                         (unsigned long) pciio_pio_addr(vhdl, 0, PCIIO_SPACE_ROM, 0,
 467                                 size, 0, PCIIO_BYTE_STREAM);
 468                         device_dev->resource[PCI_ROM_RESOURCE].start |= __IA64_UNCACHED_OFFSET;
 469                         device_dev->resource[PCI_ROM_RESOURCE].end =
 470                         device_dev->resource[PCI_ROM_RESOURCE].start + size;
 471
 472 #ifdef CONFIG_IA64_SGI_SN1
 473                         /*
 474                          * go through synergy swizzled space
 475                          */
 476                         device_dev->resource[PCI_ROM_RESOURCE].start &= 0xfffff7ffffffffffUL;
 477                         device_dev->resource[PCI_ROM_RESOURCE].end   &= 0xfffff7ffffffffffUL;
 478 #endif
 479
 480                 }
 481
 482                 /*
 483                  * Update the Command Word on the Card.
 484                  */
 485                 cmd |= PCI_COMMAND_MASTER; /* If the device doesn't support */
 486                                            /* bit gets dropped .. no harm */
 487                 pci_write_config_word(device_dev, PCI_COMMAND, cmd);
 488
 489                 pci_read_config_byte(device_dev, PCI_INTERRUPT_PIN, (unsigned char *)&lines);
 490                 if (device_dev->vendor == PCI_VENDOR_ID_SGI &&
 491                         device_dev->device == PCI_DEVICE_ID_SGI_IOC3 ) {
 492                                 lines = 1;
 493                 }
 494
 495                 device_sysdata = (struct sn1_device_sysdata *)device_dev->sysdata;
 496                 device_vertex = device_sysdata->vhdl;
 497
 498                 intr_handle = pciio_intr_alloc(device_vertex, NULL, lines, device_vertex);
 499
 500                 bit = intr_handle->pi_irq;
 501                 cpuid = intr_handle->pi_cpu;
 502 #ifdef CONFIG_IA64_SGI_SN1
 503                 irq = bit_pos_to_irq(bit);
 504 #else /* SN2 */
 505                 irq = bit;
 506 #endif
 507                 irq = irq + (cpuid << 8);
 508                 pciio_intr_connect(intr_handle);
 509                 device_dev->irq = irq;
 510 #ifdef ajmtestintr
 511                 {
 512                         int slot = PCI_SLOT(device_dev->devfn);
 513                         static int timer_set = 0;
 514                         pcibr_intr_t    pcibr_intr = (pcibr_intr_t)intr_handle;
 515                         pcibr_soft_t    pcibr_soft = pcibr_intr->bi_soft;
 516                         extern void intr_test_handle_intr(int, void*, struct pt_regs *);
 517
 518                         if (!timer_set) {
 519                                 intr_test_set_timer();
 520                                 timer_set = 1;
 521                         }
 522                         intr_test_register_irq(irq, pcibr_soft, slot);
 523                         request_irq(irq, intr_test_handle_intr,0,NULL, NULL);
 524                 }
 525 #endif
 526
 527         }
 528
 529 #if 0
 530
 531 {
 532         devfs_handle_t  bridge_vhdl = pci_bus_to_vertex(0);
 533         pcibr_soft_t    pcibr_soft = (pcibr_soft_t) hwgraph_fastinfo_get(bridge_vhdl);
 534         bridge_t        *bridge = pcibr_soft->bs_base;
 535
 536         printk("pci_fixup_ioc3: Before devreg fixup\n");
 537         printk("pci_fixup_ioc3: Devreg 0 0x%x\n", bridge->b_device[0].reg);
 538         printk("pci_fixup_ioc3: Devreg 1 0x%x\n", bridge->b_device[1].reg);
 539         printk("pci_fixup_ioc3: Devreg 2 0x%x\n", bridge->b_device[2].reg);
 540         printk("pci_fixup_ioc3: Devreg 3 0x%x\n", bridge->b_device[3].reg);
 541         printk("pci_fixup_ioc3: Devreg 4 0x%x\n", bridge->b_device[4].reg);
 542         printk("pci_fixup_ioc3: Devreg 5 0x%x\n", bridge->b_device[5].reg);
 543         printk("pci_fixup_ioc3: Devreg 6 0x%x\n", bridge->b_device[6].reg);
 544         printk("pci_fixup_ioc3: Devreg 7 0x%x\n", bridge->b_device[7].reg);
 545 }
 546
 547 printk("testing Big Window: 0xC0000200c0000000 %p\n", *( (volatile uint64_t *)0xc0000200a0000000));
 548 printk("testing Big Window: 0xC0000200c0000008 %p\n", *( (volatile uint64_t *)0xc0000200a0000008));
 549
 550 #endif
 551
 552 }
 553
 554 /*
 555  * pci_bus_map_create() - Called by pci_bus_to_hcl_cvlink() to finish the job.
 556  *
 557  *      Linux PCI Bus numbers are assigned from lowest module_id numbers
 558  *      (rack/slot etc.) starting from HUB_WIDGET_ID_MAX down to
 559  *      HUB_WIDGET_ID_MIN:
 560  *              widgetnum 15 gets lower Bus Number than widgetnum 14 etc.
 561  *
 562  *      Given 2 modules 001c01 and 001c02 we get the following mappings:
 563  *              001c01, widgetnum 15 = Bus number 0
 564  *              001c01, widgetnum 14 = Bus number 1
 565  *              001c02, widgetnum 15 = Bus number 3
 566  *              001c02, widgetnum 14 = Bus number 4
 567  *              etc.
 568  *
 569  * The rational for starting Bus Number 0 with Widget number 15 is because
 570  * the system boot disks are always connected via Widget 15 Slot 0 of the
 571  * I-brick.  Linux creates /dev/sd* devices(naming) strating from Bus Number 0
 572  * Therefore, /dev/sda1 will be the first disk, on Widget 15 of the lowest
 573  * module id(Master Cnode) of the system.
 574  *
 575  */
 576 static int
 577 pci_bus_map_create(devfs_handle_t xtalk)
 578 {
 579
 580         devfs_handle_t master_node_vertex = NULL;
 581         devfs_handle_t xwidget = NULL;
 582         devfs_handle_t pci_bus = NULL;
 583         hubinfo_t hubinfo = NULL;
 584         xwidgetnum_t widgetnum;
 585         char pathname[128];
 586         graph_error_t rv;
 587
 588         /*
 589          * Loop throught this vertex and get the Xwidgets ..
 590          */
 591         for (widgetnum = HUB_WIDGET_ID_MAX; widgetnum >= HUB_WIDGET_ID_MIN; widgetnum--) {
 592 #if 0
 593         {
 594                 int pos;
 595                 char dname[256];
 596                 pos = devfs_generate_path(xtalk, dname, 256);
 597                 printk("%s : path= %s\n", __FUNCTION__, &dname[pos]);
 598         }
 599 #endif
 600
 601                 sprintf(pathname, "%d", widgetnum);
 602                 xwidget = NULL;
 603
 604                 /*
 605                  * Example - /hw/module/001c16/Pbrick/xtalk/8 is the xwidget
 606                  *           /hw/module/001c16/Pbrick/xtalk/8/pci/1 is device
 607                  */
 608                 rv = hwgraph_traverse(xtalk, pathname, &xwidget);
 609                 if ( (rv != GRAPH_SUCCESS) ) {
 610                         if (!xwidget)
 611                                 continue;
 612                 }
 613
 614                 sprintf(pathname, "%d/"EDGE_LBL_PCI, widgetnum);
 615                 pci_bus = NULL;
 616                 if (hwgraph_traverse(xtalk, pathname, &pci_bus) != GRAPH_SUCCESS)
 617                         if (!pci_bus)
 618                                 continue;
 619
 620                 /*
 621                  * Assign the correct bus number and also the nasid of this
 622                  * pci Xwidget.
 623                  *
 624                  * Should not be any race here ...
 625                  */
 626                 num_bridges++;
 627                 busnum_to_pcibr_vhdl[num_bridges - 1] = pci_bus;
 628
 629                 /*
 630                  * Get the master node and from there get the NASID.
 631                  */
 632                 master_node_vertex = device_master_get(xwidget);
 633                 if (!master_node_vertex) {
 634                         printk("WARNING: pci_bus_map_create: Unable to get .master for vertex 0x%p\n", (void *)xwidget);
 635                 }
 636
 637                 hubinfo_get(master_node_vertex, &hubinfo);
 638                 if (!hubinfo) {
 639                         printk("WARNING: pci_bus_map_create: Unable to get hubinfo for master node vertex 0x%p\n", (void *)master_node_vertex);
 640                         return(1);
 641                 } else {
 642                         busnum_to_nid[num_bridges - 1] = hubinfo->h_nasid;
 643                 }
 644
 645                 /*
 646                  * Pre assign DMA maps needed for 32 Bits Page Map DMA.
 647                  */
 648                 busnum_to_atedmamaps[num_bridges - 1] = (void *) kmalloc(
 649                         sizeof(struct sn1_dma_maps_s) * MAX_ATE_MAPS, GFP_KERNEL);
 650                 if (!busnum_to_atedmamaps[num_bridges - 1])
 651                         printk("WARNING: pci_bus_map_create: Unable to precreate ATE DMA Maps for busnum %d vertex 0x%p\n", num_bridges - 1, (void *)xwidget);
 652
 653                 memset(busnum_to_atedmamaps[num_bridges - 1], 0x0,
 654                         sizeof(struct sn1_dma_maps_s) * MAX_ATE_MAPS);
 655
 656         }
 657
 658         return(0);
 659 }
 660
 661 /*
 662  * pci_bus_to_hcl_cvlink() - This routine is called after SGI IO Infrastructure
 663  *      initialization has completed to set up the mappings between Xbridge
 664  *      and logical pci bus numbers.  We also set up the NASID for each of these
 665  *      xbridges.
 666  *
 667  *      Must be called before pci_init() is invoked.
 668  */
 669 int
 670 pci_bus_to_hcl_cvlink(void)
 671 {
 672
 673         devfs_handle_t devfs_hdl = NULL;
 674         devfs_handle_t xtalk = NULL;
 675         int rv = 0;
 676         char name[256];
 677         int master_iobrick;
 678         int i;
 679
 680         /*
 681          * Iterate throught each xtalk links in the system ..
 682          * /hw/module/001c01/node/xtalk/ 8|9|10|11|12|13|14|15
 683          *
 684          * /hw/module/001c01/node/xtalk/15 -> /hw/module/001c01/Ibrick/xtalk/15
 685          *
 686          * What if it is not pci?
 687          */
 688         devfs_hdl = hwgraph_path_to_vertex("/dev/hw/module");
 689
 690         /*
 691          * To provide consistent(not persistent) device naming, we need to start
 692          * bus number allocation from the C-Brick with the lowest module id e.g. 001c01
 693          * with an attached I-Brick.  Find the master_iobrick.
 694          */
 695         master_iobrick = -1;
 696         for (i = 0; i < nummodules; i++) {
 697                 moduleid_t iobrick_id;
 698                 iobrick_id = iobrick_module_get(&modules[i]->elsc);
 699                 if (iobrick_id > 0) { /* Valid module id */
 700                         if (MODULE_GET_BTYPE(iobrick_id) == MODULE_IBRICK) {
 701                                 master_iobrick = i;
 702                                 break;
 703                         }
 704                 }
 705         }
 706
 707         /*
 708          * The master_iobrick gets bus 0 and 1.
 709          */
 710         if (master_iobrick >= 0) {
 711                 memset(name, 0, 256);
 712                 format_module_id(name, modules[master_iobrick]->id, MODULE_FORMAT_BRIEF);
 713                 strcat(name, "/node/xtalk");
 714                 xtalk = NULL;
 715                 rv = hwgraph_edge_get(devfs_hdl, name, &xtalk);
 716                 pci_bus_map_create(xtalk);
 717         }
 718
 719         /*
 720          * Now go do the rest of the modules, starting from the C-Brick with the lowest
 721          * module id, remembering to skip the master_iobrick, which was done above.
 722          */
 723         for (i = 0; i < nummodules; i++) {
 724                 if (i == master_iobrick) {
 725                         continue; /* Did the master_iobrick already. */
 726                 }
 727
 728                 memset(name, 0, 256);
 729                 format_module_id(name, modules[i]->id, MODULE_FORMAT_BRIEF);
 730                 strcat(name, "/node/xtalk");
 731                 xtalk = NULL;
 732                 rv = hwgraph_edge_get(devfs_hdl, name, &xtalk);
 733                 pci_bus_map_create(xtalk);
 734         }
 735
 736         return(0);
 737 }