drivers/tty/serial/8250/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/8250_pci.h>
  22 #include <linux/bitops.h>
  23
  24 #include <asm/byteorder.h>
  25 #include <asm/io.h>
  26
  27 #include "8250.h"
  28
  29 #undef SERIAL_DEBUG_PCI
  30
  31 /*
  32  * init function returns:
  33  *  > 0 - number of ports
  34  *  = 0 - use board->num_ports
  35  *  < 0 - error
  36  */
  37 struct pci_serial_quirk {
  38         u32     vendor;
  39         u32     device;
  40         u32     subvendor;
  41         u32     subdevice;
  42         int     (*probe)(struct pci_dev *dev);
  43         int     (*init)(struct pci_dev *dev);
  44         int     (*setup)(struct serial_private *,
  45                          const struct pciserial_board *,
  46                          struct uart_port *, int);
  47         void    (*exit)(struct pci_dev *dev);
  48 };
  49
  50 #define PCI_NUM_BAR_RESOURCES   6
  51
  52 struct serial_private {
  53         struct pci_dev          *dev;
  54         unsigned int            nr;
  55         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  56         struct pci_serial_quirk *quirk;
  57         int                     line[0];
  58 };
  59
  60 static int pci_default_setup(struct serial_private*,
  61           const struct pciserial_board*, struct uart_port*, int);
  62
  63 static void moan_device(const char *str, struct pci_dev *dev)
  64 {
  65         printk(KERN_WARNING
  66                "%s: %s\n"
  67                "Please send the output of lspci -vv, this\n"
  68                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  69                "manufacturer and name of serial board or\n"
  70                "modem board to rmk+serial@arm.linux.org.uk.\n",
  71                pci_name(dev), str, dev->vendor, dev->device,
  72                dev->subsystem_vendor, dev->subsystem_device);
  73 }
  74
  75 static int
  76 setup_port(struct serial_private *priv, struct uart_port *port,
  77            int bar, int offset, int regshift)
  78 {
  79         struct pci_dev *dev = priv->dev;
  80         unsigned long base, len;
  81
  82         if (bar >= PCI_NUM_BAR_RESOURCES)
  83                 return -EINVAL;
  84
  85         base = pci_resource_start(dev, bar);
  86
  87         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  88                 len =  pci_resource_len(dev, bar);
  89
  90                 if (!priv->remapped_bar[bar])
  91                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  92                 if (!priv->remapped_bar[bar])
  93                         return -ENOMEM;
  94
  95                 port->iotype = UPIO_MEM;
  96                 port->iobase = 0;
  97                 port->mapbase = base + offset;
  98                 port->membase = priv->remapped_bar[bar] + offset;
  99                 port->regshift = regshift;
 100         } else {
 101                 port->iotype = UPIO_PORT;
 102                 port->iobase = base + offset;
 103                 port->mapbase = 0;
 104                 port->membase = NULL;
 105                 port->regshift = 0;
 106         }
 107         return 0;
 108 }
 109
 110 /*
 111  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 112  */
 113 static int addidata_apci7800_setup(struct serial_private *priv,
 114                                 const struct pciserial_board *board,
 115                                 struct uart_port *port, int idx)
 116 {
 117         unsigned int bar = 0, offset = board->first_offset;
 118         bar = FL_GET_BASE(board->flags);
 119
 120         if (idx < 2) {
 121                 offset += idx * board->uart_offset;
 122         } else if ((idx >= 2) && (idx < 4)) {
 123                 bar += 1;
 124                 offset += ((idx - 2) * board->uart_offset);
 125         } else if ((idx >= 4) && (idx < 6)) {
 126                 bar += 2;
 127                 offset += ((idx - 4) * board->uart_offset);
 128         } else if (idx >= 6) {
 129                 bar += 3;
 130                 offset += ((idx - 6) * board->uart_offset);
 131         }
 132
 133         return setup_port(priv, port, bar, offset, board->reg_shift);
 134 }
 135
 136 /*
 137  * AFAVLAB uses a different mixture of BARs and offsets
 138  * Not that ugly ;) -- HW
 139  */
 140 static int
 141 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 142               struct uart_port *port, int idx)
 143 {
 144         unsigned int bar, offset = board->first_offset;
 145
 146         bar = FL_GET_BASE(board->flags);
 147         if (idx < 4)
 148                 bar += idx;
 149         else {
 150                 bar = 4;
 151                 offset += (idx - 4) * board->uart_offset;
 152         }
 153
 154         return setup_port(priv, port, bar, offset, board->reg_shift);
 155 }
 156
 157 /*
 158  * HP's Remote Management Console.  The Diva chip came in several
 159  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 160  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 161  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 162  * one Diva chip, but it has been expanded to 5 UARTs.
 163  */
 164 static int pci_hp_diva_init(struct pci_dev *dev)
 165 {
 166         int rc = 0;
 167
 168         switch (dev->subsystem_device) {
 169         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 170         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 171         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 172         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 173                 rc = 3;
 174                 break;
 175         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 176                 rc = 2;
 177                 break;
 178         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 179                 rc = 4;
 180                 break;
 181         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 182         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 183                 rc = 1;
 184                 break;
 185         }
 186
 187         return rc;
 188 }
 189
 190 /*
 191  * HP's Diva chip puts the 4th/5th serial port further out, and
 192  * some serial ports are supposed to be hidden on certain models.
 193  */
 194 static int
 195 pci_hp_diva_setup(struct serial_private *priv,
 196                 const struct pciserial_board *board,
 197                 struct uart_port *port, int idx)
 198 {
 199         unsigned int offset = board->first_offset;
 200         unsigned int bar = FL_GET_BASE(board->flags);
 201
 202         switch (priv->dev->subsystem_device) {
 203         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 204                 if (idx == 3)
 205                         idx++;
 206                 break;
 207         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 208                 if (idx > 0)
 209                         idx++;
 210                 if (idx > 2)
 211                         idx++;
 212                 break;
 213         }
 214         if (idx > 2)
 215                 offset = 0x18;
 216
 217         offset += idx * board->uart_offset;
 218
 219         return setup_port(priv, port, bar, offset, board->reg_shift);
 220 }
 221
 222 /*
 223  * Added for EKF Intel i960 serial boards
 224  */
 225 static int pci_inteli960ni_init(struct pci_dev *dev)
 226 {
 227         unsigned long oldval;
 228
 229         if (!(dev->subsystem_device & 0x1000))
 230                 return -ENODEV;
 231
 232         /* is firmware started? */
 233         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 234         if (oldval == 0x00001000L) { /* RESET value */
 235                 printk(KERN_DEBUG "Local i960 firmware missing");
 236                 return -ENODEV;
 237         }
 238         return 0;
 239 }
 240
 241 /*
 242  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 243  * that the card interrupt be explicitly enabled or disabled.  This
 244  * seems to be mainly needed on card using the PLX which also use I/O
 245  * mapped memory.
 246  */
 247 static int pci_plx9050_init(struct pci_dev *dev)
 248 {
 249         u8 irq_config;
 250         void __iomem *p;
 251
 252         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 253                 moan_device("no memory in bar 0", dev);
 254                 return 0;
 255         }
 256
 257         irq_config = 0x41;
 258         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 259             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 260                 irq_config = 0x43;
 261
 262         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 263             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 264                 /*
 265                  * As the megawolf cards have the int pins active
 266                  * high, and have 2 UART chips, both ints must be
 267                  * enabled on the 9050. Also, the UARTS are set in
 268                  * 16450 mode by default, so we have to enable the
 269                  * 16C950 'enhanced' mode so that we can use the
 270                  * deep FIFOs
 271                  */
 272                 irq_config = 0x5b;
 273         /*
 274          * enable/disable interrupts
 275          */
 276         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 277         if (p == NULL)
 278                 return -ENOMEM;
 279         writel(irq_config, p + 0x4c);
 280
 281         /*
 282          * Read the register back to ensure that it took effect.
 283          */
 284         readl(p + 0x4c);
 285         iounmap(p);
 286
 287         return 0;
 288 }
 289
 290 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 291 {
 292         u8 __iomem *p;
 293
 294         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 295                 return;
 296
 297         /*
 298          * disable interrupts
 299          */
 300         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 301         if (p != NULL) {
 302                 writel(0, p + 0x4c);
 303
 304                 /*
 305                  * Read the register back to ensure that it took effect.
 306                  */
 307                 readl(p + 0x4c);
 308                 iounmap(p);
 309         }
 310 }
 311
 312 #define NI8420_INT_ENABLE_REG   0x38
 313 #define NI8420_INT_ENABLE_BIT   0x2000
 314
 315 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
 316 {
 317         void __iomem *p;
 318         unsigned long base, len;
 319         unsigned int bar = 0;
 320
 321         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 322                 moan_device("no memory in bar", dev);
 323                 return;
 324         }
 325
 326         base = pci_resource_start(dev, bar);
 327         len =  pci_resource_len(dev, bar);
 328         p = ioremap_nocache(base, len);
 329         if (p == NULL)
 330                 return;
 331
 332         /* Disable the CPU Interrupt */
 333         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 334                p + NI8420_INT_ENABLE_REG);
 335         iounmap(p);
 336 }
 337
 338
 339 /* MITE registers */
 340 #define MITE_IOWBSR1    0xc4
 341 #define MITE_IOWCR1     0xf4
 342 #define MITE_LCIMR1     0x08
 343 #define MITE_LCIMR2     0x10
 344
 345 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 346
 347 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
 348 {
 349         void __iomem *p;
 350         unsigned long base, len;
 351         unsigned int bar = 0;
 352
 353         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 354                 moan_device("no memory in bar", dev);
 355                 return;
 356         }
 357
 358         base = pci_resource_start(dev, bar);
 359         len =  pci_resource_len(dev, bar);
 360         p = ioremap_nocache(base, len);
 361         if (p == NULL)
 362                 return;
 363
 364         /* Disable the CPU Interrupt */
 365         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 366         iounmap(p);
 367 }
 368
 369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 370 static int
 371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 372                 struct uart_port *port, int idx)
 373 {
 374         unsigned int bar, offset = board->first_offset;
 375
 376         bar = 0;
 377
 378         if (idx < 4) {
 379                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 380                 offset += idx * board->uart_offset;
 381         } else if (idx < 8) {
 382                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 383                 offset += idx * board->uart_offset + 0xC00;
 384         } else /* we have only 8 ports on PMC-OCTALPRO */
 385                 return 1;
 386
 387         return setup_port(priv, port, bar, offset, board->reg_shift);
 388 }
 389
 390 /*
 391 * This does initialization for PMC OCTALPRO cards:
 392 * maps the device memory, resets the UARTs (needed, bc
 393 * if the module is removed and inserted again, the card
 394 * is in the sleep mode) and enables global interrupt.
 395 */
 396
 397 /* global control register offset for SBS PMC-OctalPro */
 398 #define OCT_REG_CR_OFF          0x500
 399
 400 static int sbs_init(struct pci_dev *dev)
 401 {
 402         u8 __iomem *p;
 403
 404         p = pci_ioremap_bar(dev, 0);
 405
 406         if (p == NULL)
 407                 return -ENOMEM;
 408         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 409         writeb(0x10, p + OCT_REG_CR_OFF);
 410         udelay(50);
 411         writeb(0x0, p + OCT_REG_CR_OFF);
 412
 413         /* Set bit-2 (INTENABLE) of Control Register */
 414         writeb(0x4, p + OCT_REG_CR_OFF);
 415         iounmap(p);
 416
 417         return 0;
 418 }
 419
 420 /*
 421  * Disables the global interrupt of PMC-OctalPro
 422  */
 423
 424 static void __devexit sbs_exit(struct pci_dev *dev)
 425 {
 426         u8 __iomem *p;
 427
 428         p = pci_ioremap_bar(dev, 0);
 429         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 430         if (p != NULL)
 431                 writeb(0, p + OCT_REG_CR_OFF);
 432         iounmap(p);
 433 }
 434
 435 /*
 436  * SIIG serial cards have an PCI interface chip which also controls
 437  * the UART clocking frequency. Each UART can be clocked independently
 438  * (except cards equipped with 4 UARTs) and initial clocking settings
 439  * are stored in the EEPROM chip. It can cause problems because this
 440  * version of serial driver doesn't support differently clocked UART's
 441  * on single PCI card. To prevent this, initialization functions set
 442  * high frequency clocking for all UART's on given card. It is safe (I
 443  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 444  * with other OSes (like M$ DOS).
 445  *
 446  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 447  *
 448  * There is two family of SIIG serial cards with different PCI
 449  * interface chip and different configuration methods:
 450  *     - 10x cards have control registers in IO and/or memory space;
 451  *     - 20x cards have control registers in standard PCI configuration space.
 452  *
 453  * Note: all 10x cards have PCI device ids 0x10..
 454  *       all 20x cards have PCI device ids 0x20..
 455  *
 456  * There are also Quartet Serial cards which use Oxford Semiconductor
 457  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 458  *
 459  * Note: some SIIG cards are probed by the parport_serial object.
 460  */
 461
 462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 464
 465 static int pci_siig10x_init(struct pci_dev *dev)
 466 {
 467         u16 data;
 468         void __iomem *p;
 469
 470         switch (dev->device & 0xfff8) {
 471         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 472                 data = 0xffdf;
 473                 break;
 474         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 475                 data = 0xf7ff;
 476                 break;
 477         default:                        /* 1S1P, 4S */
 478                 data = 0xfffb;
 479                 break;
 480         }
 481
 482         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 483         if (p == NULL)
 484                 return -ENOMEM;
 485
 486         writew(readw(p + 0x28) & data, p + 0x28);
 487         readw(p + 0x28);
 488         iounmap(p);
 489         return 0;
 490 }
 491
 492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 494
 495 static int pci_siig20x_init(struct pci_dev *dev)
 496 {
 497         u8 data;
 498
 499         /* Change clock frequency for the first UART. */
 500         pci_read_config_byte(dev, 0x6f, &data);
 501         pci_write_config_byte(dev, 0x6f, data & 0xef);
 502
 503         /* If this card has 2 UART, we have to do the same with second UART. */
 504         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 505             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 506                 pci_read_config_byte(dev, 0x73, &data);
 507                 pci_write_config_byte(dev, 0x73, data & 0xef);
 508         }
 509         return 0;
 510 }
 511
 512 static int pci_siig_init(struct pci_dev *dev)
 513 {
 514         unsigned int type = dev->device & 0xff00;
 515
 516         if (type == 0x1000)
 517                 return pci_siig10x_init(dev);
 518         else if (type == 0x2000)
 519                 return pci_siig20x_init(dev);
 520
 521         moan_device("Unknown SIIG card", dev);
 522         return -ENODEV;
 523 }
 524
 525 static int pci_siig_setup(struct serial_private *priv,
 526                           const struct pciserial_board *board,
 527                           struct uart_port *port, int idx)
 528 {
 529         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 530
 531         if (idx > 3) {
 532                 bar = 4;
 533                 offset = (idx - 4) * 8;
 534         }
 535
 536         return setup_port(priv, port, bar, offset, 0);
 537 }
 538
 539 /*
 540  * Timedia has an explosion of boards, and to avoid the PCI table from
 541  * growing *huge*, we use this function to collapse some 70 entries
 542  * in the PCI table into one, for sanity's and compactness's sake.
 543  */
 544 static const unsigned short timedia_single_port[] = {
 545         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 546 };
 547
 548 static const unsigned short timedia_dual_port[] = {
 549         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 550         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 551         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 552         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 553         0xD079, 0
 554 };
 555
 556 static const unsigned short timedia_quad_port[] = {
 557         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 558         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 559         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 560         0xB157, 0
 561 };
 562
 563 static const unsigned short timedia_eight_port[] = {
 564         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 565         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 566 };
 567
 568 static const struct timedia_struct {
 569         int num;
 570         const unsigned short *ids;
 571 } timedia_data[] = {
 572         { 1, timedia_single_port },
 573         { 2, timedia_dual_port },
 574         { 4, timedia_quad_port },
 575         { 8, timedia_eight_port }
 576 };
 577
 578 /*
 579  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 580  * listing them individually, this driver merely grabs them all with
 581  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 582  * and should be left free to be claimed by parport_serial instead.
 583  */
 584 static int pci_timedia_probe(struct pci_dev *dev)
 585 {
 586         /*
 587          * Check the third digit of the subdevice ID
 588          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 589          */
 590         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 591                 dev_info(&dev->dev,
 592                         "ignoring Timedia subdevice %04x for parport_serial\n",
 593                         dev->subsystem_device);
 594                 return -ENODEV;
 595         }
 596
 597         return 0;
 598 }
 599
 600 static int pci_timedia_init(struct pci_dev *dev)
 601 {
 602         const unsigned short *ids;
 603         int i, j;
 604
 605         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 606                 ids = timedia_data[i].ids;
 607                 for (j = 0; ids[j]; j++)
 608                         if (dev->subsystem_device == ids[j])
 609                                 return timedia_data[i].num;
 610         }
 611         return 0;
 612 }
 613
 614 /*
 615  * Timedia/SUNIX uses a mixture of BARs and offsets
 616  * Ugh, this is ugly as all hell --- TYT
 617  */
 618 static int
 619 pci_timedia_setup(struct serial_private *priv,
 620                   const struct pciserial_board *board,
 621                   struct uart_port *port, int idx)
 622 {
 623         unsigned int bar = 0, offset = board->first_offset;
 624
 625         switch (idx) {
 626         case 0:
 627                 bar = 0;
 628                 break;
 629         case 1:
 630                 offset = board->uart_offset;
 631                 bar = 0;
 632                 break;
 633         case 2:
 634                 bar = 1;
 635                 break;
 636         case 3:
 637                 offset = board->uart_offset;
 638                 /* FALLTHROUGH */
 639         case 4: /* BAR 2 */
 640         case 5: /* BAR 3 */
 641         case 6: /* BAR 4 */
 642         case 7: /* BAR 5 */
 643                 bar = idx - 2;
 644         }
 645
 646         return setup_port(priv, port, bar, offset, board->reg_shift);
 647 }
 648
 649 /*
 650  * Some Titan cards are also a little weird
 651  */
 652 static int
 653 titan_400l_800l_setup(struct serial_private *priv,
 654                       const struct pciserial_board *board,
 655                       struct uart_port *port, int idx)
 656 {
 657         unsigned int bar, offset = board->first_offset;
 658
 659         switch (idx) {
 660         case 0:
 661                 bar = 1;
 662                 break;
 663         case 1:
 664                 bar = 2;
 665                 break;
 666         default:
 667                 bar = 4;
 668                 offset = (idx - 2) * board->uart_offset;
 669         }
 670
 671         return setup_port(priv, port, bar, offset, board->reg_shift);
 672 }
 673
 674 static int pci_xircom_init(struct pci_dev *dev)
 675 {
 676         msleep(100);
 677         return 0;
 678 }
 679
 680 static int pci_ni8420_init(struct pci_dev *dev)
 681 {
 682         void __iomem *p;
 683         unsigned long base, len;
 684         unsigned int bar = 0;
 685
 686         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 687                 moan_device("no memory in bar", dev);
 688                 return 0;
 689         }
 690
 691         base = pci_resource_start(dev, bar);
 692         len =  pci_resource_len(dev, bar);
 693         p = ioremap_nocache(base, len);
 694         if (p == NULL)
 695                 return -ENOMEM;
 696
 697         /* Enable CPU Interrupt */
 698         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 699                p + NI8420_INT_ENABLE_REG);
 700
 701         iounmap(p);
 702         return 0;
 703 }
 704
 705 #define MITE_IOWBSR1_WSIZE      0xa
 706 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 707 #define MITE_IOWBSR1_WENAB      (1 << 7)
 708 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 709 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 710 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 711
 712 static int pci_ni8430_init(struct pci_dev *dev)
 713 {
 714         void __iomem *p;
 715         unsigned long base, len;
 716         u32 device_window;
 717         unsigned int bar = 0;
 718
 719         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 720                 moan_device("no memory in bar", dev);
 721                 return 0;
 722         }
 723
 724         base = pci_resource_start(dev, bar);
 725         len =  pci_resource_len(dev, bar);
 726         p = ioremap_nocache(base, len);
 727         if (p == NULL)
 728                 return -ENOMEM;
 729
 730         /* Set device window address and size in BAR0 */
 731         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 732                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 733         writel(device_window, p + MITE_IOWBSR1);
 734
 735         /* Set window access to go to RAMSEL IO address space */
 736         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 737                p + MITE_IOWCR1);
 738
 739         /* Enable IO Bus Interrupt 0 */
 740         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 741
 742         /* Enable CPU Interrupt */
 743         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 744
 745         iounmap(p);
 746         return 0;
 747 }
 748
 749 /* UART Port Control Register */
 750 #define NI8430_PORTCON  0x0f
 751 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 752
 753 static int
 754 pci_ni8430_setup(struct serial_private *priv,
 755                  const struct pciserial_board *board,
 756                  struct uart_port *port, int idx)
 757 {
 758         void __iomem *p;
 759         unsigned long base, len;
 760         unsigned int bar, offset = board->first_offset;
 761
 762         if (idx >= board->num_ports)
 763                 return 1;
 764
 765         bar = FL_GET_BASE(board->flags);
 766         offset += idx * board->uart_offset;
 767
 768         base = pci_resource_start(priv->dev, bar);
 769         len =  pci_resource_len(priv->dev, bar);
 770         p = ioremap_nocache(base, len);
 771
 772         /* enable the transceiver */
 773         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 774                p + offset + NI8430_PORTCON);
 775
 776         iounmap(p);
 777
 778         return setup_port(priv, port, bar, offset, board->reg_shift);
 779 }
 780
 781 static int pci_netmos_9900_setup(struct serial_private *priv,
 782                                 const struct pciserial_board *board,
 783                                 struct uart_port *port, int idx)
 784 {
 785         unsigned int bar;
 786
 787         if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
 788                 /* netmos apparently orders BARs by datasheet layout, so serial
 789                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 790                  */
 791                 bar = 3 * idx;
 792
 793                 return setup_port(priv, port, bar, 0, board->reg_shift);
 794         } else {
 795                 return pci_default_setup(priv, board, port, idx);
 796         }
 797 }
 798
 799 /* the 99xx series comes with a range of device IDs and a variety
 800  * of capabilities:
 801  *
 802  * 9900 has varying capabilities and can cascade to sub-controllers
 803  *   (cascading should be purely internal)
 804  * 9904 is hardwired with 4 serial ports
 805  * 9912 and 9922 are hardwired with 2 serial ports
 806  */
 807 static int pci_netmos_9900_numports(struct pci_dev *dev)
 808 {
 809         unsigned int c = dev->class;
 810         unsigned int pi;
 811         unsigned short sub_serports;
 812
 813         pi = (c & 0xff);
 814
 815         if (pi == 2) {
 816                 return 1;
 817         } else if ((pi == 0) &&
 818                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 819                 /* two possibilities: 0x30ps encodes number of parallel and
 820                  * serial ports, or 0x1000 indicates *something*. This is not
 821                  * immediately obvious, since the 2s1p+4s configuration seems
 822                  * to offer all functionality on functions 0..2, while still
 823                  * advertising the same function 3 as the 4s+2s1p config.
 824                  */
 825                 sub_serports = dev->subsystem_device & 0xf;
 826                 if (sub_serports > 0) {
 827                         return sub_serports;
 828                 } else {
 829                         printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 830                         return 0;
 831                 }
 832         }
 833
 834         moan_device("unknown NetMos/Mostech program interface", dev);
 835         return 0;
 836 }
 837
 838 static int pci_netmos_init(struct pci_dev *dev)
 839 {
 840         /* subdevice 0x00PS means <P> parallel, <S> serial */
 841         unsigned int num_serial = dev->subsystem_device & 0xf;
 842
 843         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 844                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 845                 return 0;
 846
 847         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 848                         dev->subsystem_device == 0x0299)
 849                 return 0;
 850
 851         switch (dev->device) { /* FALLTHROUGH on all */
 852                 case PCI_DEVICE_ID_NETMOS_9904:
 853                 case PCI_DEVICE_ID_NETMOS_9912:
 854                 case PCI_DEVICE_ID_NETMOS_9922:
 855                 case PCI_DEVICE_ID_NETMOS_9900:
 856                         num_serial = pci_netmos_9900_numports(dev);
 857                         break;
 858
 859                 default:
 860                         if (num_serial == 0 ) {
 861                                 moan_device("unknown NetMos/Mostech device", dev);
 862                         }
 863         }
 864
 865         if (num_serial == 0)
 866                 return -ENODEV;
 867
 868         return num_serial;
 869 }
 870
 871 /*
 872  * These chips are available with optionally one parallel port and up to
 873  * two serial ports. Unfortunately they all have the same product id.
 874  *
 875  * Basic configuration is done over a region of 32 I/O ports. The base
 876  * ioport is called INTA or INTC, depending on docs/other drivers.
 877  *
 878  * The region of the 32 I/O ports is configured in POSIO0R...
 879  */
 880
 881 /* registers */
 882 #define ITE_887x_MISCR          0x9c
 883 #define ITE_887x_INTCBAR        0x78
 884 #define ITE_887x_UARTBAR        0x7c
 885 #define ITE_887x_PS0BAR         0x10
 886 #define ITE_887x_POSIO0         0x60
 887
 888 /* I/O space size */
 889 #define ITE_887x_IOSIZE         32
 890 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 891 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 892 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 893 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 894 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 895 #define ITE_887x_POSIO_SPEED            (3 << 29)
 896 /* enable IO_Space bit */
 897 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 898
 899 static int pci_ite887x_init(struct pci_dev *dev)
 900 {
 901         /* inta_addr are the configuration addresses of the ITE */
 902         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 903                                                         0x200, 0x280, 0 };
 904         int ret, i, type;
 905         struct resource *iobase = NULL;
 906         u32 miscr, uartbar, ioport;
 907
 908         /* search for the base-ioport */
 909         i = 0;
 910         while (inta_addr[i] && iobase == NULL) {
 911                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 912                                                                 "ite887x");
 913                 if (iobase != NULL) {
 914                         /* write POSIO0R - speed | size | ioport */
 915                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 916                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 917                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 918                         /* write INTCBAR - ioport */
 919                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 920                                                                 inta_addr[i]);
 921                         ret = inb(inta_addr[i]);
 922                         if (ret != 0xff) {
 923                                 /* ioport connected */
 924                                 break;
 925                         }
 926                         release_region(iobase->start, ITE_887x_IOSIZE);
 927                         iobase = NULL;
 928                 }
 929                 i++;
 930         }
 931
 932         if (!inta_addr[i]) {
 933                 printk(KERN_ERR "ite887x: could not find iobase\n");
 934                 return -ENODEV;
 935         }
 936
 937         /* start of undocumented type checking (see parport_pc.c) */
 938         type = inb(iobase->start + 0x18) & 0x0f;
 939
 940         switch (type) {
 941         case 0x2:       /* ITE8871 (1P) */
 942         case 0xa:       /* ITE8875 (1P) */
 943                 ret = 0;
 944                 break;
 945         case 0xe:       /* ITE8872 (2S1P) */
 946                 ret = 2;
 947                 break;
 948         case 0x6:       /* ITE8873 (1S) */
 949                 ret = 1;
 950                 break;
 951         case 0x8:       /* ITE8874 (2S) */
 952                 ret = 2;
 953                 break;
 954         default:
 955                 moan_device("Unknown ITE887x", dev);
 956                 ret = -ENODEV;
 957         }
 958
 959         /* configure all serial ports */
 960         for (i = 0; i < ret; i++) {
 961                 /* read the I/O port from the device */
 962                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 963                                                                 &ioport);
 964                 ioport &= 0x0000FF00;   /* the actual base address */
 965                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 966                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 967                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 968
 969                 /* write the ioport to the UARTBAR */
 970                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 971                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 972                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 973                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 974
 975                 /* get current config */
 976                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 977                 /* disable interrupts (UARTx_Routing[3:0]) */
 978                 miscr &= ~(0xf << (12 - 4 * i));
 979                 /* activate the UART (UARTx_En) */
 980                 miscr |= 1 << (23 - i);
 981                 /* write new config with activated UART */
 982                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 983         }
 984
 985         if (ret <= 0) {
 986                 /* the device has no UARTs if we get here */
 987                 release_region(iobase->start, ITE_887x_IOSIZE);
 988         }
 989
 990         return ret;
 991 }
 992
 993 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 994 {
 995         u32 ioport;
 996         /* the ioport is bit 0-15 in POSIO0R */
 997         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 998         ioport &= 0xffff;
 999         release_region(ioport, ITE_887x_IOSIZE);
1000 }
1001
1002 /*
1003  * Oxford Semiconductor Inc.
1004  * Check that device is part of the Tornado range of devices, then determine
1005  * the number of ports available on the device.
1006  */
1007 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008 {
1009         u8 __iomem *p;
1010         unsigned long deviceID;
1011         unsigned int  number_uarts = 0;
1012
1013         /* OxSemi Tornado devices are all 0xCxxx */
1014         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015             (dev->device & 0xF000) != 0xC000)
1016                 return 0;
1017
1018         p = pci_iomap(dev, 0, 5);
1019         if (p == NULL)
1020                 return -ENOMEM;
1021
1022         deviceID = ioread32(p);
1023         /* Tornado device */
1024         if (deviceID == 0x07000200) {
1025                 number_uarts = ioread8(p + 4);
1026                 printk(KERN_DEBUG
1027                         "%d ports detected on Oxford PCI Express device\n",
1028                                                                 number_uarts);
1029         }
1030         pci_iounmap(dev, p);
1031         return number_uarts;
1032 }
1033
1034 static int
1035 pci_default_setup(struct serial_private *priv,
1036                   const struct pciserial_board *board,
1037                   struct uart_port *port, int idx)
1038 {
1039         unsigned int bar, offset = board->first_offset, maxnr;
1040
1041         bar = FL_GET_BASE(board->flags);
1042         if (board->flags & FL_BASE_BARS)
1043                 bar += idx;
1044         else
1045                 offset += idx * board->uart_offset;
1046
1047         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1048                 (board->reg_shift + 3);
1049
1050         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1051                 return 1;
1052
1053         return setup_port(priv, port, bar, offset, board->reg_shift);
1054 }
1055
1056 static int
1057 ce4100_serial_setup(struct serial_private *priv,
1058                   const struct pciserial_board *board,
1059                   struct uart_port *port, int idx)
1060 {
1061         int ret;
1062
1063         ret = setup_port(priv, port, 0, 0, board->reg_shift);
1064         port->iotype = UPIO_MEM32;
1065         port->type = PORT_XSCALE;
1066         port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1067         port->regshift = 2;
1068
1069         return ret;
1070 }
1071
1072 static int
1073 pci_omegapci_setup(struct serial_private *priv,
1074                       const struct pciserial_board *board,
1075                       struct uart_port *port, int idx)
1076 {
1077         return setup_port(priv, port, 2, idx * 8, 0);
1078 }
1079
1080 static int skip_tx_en_setup(struct serial_private *priv,
1081                         const struct pciserial_board *board,
1082                         struct uart_port *port, int idx)
1083 {
1084         port->flags |= UPF_NO_TXEN_TEST;
1085         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1086                           "[%04x:%04x] subsystem [%04x:%04x]\n",
1087                           priv->dev->vendor,
1088                           priv->dev->device,
1089                           priv->dev->subsystem_vendor,
1090                           priv->dev->subsystem_device);
1091
1092         return pci_default_setup(priv, board, port, idx);
1093 }
1094
1095 static int kt_serial_setup(struct serial_private *priv,
1096                            const struct pciserial_board *board,
1097                            struct uart_port *port, int idx)
1098 {
1099         port->flags |= UPF_IIR_ONCE;
1100         return skip_tx_en_setup(priv, board, port, idx);
1101 }
1102
1103 static int pci_eg20t_init(struct pci_dev *dev)
1104 {
1105 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1106         return -ENODEV;
1107 #else
1108         return 0;
1109 #endif
1110 }
1111
1112 static int
1113 pci_xr17c154_setup(struct serial_private *priv,
1114                   const struct pciserial_board *board,
1115                   struct uart_port *port, int idx)
1116 {
1117         port->flags |= UPF_EXAR_EFR;
1118         return pci_default_setup(priv, board, port, idx);
1119 }
1120
1121 static int try_enable_msi(struct pci_dev *dev)
1122 {
1123         /* use msi if available, but fallback to legacy otherwise */
1124         pci_enable_msi(dev);
1125         return 0;
1126 }
1127
1128 static void disable_msi(struct pci_dev *dev)
1129 {
1130         pci_disable_msi(dev);
1131 }
1132
1133 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1134 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1135 #define PCI_DEVICE_ID_OCTPRO            0x0001
1136 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1137 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1138 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1139 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1140 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1141 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1142 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1143 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1144 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1145 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1146 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1147 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1148 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1149 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1150 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1151 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1152 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1153 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1154 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1155 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1156 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1157 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1158 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1159 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1160 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1161 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1162 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1163
1164 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1165 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1166
1167 /*
1168  * Master list of serial port init/setup/exit quirks.
1169  * This does not describe the general nature of the port.
1170  * (ie, baud base, number and location of ports, etc)
1171  *
1172  * This list is ordered alphabetically by vendor then device.
1173  * Specific entries must come before more generic entries.
1174  */
1175 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1176         /*
1177         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1178         */
1179         {
1180                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1181                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1182                 .subvendor      = PCI_ANY_ID,
1183                 .subdevice      = PCI_ANY_ID,
1184                 .setup          = addidata_apci7800_setup,
1185         },
1186         /*
1187          * AFAVLAB cards - these may be called via parport_serial
1188          *  It is not clear whether this applies to all products.
1189          */
1190         {
1191                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1192                 .device         = PCI_ANY_ID,
1193                 .subvendor      = PCI_ANY_ID,
1194                 .subdevice      = PCI_ANY_ID,
1195                 .setup          = afavlab_setup,
1196         },
1197         /*
1198          * HP Diva
1199          */
1200         {
1201                 .vendor         = PCI_VENDOR_ID_HP,
1202                 .device         = PCI_DEVICE_ID_HP_DIVA,
1203                 .subvendor      = PCI_ANY_ID,
1204                 .subdevice      = PCI_ANY_ID,
1205                 .init           = pci_hp_diva_init,
1206                 .setup          = pci_hp_diva_setup,
1207         },
1208         /*
1209          * Intel
1210          */
1211         {
1212                 .vendor         = PCI_VENDOR_ID_INTEL,
1213                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1214                 .subvendor      = 0xe4bf,
1215                 .subdevice      = PCI_ANY_ID,
1216                 .init           = pci_inteli960ni_init,
1217                 .setup          = pci_default_setup,
1218         },
1219         {
1220                 .vendor         = PCI_VENDOR_ID_INTEL,
1221                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1222                 .subvendor      = PCI_ANY_ID,
1223                 .subdevice      = PCI_ANY_ID,
1224                 .setup          = skip_tx_en_setup,
1225         },
1226         {
1227                 .vendor         = PCI_VENDOR_ID_INTEL,
1228                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1229                 .subvendor      = PCI_ANY_ID,
1230                 .subdevice      = PCI_ANY_ID,
1231                 .setup          = skip_tx_en_setup,
1232         },
1233         {
1234                 .vendor         = PCI_VENDOR_ID_INTEL,
1235                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1236                 .subvendor      = PCI_ANY_ID,
1237                 .subdevice      = PCI_ANY_ID,
1238                 .setup          = skip_tx_en_setup,
1239         },
1240         {
1241                 .vendor         = PCI_VENDOR_ID_INTEL,
1242                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1243                 .subvendor      = PCI_ANY_ID,
1244                 .subdevice      = PCI_ANY_ID,
1245                 .setup          = ce4100_serial_setup,
1246         },
1247         {
1248                 .vendor         = PCI_VENDOR_ID_INTEL,
1249                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1250                 .subvendor      = PCI_ANY_ID,
1251                 .subdevice      = PCI_ANY_ID,
1252                 .init           = try_enable_msi,
1253                 .setup          = kt_serial_setup,
1254                 .exit           = disable_msi,
1255         },
1256         /*
1257          * ITE
1258          */
1259         {
1260                 .vendor         = PCI_VENDOR_ID_ITE,
1261                 .device         = PCI_DEVICE_ID_ITE_8872,
1262                 .subvendor      = PCI_ANY_ID,
1263                 .subdevice      = PCI_ANY_ID,
1264                 .init           = pci_ite887x_init,
1265                 .setup          = pci_default_setup,
1266                 .exit           = __devexit_p(pci_ite887x_exit),
1267         },
1268         /*
1269          * National Instruments
1270          */
1271         {
1272                 .vendor         = PCI_VENDOR_ID_NI,
1273                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1274                 .subvendor      = PCI_ANY_ID,
1275                 .subdevice      = PCI_ANY_ID,
1276                 .init           = pci_ni8420_init,
1277                 .setup          = pci_default_setup,
1278                 .exit           = __devexit_p(pci_ni8420_exit),
1279         },
1280         {
1281                 .vendor         = PCI_VENDOR_ID_NI,
1282                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1283                 .subvendor      = PCI_ANY_ID,
1284                 .subdevice      = PCI_ANY_ID,
1285                 .init           = pci_ni8420_init,
1286                 .setup          = pci_default_setup,
1287                 .exit           = __devexit_p(pci_ni8420_exit),
1288         },
1289         {
1290                 .vendor         = PCI_VENDOR_ID_NI,
1291                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1292                 .subvendor      = PCI_ANY_ID,
1293                 .subdevice      = PCI_ANY_ID,
1294                 .init           = pci_ni8420_init,
1295                 .setup          = pci_default_setup,
1296                 .exit           = __devexit_p(pci_ni8420_exit),
1297         },
1298         {
1299                 .vendor         = PCI_VENDOR_ID_NI,
1300                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1301                 .subvendor      = PCI_ANY_ID,
1302                 .subdevice      = PCI_ANY_ID,
1303                 .init           = pci_ni8420_init,
1304                 .setup          = pci_default_setup,
1305                 .exit           = __devexit_p(pci_ni8420_exit),
1306         },
1307         {
1308                 .vendor         = PCI_VENDOR_ID_NI,
1309                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1310                 .subvendor      = PCI_ANY_ID,
1311                 .subdevice      = PCI_ANY_ID,
1312                 .init           = pci_ni8420_init,
1313                 .setup          = pci_default_setup,
1314                 .exit           = __devexit_p(pci_ni8420_exit),
1315         },
1316         {
1317                 .vendor         = PCI_VENDOR_ID_NI,
1318                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1319                 .subvendor      = PCI_ANY_ID,
1320                 .subdevice      = PCI_ANY_ID,
1321                 .init           = pci_ni8420_init,
1322                 .setup          = pci_default_setup,
1323                 .exit           = __devexit_p(pci_ni8420_exit),
1324         },
1325         {
1326                 .vendor         = PCI_VENDOR_ID_NI,
1327                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1328                 .subvendor      = PCI_ANY_ID,
1329                 .subdevice      = PCI_ANY_ID,
1330                 .init           = pci_ni8420_init,
1331                 .setup          = pci_default_setup,
1332                 .exit           = __devexit_p(pci_ni8420_exit),
1333         },
1334         {
1335                 .vendor         = PCI_VENDOR_ID_NI,
1336                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1337                 .subvendor      = PCI_ANY_ID,
1338                 .subdevice      = PCI_ANY_ID,
1339                 .init           = pci_ni8420_init,
1340                 .setup          = pci_default_setup,
1341                 .exit           = __devexit_p(pci_ni8420_exit),
1342         },
1343         {
1344                 .vendor         = PCI_VENDOR_ID_NI,
1345                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1346                 .subvendor      = PCI_ANY_ID,
1347                 .subdevice      = PCI_ANY_ID,
1348                 .init           = pci_ni8420_init,
1349                 .setup          = pci_default_setup,
1350                 .exit           = __devexit_p(pci_ni8420_exit),
1351         },
1352         {
1353                 .vendor         = PCI_VENDOR_ID_NI,
1354                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1355                 .subvendor      = PCI_ANY_ID,
1356                 .subdevice      = PCI_ANY_ID,
1357                 .init           = pci_ni8420_init,
1358                 .setup          = pci_default_setup,
1359                 .exit           = __devexit_p(pci_ni8420_exit),
1360         },
1361         {
1362                 .vendor         = PCI_VENDOR_ID_NI,
1363                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1364                 .subvendor      = PCI_ANY_ID,
1365                 .subdevice      = PCI_ANY_ID,
1366                 .init           = pci_ni8420_init,
1367                 .setup          = pci_default_setup,
1368                 .exit           = __devexit_p(pci_ni8420_exit),
1369         },
1370         {
1371                 .vendor         = PCI_VENDOR_ID_NI,
1372                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1373                 .subvendor      = PCI_ANY_ID,
1374                 .subdevice      = PCI_ANY_ID,
1375                 .init           = pci_ni8420_init,
1376                 .setup          = pci_default_setup,
1377                 .exit           = __devexit_p(pci_ni8420_exit),
1378         },
1379         {
1380                 .vendor         = PCI_VENDOR_ID_NI,
1381                 .device         = PCI_ANY_ID,
1382                 .subvendor      = PCI_ANY_ID,
1383                 .subdevice      = PCI_ANY_ID,
1384                 .init           = pci_ni8430_init,
1385                 .setup          = pci_ni8430_setup,
1386                 .exit           = __devexit_p(pci_ni8430_exit),
1387         },
1388         /*
1389          * Panacom
1390          */
1391         {
1392                 .vendor         = PCI_VENDOR_ID_PANACOM,
1393                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1394                 .subvendor      = PCI_ANY_ID,
1395                 .subdevice      = PCI_ANY_ID,
1396                 .init           = pci_plx9050_init,
1397                 .setup          = pci_default_setup,
1398                 .exit           = __devexit_p(pci_plx9050_exit),
1399         },
1400         {
1401                 .vendor         = PCI_VENDOR_ID_PANACOM,
1402                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1403                 .subvendor      = PCI_ANY_ID,
1404                 .subdevice      = PCI_ANY_ID,
1405                 .init           = pci_plx9050_init,
1406                 .setup          = pci_default_setup,
1407                 .exit           = __devexit_p(pci_plx9050_exit),
1408         },
1409         /*
1410          * PLX
1411          */
1412         {
1413                 .vendor         = PCI_VENDOR_ID_PLX,
1414                 .device         = PCI_DEVICE_ID_PLX_9030,
1415                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1416                 .subdevice      = PCI_ANY_ID,
1417                 .setup          = pci_default_setup,
1418         },
1419         {
1420                 .vendor         = PCI_VENDOR_ID_PLX,
1421                 .device         = PCI_DEVICE_ID_PLX_9050,
1422                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1423                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1424                 .init           = pci_plx9050_init,
1425                 .setup          = pci_default_setup,
1426                 .exit           = __devexit_p(pci_plx9050_exit),
1427         },
1428         {
1429                 .vendor         = PCI_VENDOR_ID_PLX,
1430                 .device         = PCI_DEVICE_ID_PLX_9050,
1431                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1432                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1433                 .init           = pci_plx9050_init,
1434                 .setup          = pci_default_setup,
1435                 .exit           = __devexit_p(pci_plx9050_exit),
1436         },
1437         {
1438                 .vendor         = PCI_VENDOR_ID_PLX,
1439                 .device         = PCI_DEVICE_ID_PLX_9050,
1440                 .subvendor      = PCI_VENDOR_ID_PLX,
1441                 .subdevice      = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1442                 .init           = pci_plx9050_init,
1443                 .setup          = pci_default_setup,
1444                 .exit           = __devexit_p(pci_plx9050_exit),
1445         },
1446         {
1447                 .vendor         = PCI_VENDOR_ID_PLX,
1448                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1449                 .subvendor      = PCI_VENDOR_ID_PLX,
1450                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1451                 .init           = pci_plx9050_init,
1452                 .setup          = pci_default_setup,
1453                 .exit           = __devexit_p(pci_plx9050_exit),
1454         },
1455         /*
1456          * SBS Technologies, Inc., PMC-OCTALPRO 232
1457          */
1458         {
1459                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1460                 .device         = PCI_DEVICE_ID_OCTPRO,
1461                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1462                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1463                 .init           = sbs_init,
1464                 .setup          = sbs_setup,
1465                 .exit           = __devexit_p(sbs_exit),
1466         },
1467         /*
1468          * SBS Technologies, Inc., PMC-OCTALPRO 422
1469          */
1470         {
1471                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1472                 .device         = PCI_DEVICE_ID_OCTPRO,
1473                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1474                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1475                 .init           = sbs_init,
1476                 .setup          = sbs_setup,
1477                 .exit           = __devexit_p(sbs_exit),
1478         },
1479         /*
1480          * SBS Technologies, Inc., P-Octal 232
1481          */
1482         {
1483                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1484                 .device         = PCI_DEVICE_ID_OCTPRO,
1485                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1486                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1487                 .init           = sbs_init,
1488                 .setup          = sbs_setup,
1489                 .exit           = __devexit_p(sbs_exit),
1490         },
1491         /*
1492          * SBS Technologies, Inc., P-Octal 422
1493          */
1494         {
1495                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1496                 .device         = PCI_DEVICE_ID_OCTPRO,
1497                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1498                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1499                 .init           = sbs_init,
1500                 .setup          = sbs_setup,
1501                 .exit           = __devexit_p(sbs_exit),
1502         },
1503         /*
1504          * SIIG cards - these may be called via parport_serial
1505          */
1506         {
1507                 .vendor         = PCI_VENDOR_ID_SIIG,
1508                 .device         = PCI_ANY_ID,
1509                 .subvendor      = PCI_ANY_ID,
1510                 .subdevice      = PCI_ANY_ID,
1511                 .init           = pci_siig_init,
1512                 .setup          = pci_siig_setup,
1513         },
1514         /*
1515          * Titan cards
1516          */
1517         {
1518                 .vendor         = PCI_VENDOR_ID_TITAN,
1519                 .device         = PCI_DEVICE_ID_TITAN_400L,
1520                 .subvendor      = PCI_ANY_ID,
1521                 .subdevice      = PCI_ANY_ID,
1522                 .setup          = titan_400l_800l_setup,
1523         },
1524         {
1525                 .vendor         = PCI_VENDOR_ID_TITAN,
1526                 .device         = PCI_DEVICE_ID_TITAN_800L,
1527                 .subvendor      = PCI_ANY_ID,
1528                 .subdevice      = PCI_ANY_ID,
1529                 .setup          = titan_400l_800l_setup,
1530         },
1531         /*
1532          * Timedia cards
1533          */
1534         {
1535                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1536                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1537                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1538                 .subdevice      = PCI_ANY_ID,
1539                 .probe          = pci_timedia_probe,
1540                 .init           = pci_timedia_init,
1541                 .setup          = pci_timedia_setup,
1542         },
1543         {
1544                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1545                 .device         = PCI_ANY_ID,
1546                 .subvendor      = PCI_ANY_ID,
1547                 .subdevice      = PCI_ANY_ID,
1548                 .setup          = pci_timedia_setup,
1549         },
1550         /*
1551          * Exar cards
1552          */
1553         {
1554                 .vendor = PCI_VENDOR_ID_EXAR,
1555                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1556                 .subvendor      = PCI_ANY_ID,
1557                 .subdevice      = PCI_ANY_ID,
1558                 .setup          = pci_xr17c154_setup,
1559         },
1560         {
1561                 .vendor = PCI_VENDOR_ID_EXAR,
1562                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1563                 .subvendor      = PCI_ANY_ID,
1564                 .subdevice      = PCI_ANY_ID,
1565                 .setup          = pci_xr17c154_setup,
1566         },
1567         {
1568                 .vendor = PCI_VENDOR_ID_EXAR,
1569                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1570                 .subvendor      = PCI_ANY_ID,
1571                 .subdevice      = PCI_ANY_ID,
1572                 .setup          = pci_xr17c154_setup,
1573         },
1574         /*
1575          * Xircom cards
1576          */
1577         {
1578                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1579                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1580                 .subvendor      = PCI_ANY_ID,
1581                 .subdevice      = PCI_ANY_ID,
1582                 .init           = pci_xircom_init,
1583                 .setup          = pci_default_setup,
1584         },
1585         /*
1586          * Netmos cards - these may be called via parport_serial
1587          */
1588         {
1589                 .vendor         = PCI_VENDOR_ID_NETMOS,
1590                 .device         = PCI_ANY_ID,
1591                 .subvendor      = PCI_ANY_ID,
1592                 .subdevice      = PCI_ANY_ID,
1593                 .init           = pci_netmos_init,
1594                 .setup          = pci_netmos_9900_setup,
1595         },
1596         /*
1597          * For Oxford Semiconductor Tornado based devices
1598          */
1599         {
1600                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1601                 .device         = PCI_ANY_ID,
1602                 .subvendor      = PCI_ANY_ID,
1603                 .subdevice      = PCI_ANY_ID,
1604                 .init           = pci_oxsemi_tornado_init,
1605                 .setup          = pci_default_setup,
1606         },
1607         {
1608                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1609                 .device         = PCI_ANY_ID,
1610                 .subvendor      = PCI_ANY_ID,
1611                 .subdevice      = PCI_ANY_ID,
1612                 .init           = pci_oxsemi_tornado_init,
1613                 .setup          = pci_default_setup,
1614         },
1615         {
1616                 .vendor         = PCI_VENDOR_ID_DIGI,
1617                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1618                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
1619                 .subdevice              = PCI_ANY_ID,
1620                 .init                   = pci_oxsemi_tornado_init,
1621                 .setup          = pci_default_setup,
1622         },
1623         {
1624                 .vendor         = PCI_VENDOR_ID_INTEL,
1625                 .device         = 0x8811,
1626                 .init           = pci_eg20t_init,
1627                 .setup          = pci_default_setup,
1628         },
1629         {
1630                 .vendor         = PCI_VENDOR_ID_INTEL,
1631                 .device         = 0x8812,
1632                 .init           = pci_eg20t_init,
1633                 .setup          = pci_default_setup,
1634         },
1635         {
1636                 .vendor         = PCI_VENDOR_ID_INTEL,
1637                 .device         = 0x8813,
1638                 .init           = pci_eg20t_init,
1639                 .setup          = pci_default_setup,
1640         },
1641         {
1642                 .vendor         = PCI_VENDOR_ID_INTEL,
1643                 .device         = 0x8814,
1644                 .init           = pci_eg20t_init,
1645                 .setup          = pci_default_setup,
1646         },
1647         {
1648                 .vendor         = 0x10DB,
1649                 .device         = 0x8027,
1650                 .init           = pci_eg20t_init,
1651                 .setup          = pci_default_setup,
1652         },
1653         {
1654                 .vendor         = 0x10DB,
1655                 .device         = 0x8028,
1656                 .init           = pci_eg20t_init,
1657                 .setup          = pci_default_setup,
1658         },
1659         {
1660                 .vendor         = 0x10DB,
1661                 .device         = 0x8029,
1662                 .init           = pci_eg20t_init,
1663                 .setup          = pci_default_setup,
1664         },
1665         {
1666                 .vendor         = 0x10DB,
1667                 .device         = 0x800C,
1668                 .init           = pci_eg20t_init,
1669                 .setup          = pci_default_setup,
1670         },
1671         {
1672                 .vendor         = 0x10DB,
1673                 .device         = 0x800D,
1674                 .init           = pci_eg20t_init,
1675                 .setup          = pci_default_setup,
1676         },
1677         /*
1678          * Cronyx Omega PCI (PLX-chip based)
1679          */
1680         {
1681                 .vendor         = PCI_VENDOR_ID_PLX,
1682                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1683                 .subvendor      = PCI_ANY_ID,
1684                 .subdevice      = PCI_ANY_ID,
1685                 .setup          = pci_omegapci_setup,
1686          },
1687         /*
1688          * Default "match everything" terminator entry
1689          */
1690         {
1691                 .vendor         = PCI_ANY_ID,
1692                 .device         = PCI_ANY_ID,
1693                 .subvendor      = PCI_ANY_ID,
1694                 .subdevice      = PCI_ANY_ID,
1695                 .setup          = pci_default_setup,
1696         }
1697 };
1698
1699 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1700 {
1701         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1702 }
1703
1704 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1705 {
1706         struct pci_serial_quirk *quirk;
1707
1708         for (quirk = pci_serial_quirks; ; quirk++)
1709                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1710                     quirk_id_matches(quirk->device, dev->device) &&
1711                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1712                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1713                         break;
1714         return quirk;
1715 }
1716
1717 static inline int get_pci_irq(struct pci_dev *dev,
1718                                 const struct pciserial_board *board)
1719 {
1720         if (board->flags & FL_NOIRQ)
1721                 return 0;
1722         else
1723                 return dev->irq;
1724 }
1725
1726 /*
1727  * This is the configuration table for all of the PCI serial boards
1728  * which we support.  It is directly indexed by the pci_board_num_t enum
1729  * value, which is encoded in the pci_device_id PCI probe table's
1730  * driver_data member.
1731  *
1732  * The makeup of these names are:
1733  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1734  *
1735  *  bn          = PCI BAR number
1736  *  bt          = Index using PCI BARs
1737  *  n           = number of serial ports
1738  *  baud        = baud rate
1739  *  offsetinhex = offset for each sequential port (in hex)
1740  *
1741  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1742  *
1743  * Please note: in theory if n = 1, _bt infix should make no difference.
1744  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1745  */
1746 enum pci_board_num_t {
1747         pbn_default = 0,
1748
1749         pbn_b0_1_115200,
1750         pbn_b0_2_115200,
1751         pbn_b0_4_115200,
1752         pbn_b0_5_115200,
1753         pbn_b0_8_115200,
1754
1755         pbn_b0_1_921600,
1756         pbn_b0_2_921600,
1757         pbn_b0_4_921600,
1758
1759         pbn_b0_2_1130000,
1760
1761         pbn_b0_4_1152000,
1762
1763         pbn_b0_2_1843200,
1764         pbn_b0_4_1843200,
1765
1766         pbn_b0_2_1843200_200,
1767         pbn_b0_4_1843200_200,
1768         pbn_b0_8_1843200_200,
1769
1770         pbn_b0_1_4000000,
1771
1772         pbn_b0_bt_1_115200,
1773         pbn_b0_bt_2_115200,
1774         pbn_b0_bt_4_115200,
1775         pbn_b0_bt_8_115200,
1776
1777         pbn_b0_bt_1_460800,
1778         pbn_b0_bt_2_460800,
1779         pbn_b0_bt_4_460800,
1780
1781         pbn_b0_bt_1_921600,
1782         pbn_b0_bt_2_921600,
1783         pbn_b0_bt_4_921600,
1784         pbn_b0_bt_8_921600,
1785
1786         pbn_b1_1_115200,
1787         pbn_b1_2_115200,
1788         pbn_b1_4_115200,
1789         pbn_b1_8_115200,
1790         pbn_b1_16_115200,
1791
1792         pbn_b1_1_921600,
1793         pbn_b1_2_921600,
1794         pbn_b1_4_921600,
1795         pbn_b1_8_921600,
1796
1797         pbn_b1_2_1250000,
1798
1799         pbn_b1_bt_1_115200,
1800         pbn_b1_bt_2_115200,
1801         pbn_b1_bt_4_115200,
1802
1803         pbn_b1_bt_2_921600,
1804
1805         pbn_b1_1_1382400,
1806         pbn_b1_2_1382400,
1807         pbn_b1_4_1382400,
1808         pbn_b1_8_1382400,
1809
1810         pbn_b2_1_115200,
1811         pbn_b2_2_115200,
1812         pbn_b2_4_115200,
1813         pbn_b2_8_115200,
1814
1815         pbn_b2_1_460800,
1816         pbn_b2_4_460800,
1817         pbn_b2_8_460800,
1818         pbn_b2_16_460800,
1819
1820         pbn_b2_1_921600,
1821         pbn_b2_4_921600,
1822         pbn_b2_8_921600,
1823
1824         pbn_b2_8_1152000,
1825
1826         pbn_b2_bt_1_115200,
1827         pbn_b2_bt_2_115200,
1828         pbn_b2_bt_4_115200,
1829
1830         pbn_b2_bt_2_921600,
1831         pbn_b2_bt_4_921600,
1832
1833         pbn_b3_2_115200,
1834         pbn_b3_4_115200,
1835         pbn_b3_8_115200,
1836
1837         pbn_b4_bt_2_921600,
1838         pbn_b4_bt_4_921600,
1839         pbn_b4_bt_8_921600,
1840
1841         /*
1842          * Board-specific versions.
1843          */
1844         pbn_panacom,
1845         pbn_panacom2,
1846         pbn_panacom4,
1847         pbn_exsys_4055,
1848         pbn_plx_romulus,
1849         pbn_oxsemi,
1850         pbn_oxsemi_1_4000000,
1851         pbn_oxsemi_2_4000000,
1852         pbn_oxsemi_4_4000000,
1853         pbn_oxsemi_8_4000000,
1854         pbn_intel_i960,
1855         pbn_sgi_ioc3,
1856         pbn_computone_4,
1857         pbn_computone_6,
1858         pbn_computone_8,
1859         pbn_sbsxrsio,
1860         pbn_exar_XR17C152,
1861         pbn_exar_XR17C154,
1862         pbn_exar_XR17C158,
1863         pbn_exar_ibm_saturn,
1864         pbn_pasemi_1682M,
1865         pbn_ni8430_2,
1866         pbn_ni8430_4,
1867         pbn_ni8430_8,
1868         pbn_ni8430_16,
1869         pbn_ADDIDATA_PCIe_1_3906250,
1870         pbn_ADDIDATA_PCIe_2_3906250,
1871         pbn_ADDIDATA_PCIe_4_3906250,
1872         pbn_ADDIDATA_PCIe_8_3906250,
1873         pbn_ce4100_1_115200,
1874         pbn_omegapci,
1875         pbn_NETMOS9900_2s_115200,
1876 };
1877
1878 /*
1879  * uart_offset - the space between channels
1880  * reg_shift   - describes how the UART registers are mapped
1881  *               to PCI memory by the card.
1882  * For example IER register on SBS, Inc. PMC-OctPro is located at
1883  * offset 0x10 from the UART base, while UART_IER is defined as 1
1884  * in include/linux/serial_reg.h,
1885  * see first lines of serial_in() and serial_out() in 8250.c
1886 */
1887
1888 static struct pciserial_board pci_boards[] __devinitdata = {
1889         [pbn_default] = {
1890                 .flags          = FL_BASE0,
1891                 .num_ports      = 1,
1892                 .base_baud      = 115200,
1893                 .uart_offset    = 8,
1894         },
1895         [pbn_b0_1_115200] = {
1896                 .flags          = FL_BASE0,
1897                 .num_ports      = 1,
1898                 .base_baud      = 115200,
1899                 .uart_offset    = 8,
1900         },
1901         [pbn_b0_2_115200] = {
1902                 .flags          = FL_BASE0,
1903                 .num_ports      = 2,
1904                 .base_baud      = 115200,
1905                 .uart_offset    = 8,
1906         },
1907         [pbn_b0_4_115200] = {
1908                 .flags          = FL_BASE0,
1909                 .num_ports      = 4,
1910                 .base_baud      = 115200,
1911                 .uart_offset    = 8,
1912         },
1913         [pbn_b0_5_115200] = {
1914                 .flags          = FL_BASE0,
1915                 .num_ports      = 5,
1916                 .base_baud      = 115200,
1917                 .uart_offset    = 8,
1918         },
1919         [pbn_b0_8_115200] = {
1920                 .flags          = FL_BASE0,
1921                 .num_ports      = 8,
1922                 .base_baud      = 115200,
1923                 .uart_offset    = 8,
1924         },
1925         [pbn_b0_1_921600] = {
1926                 .flags          = FL_BASE0,
1927                 .num_ports      = 1,
1928                 .base_baud      = 921600,
1929                 .uart_offset    = 8,
1930         },
1931         [pbn_b0_2_921600] = {
1932                 .flags          = FL_BASE0,
1933                 .num_ports      = 2,
1934                 .base_baud      = 921600,
1935                 .uart_offset    = 8,
1936         },
1937         [pbn_b0_4_921600] = {
1938                 .flags          = FL_BASE0,
1939                 .num_ports      = 4,
1940                 .base_baud      = 921600,
1941                 .uart_offset    = 8,
1942         },
1943
1944         [pbn_b0_2_1130000] = {
1945                 .flags          = FL_BASE0,
1946                 .num_ports      = 2,
1947                 .base_baud      = 1130000,
1948                 .uart_offset    = 8,
1949         },
1950
1951         [pbn_b0_4_1152000] = {
1952                 .flags          = FL_BASE0,
1953                 .num_ports      = 4,
1954                 .base_baud      = 1152000,
1955                 .uart_offset    = 8,
1956         },
1957
1958         [pbn_b0_2_1843200] = {
1959                 .flags          = FL_BASE0,
1960                 .num_ports      = 2,
1961                 .base_baud      = 1843200,
1962                 .uart_offset    = 8,
1963         },
1964         [pbn_b0_4_1843200] = {
1965                 .flags          = FL_BASE0,
1966                 .num_ports      = 4,
1967                 .base_baud      = 1843200,
1968                 .uart_offset    = 8,
1969         },
1970
1971         [pbn_b0_2_1843200_200] = {
1972                 .flags          = FL_BASE0,
1973                 .num_ports      = 2,
1974                 .base_baud      = 1843200,
1975                 .uart_offset    = 0x200,
1976         },
1977         [pbn_b0_4_1843200_200] = {
1978                 .flags          = FL_BASE0,
1979                 .num_ports      = 4,
1980                 .base_baud      = 1843200,
1981                 .uart_offset    = 0x200,
1982         },
1983         [pbn_b0_8_1843200_200] = {
1984                 .flags          = FL_BASE0,
1985                 .num_ports      = 8,
1986                 .base_baud      = 1843200,
1987                 .uart_offset    = 0x200,
1988         },
1989         [pbn_b0_1_4000000] = {
1990                 .flags          = FL_BASE0,
1991                 .num_ports      = 1,
1992                 .base_baud      = 4000000,
1993                 .uart_offset    = 8,
1994         },
1995
1996         [pbn_b0_bt_1_115200] = {
1997                 .flags          = FL_BASE0|FL_BASE_BARS,
1998                 .num_ports      = 1,
1999                 .base_baud      = 115200,
2000                 .uart_offset    = 8,
2001         },
2002         [pbn_b0_bt_2_115200] = {
2003                 .flags          = FL_BASE0|FL_BASE_BARS,
2004                 .num_ports      = 2,
2005                 .base_baud      = 115200,
2006                 .uart_offset    = 8,
2007         },
2008         [pbn_b0_bt_4_115200] = {
2009                 .flags          = FL_BASE0|FL_BASE_BARS,
2010                 .num_ports      = 4,
2011                 .base_baud      = 115200,
2012                 .uart_offset    = 8,
2013         },
2014         [pbn_b0_bt_8_115200] = {
2015                 .flags          = FL_BASE0|FL_BASE_BARS,
2016                 .num_ports      = 8,
2017                 .base_baud      = 115200,
2018                 .uart_offset    = 8,
2019         },
2020
2021         [pbn_b0_bt_1_460800] = {
2022                 .flags          = FL_BASE0|FL_BASE_BARS,
2023                 .num_ports      = 1,
2024                 .base_baud      = 460800,
2025                 .uart_offset    = 8,
2026         },
2027         [pbn_b0_bt_2_460800] = {
2028                 .flags          = FL_BASE0|FL_BASE_BARS,
2029                 .num_ports      = 2,
2030                 .base_baud      = 460800,
2031                 .uart_offset    = 8,
2032         },
2033         [pbn_b0_bt_4_460800] = {
2034                 .flags          = FL_BASE0|FL_BASE_BARS,
2035                 .num_ports      = 4,
2036                 .base_baud      = 460800,
2037                 .uart_offset    = 8,
2038         },
2039
2040         [pbn_b0_bt_1_921600] = {
2041                 .flags          = FL_BASE0|FL_BASE_BARS,
2042                 .num_ports      = 1,
2043                 .base_baud      = 921600,
2044                 .uart_offset    = 8,
2045         },
2046         [pbn_b0_bt_2_921600] = {
2047                 .flags          = FL_BASE0|FL_BASE_BARS,
2048                 .num_ports      = 2,
2049                 .base_baud      = 921600,
2050                 .uart_offset    = 8,
2051         },
2052         [pbn_b0_bt_4_921600] = {
2053                 .flags          = FL_BASE0|FL_BASE_BARS,
2054                 .num_ports      = 4,
2055                 .base_baud      = 921600,
2056                 .uart_offset    = 8,
2057         },
2058         [pbn_b0_bt_8_921600] = {
2059                 .flags          = FL_BASE0|FL_BASE_BARS,
2060                 .num_ports      = 8,
2061                 .base_baud      = 921600,
2062                 .uart_offset    = 8,
2063         },
2064
2065         [pbn_b1_1_115200] = {
2066                 .flags          = FL_BASE1,
2067                 .num_ports      = 1,
2068                 .base_baud      = 115200,
2069                 .uart_offset    = 8,
2070         },
2071         [pbn_b1_2_115200] = {
2072                 .flags          = FL_BASE1,
2073                 .num_ports      = 2,
2074                 .base_baud      = 115200,
2075                 .uart_offset    = 8,
2076         },
2077         [pbn_b1_4_115200] = {
2078                 .flags          = FL_BASE1,
2079                 .num_ports      = 4,
2080                 .base_baud      = 115200,
2081                 .uart_offset    = 8,
2082         },
2083         [pbn_b1_8_115200] = {
2084                 .flags          = FL_BASE1,
2085                 .num_ports      = 8,
2086                 .base_baud      = 115200,
2087                 .uart_offset    = 8,
2088         },
2089         [pbn_b1_16_115200] = {
2090                 .flags          = FL_BASE1,
2091                 .num_ports      = 16,
2092                 .base_baud      = 115200,
2093                 .uart_offset    = 8,
2094         },
2095
2096         [pbn_b1_1_921600] = {
2097                 .flags          = FL_BASE1,
2098                 .num_ports      = 1,
2099                 .base_baud      = 921600,
2100                 .uart_offset    = 8,
2101         },
2102         [pbn_b1_2_921600] = {
2103                 .flags          = FL_BASE1,
2104                 .num_ports      = 2,
2105                 .base_baud      = 921600,
2106                 .uart_offset    = 8,
2107         },
2108         [pbn_b1_4_921600] = {
2109                 .flags          = FL_BASE1,
2110                 .num_ports      = 4,
2111                 .base_baud      = 921600,
2112                 .uart_offset    = 8,
2113         },
2114         [pbn_b1_8_921600] = {
2115                 .flags          = FL_BASE1,
2116                 .num_ports      = 8,
2117                 .base_baud      = 921600,
2118                 .uart_offset    = 8,
2119         },
2120         [pbn_b1_2_1250000] = {
2121                 .flags          = FL_BASE1,
2122                 .num_ports      = 2,
2123                 .base_baud      = 1250000,
2124                 .uart_offset    = 8,
2125         },
2126
2127         [pbn_b1_bt_1_115200] = {
2128                 .flags          = FL_BASE1|FL_BASE_BARS,
2129                 .num_ports      = 1,
2130                 .base_baud      = 115200,
2131                 .uart_offset    = 8,
2132         },
2133         [pbn_b1_bt_2_115200] = {
2134                 .flags          = FL_BASE1|FL_BASE_BARS,
2135                 .num_ports      = 2,
2136                 .base_baud      = 115200,
2137                 .uart_offset    = 8,
2138         },
2139         [pbn_b1_bt_4_115200] = {
2140                 .flags          = FL_BASE1|FL_BASE_BARS,
2141                 .num_ports      = 4,
2142                 .base_baud      = 115200,
2143                 .uart_offset    = 8,
2144         },
2145
2146         [pbn_b1_bt_2_921600] = {
2147                 .flags          = FL_BASE1|FL_BASE_BARS,
2148                 .num_ports      = 2,
2149                 .base_baud      = 921600,
2150                 .uart_offset    = 8,
2151         },
2152
2153         [pbn_b1_1_1382400] = {
2154                 .flags          = FL_BASE1,
2155                 .num_ports      = 1,
2156                 .base_baud      = 1382400,
2157                 .uart_offset    = 8,
2158         },
2159         [pbn_b1_2_1382400] = {
2160                 .flags          = FL_BASE1,
2161                 .num_ports      = 2,
2162                 .base_baud      = 1382400,
2163                 .uart_offset    = 8,
2164         },
2165         [pbn_b1_4_1382400] = {
2166                 .flags          = FL_BASE1,
2167                 .num_ports      = 4,
2168                 .base_baud      = 1382400,
2169                 .uart_offset    = 8,
2170         },
2171         [pbn_b1_8_1382400] = {
2172                 .flags          = FL_BASE1,
2173                 .num_ports      = 8,
2174                 .base_baud      = 1382400,
2175                 .uart_offset    = 8,
2176         },
2177
2178         [pbn_b2_1_115200] = {
2179                 .flags          = FL_BASE2,
2180                 .num_ports      = 1,
2181                 .base_baud      = 115200,
2182                 .uart_offset    = 8,
2183         },
2184         [pbn_b2_2_115200] = {
2185                 .flags          = FL_BASE2,
2186                 .num_ports      = 2,
2187                 .base_baud      = 115200,
2188                 .uart_offset    = 8,
2189         },
2190         [pbn_b2_4_115200] = {
2191                 .flags          = FL_BASE2,
2192                 .num_ports      = 4,
2193                 .base_baud      = 115200,
2194                 .uart_offset    = 8,
2195         },
2196         [pbn_b2_8_115200] = {
2197                 .flags          = FL_BASE2,
2198                 .num_ports      = 8,
2199                 .base_baud      = 115200,
2200                 .uart_offset    = 8,
2201         },
2202
2203         [pbn_b2_1_460800] = {
2204                 .flags          = FL_BASE2,
2205                 .num_ports      = 1,
2206                 .base_baud      = 460800,
2207                 .uart_offset    = 8,
2208         },
2209         [pbn_b2_4_460800] = {
2210                 .flags          = FL_BASE2,
2211                 .num_ports      = 4,
2212                 .base_baud      = 460800,
2213                 .uart_offset    = 8,
2214         },
2215         [pbn_b2_8_460800] = {
2216                 .flags          = FL_BASE2,
2217                 .num_ports      = 8,
2218                 .base_baud      = 460800,
2219                 .uart_offset    = 8,
2220         },
2221         [pbn_b2_16_460800] = {
2222                 .flags          = FL_BASE2,
2223                 .num_ports      = 16,
2224                 .base_baud      = 460800,
2225                 .uart_offset    = 8,
2226          },
2227
2228         [pbn_b2_1_921600] = {
2229                 .flags          = FL_BASE2,
2230                 .num_ports      = 1,
2231                 .base_baud      = 921600,
2232                 .uart_offset    = 8,
2233         },
2234         [pbn_b2_4_921600] = {
2235                 .flags          = FL_BASE2,
2236                 .num_ports      = 4,
2237                 .base_baud      = 921600,
2238                 .uart_offset    = 8,
2239         },
2240         [pbn_b2_8_921600] = {
2241                 .flags          = FL_BASE2,
2242                 .num_ports      = 8,
2243                 .base_baud      = 921600,
2244                 .uart_offset    = 8,
2245         },
2246
2247         [pbn_b2_8_1152000] = {
2248                 .flags          = FL_BASE2,
2249                 .num_ports      = 8,
2250                 .base_baud      = 1152000,
2251                 .uart_offset    = 8,
2252         },
2253
2254         [pbn_b2_bt_1_115200] = {
2255                 .flags          = FL_BASE2|FL_BASE_BARS,
2256                 .num_ports      = 1,
2257                 .base_baud      = 115200,
2258                 .uart_offset    = 8,
2259         },
2260         [pbn_b2_bt_2_115200] = {
2261                 .flags          = FL_BASE2|FL_BASE_BARS,
2262                 .num_ports      = 2,
2263                 .base_baud      = 115200,
2264                 .uart_offset    = 8,
2265         },
2266         [pbn_b2_bt_4_115200] = {
2267                 .flags          = FL_BASE2|FL_BASE_BARS,
2268                 .num_ports      = 4,
2269                 .base_baud      = 115200,
2270                 .uart_offset    = 8,
2271         },
2272
2273         [pbn_b2_bt_2_921600] = {
2274                 .flags          = FL_BASE2|FL_BASE_BARS,
2275                 .num_ports      = 2,
2276                 .base_baud      = 921600,
2277                 .uart_offset    = 8,
2278         },
2279         [pbn_b2_bt_4_921600] = {
2280                 .flags          = FL_BASE2|FL_BASE_BARS,
2281                 .num_ports      = 4,
2282                 .base_baud      = 921600,
2283                 .uart_offset    = 8,
2284         },
2285
2286         [pbn_b3_2_115200] = {
2287                 .flags          = FL_BASE3,
2288                 .num_ports      = 2,
2289                 .base_baud      = 115200,
2290                 .uart_offset    = 8,
2291         },
2292         [pbn_b3_4_115200] = {
2293                 .flags          = FL_BASE3,
2294                 .num_ports      = 4,
2295                 .base_baud      = 115200,
2296                 .uart_offset    = 8,
2297         },
2298         [pbn_b3_8_115200] = {
2299                 .flags          = FL_BASE3,
2300                 .num_ports      = 8,
2301                 .base_baud      = 115200,
2302                 .uart_offset    = 8,
2303         },
2304
2305         [pbn_b4_bt_2_921600] = {
2306                 .flags          = FL_BASE4,
2307                 .num_ports      = 2,
2308                 .base_baud      = 921600,
2309                 .uart_offset    = 8,
2310         },
2311         [pbn_b4_bt_4_921600] = {
2312                 .flags          = FL_BASE4,
2313                 .num_ports      = 4,
2314                 .base_baud      = 921600,
2315                 .uart_offset    = 8,
2316         },
2317         [pbn_b4_bt_8_921600] = {
2318                 .flags          = FL_BASE4,
2319                 .num_ports      = 8,
2320                 .base_baud      = 921600,
2321                 .uart_offset    = 8,
2322         },
2323
2324         /*
2325          * Entries following this are board-specific.
2326          */
2327
2328         /*
2329          * Panacom - IOMEM
2330          */
2331         [pbn_panacom] = {
2332                 .flags          = FL_BASE2,
2333                 .num_ports      = 2,
2334                 .base_baud      = 921600,
2335                 .uart_offset    = 0x400,
2336                 .reg_shift      = 7,
2337         },
2338         [pbn_panacom2] = {
2339                 .flags          = FL_BASE2|FL_BASE_BARS,
2340                 .num_ports      = 2,
2341                 .base_baud      = 921600,
2342                 .uart_offset    = 0x400,
2343                 .reg_shift      = 7,
2344         },
2345         [pbn_panacom4] = {
2346                 .flags          = FL_BASE2|FL_BASE_BARS,
2347                 .num_ports      = 4,
2348                 .base_baud      = 921600,
2349                 .uart_offset    = 0x400,
2350                 .reg_shift      = 7,
2351         },
2352
2353         [pbn_exsys_4055] = {
2354                 .flags          = FL_BASE2,
2355                 .num_ports      = 4,
2356                 .base_baud      = 115200,
2357                 .uart_offset    = 8,
2358         },
2359
2360         /* I think this entry is broken - the first_offset looks wrong --rmk */
2361         [pbn_plx_romulus] = {
2362                 .flags          = FL_BASE2,
2363                 .num_ports      = 4,
2364                 .base_baud      = 921600,
2365                 .uart_offset    = 8 << 2,
2366                 .reg_shift      = 2,
2367                 .first_offset   = 0x03,
2368         },
2369
2370         /*
2371          * This board uses the size of PCI Base region 0 to
2372          * signal now many ports are available
2373          */
2374         [pbn_oxsemi] = {
2375                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2376                 .num_ports      = 32,
2377                 .base_baud      = 115200,
2378                 .uart_offset    = 8,
2379         },
2380         [pbn_oxsemi_1_4000000] = {
2381                 .flags          = FL_BASE0,
2382                 .num_ports      = 1,
2383                 .base_baud      = 4000000,
2384                 .uart_offset    = 0x200,
2385                 .first_offset   = 0x1000,
2386         },
2387         [pbn_oxsemi_2_4000000] = {
2388                 .flags          = FL_BASE0,
2389                 .num_ports      = 2,
2390                 .base_baud      = 4000000,
2391                 .uart_offset    = 0x200,
2392                 .first_offset   = 0x1000,
2393         },
2394         [pbn_oxsemi_4_4000000] = {
2395                 .flags          = FL_BASE0,
2396                 .num_ports      = 4,
2397                 .base_baud      = 4000000,
2398                 .uart_offset    = 0x200,
2399                 .first_offset   = 0x1000,
2400         },
2401         [pbn_oxsemi_8_4000000] = {
2402                 .flags          = FL_BASE0,
2403                 .num_ports      = 8,
2404                 .base_baud      = 4000000,
2405                 .uart_offset    = 0x200,
2406                 .first_offset   = 0x1000,
2407         },
2408
2409
2410         /*
2411          * EKF addition for i960 Boards form EKF with serial port.
2412          * Max 256 ports.
2413          */
2414         [pbn_intel_i960] = {
2415                 .flags          = FL_BASE0,
2416                 .num_ports      = 32,
2417                 .base_baud      = 921600,
2418                 .uart_offset    = 8 << 2,
2419                 .reg_shift      = 2,
2420                 .first_offset   = 0x10000,
2421         },
2422         [pbn_sgi_ioc3] = {
2423                 .flags          = FL_BASE0|FL_NOIRQ,
2424                 .num_ports      = 1,
2425                 .base_baud      = 458333,
2426                 .uart_offset    = 8,
2427                 .reg_shift      = 0,
2428                 .first_offset   = 0x20178,
2429         },
2430
2431         /*
2432          * Computone - uses IOMEM.
2433          */
2434         [pbn_computone_4] = {
2435                 .flags          = FL_BASE0,
2436                 .num_ports      = 4,
2437                 .base_baud      = 921600,
2438                 .uart_offset    = 0x40,
2439                 .reg_shift      = 2,
2440                 .first_offset   = 0x200,
2441         },
2442         [pbn_computone_6] = {
2443                 .flags          = FL_BASE0,
2444                 .num_ports      = 6,
2445                 .base_baud      = 921600,
2446                 .uart_offset    = 0x40,
2447                 .reg_shift      = 2,
2448                 .first_offset   = 0x200,
2449         },
2450         [pbn_computone_8] = {
2451                 .flags          = FL_BASE0,
2452                 .num_ports      = 8,
2453                 .base_baud      = 921600,
2454                 .uart_offset    = 0x40,
2455                 .reg_shift      = 2,
2456                 .first_offset   = 0x200,
2457         },
2458         [pbn_sbsxrsio] = {
2459                 .flags          = FL_BASE0,
2460                 .num_ports      = 8,
2461                 .base_baud      = 460800,
2462                 .uart_offset    = 256,
2463                 .reg_shift      = 4,
2464         },
2465         /*
2466          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2467          *  Only basic 16550A support.
2468          *  XR17C15[24] are not tested, but they should work.
2469          */
2470         [pbn_exar_XR17C152] = {
2471                 .flags          = FL_BASE0,
2472                 .num_ports      = 2,
2473                 .base_baud      = 921600,
2474                 .uart_offset    = 0x200,
2475         },
2476         [pbn_exar_XR17C154] = {
2477                 .flags          = FL_BASE0,
2478                 .num_ports      = 4,
2479                 .base_baud      = 921600,
2480                 .uart_offset    = 0x200,
2481         },
2482         [pbn_exar_XR17C158] = {
2483                 .flags          = FL_BASE0,
2484                 .num_ports      = 8,
2485                 .base_baud      = 921600,
2486                 .uart_offset    = 0x200,
2487         },
2488         [pbn_exar_ibm_saturn] = {
2489                 .flags          = FL_BASE0,
2490                 .num_ports      = 1,
2491                 .base_baud      = 921600,
2492                 .uart_offset    = 0x200,
2493         },
2494
2495         /*
2496          * PA Semi PWRficient PA6T-1682M on-chip UART
2497          */
2498         [pbn_pasemi_1682M] = {
2499                 .flags          = FL_BASE0,
2500                 .num_ports      = 1,
2501                 .base_baud      = 8333333,
2502         },
2503         /*
2504          * National Instruments 843x
2505          */
2506         [pbn_ni8430_16] = {
2507                 .flags          = FL_BASE0,
2508                 .num_ports      = 16,
2509                 .base_baud      = 3686400,
2510                 .uart_offset    = 0x10,
2511                 .first_offset   = 0x800,
2512         },
2513         [pbn_ni8430_8] = {
2514                 .flags          = FL_BASE0,
2515                 .num_ports      = 8,
2516                 .base_baud      = 3686400,
2517                 .uart_offset    = 0x10,
2518                 .first_offset   = 0x800,
2519         },
2520         [pbn_ni8430_4] = {
2521                 .flags          = FL_BASE0,
2522                 .num_ports      = 4,
2523                 .base_baud      = 3686400,
2524                 .uart_offset    = 0x10,
2525                 .first_offset   = 0x800,
2526         },
2527         [pbn_ni8430_2] = {
2528                 .flags          = FL_BASE0,
2529                 .num_ports      = 2,
2530                 .base_baud      = 3686400,
2531                 .uart_offset    = 0x10,
2532                 .first_offset   = 0x800,
2533         },
2534         /*
2535          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2536          */
2537         [pbn_ADDIDATA_PCIe_1_3906250] = {
2538                 .flags          = FL_BASE0,
2539                 .num_ports      = 1,
2540                 .base_baud      = 3906250,
2541                 .uart_offset    = 0x200,
2542                 .first_offset   = 0x1000,
2543         },
2544         [pbn_ADDIDATA_PCIe_2_3906250] = {
2545                 .flags          = FL_BASE0,
2546                 .num_ports      = 2,
2547                 .base_baud      = 3906250,
2548                 .uart_offset    = 0x200,
2549                 .first_offset   = 0x1000,
2550         },
2551         [pbn_ADDIDATA_PCIe_4_3906250] = {
2552                 .flags          = FL_BASE0,
2553                 .num_ports      = 4,
2554                 .base_baud      = 3906250,
2555                 .uart_offset    = 0x200,
2556                 .first_offset   = 0x1000,
2557         },
2558         [pbn_ADDIDATA_PCIe_8_3906250] = {
2559                 .flags          = FL_BASE0,
2560                 .num_ports      = 8,
2561                 .base_baud      = 3906250,
2562                 .uart_offset    = 0x200,
2563                 .first_offset   = 0x1000,
2564         },
2565         [pbn_ce4100_1_115200] = {
2566                 .flags          = FL_BASE0,
2567                 .num_ports      = 1,
2568                 .base_baud      = 921600,
2569                 .reg_shift      = 2,
2570         },
2571         [pbn_omegapci] = {
2572                 .flags          = FL_BASE0,
2573                 .num_ports      = 8,
2574                 .base_baud      = 115200,
2575                 .uart_offset    = 0x200,
2576         },
2577         [pbn_NETMOS9900_2s_115200] = {
2578                 .flags          = FL_BASE0,
2579                 .num_ports      = 2,
2580                 .base_baud      = 115200,
2581         },
2582 };
2583
2584 static const struct pci_device_id softmodem_blacklist[] = {
2585         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2586         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2587         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2588 };
2589
2590 /*
2591  * Given a complete unknown PCI device, try to use some heuristics to
2592  * guess what the configuration might be, based on the pitiful PCI
2593  * serial specs.  Returns 0 on success, 1 on failure.
2594  */
2595 static int __devinit
2596 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2597 {
2598         const struct pci_device_id *blacklist;
2599         int num_iomem, num_port, first_port = -1, i;
2600
2601         /*
2602          * If it is not a communications device or the programming
2603          * interface is greater than 6, give up.
2604          *
2605          * (Should we try to make guesses for multiport serial devices
2606          * later?)
2607          */
2608         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2609              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2610             (dev->class & 0xff) > 6)
2611                 return -ENODEV;
2612
2613         /*
2614          * Do not access blacklisted devices that are known not to
2615          * feature serial ports.
2616          */
2617         for (blacklist = softmodem_blacklist;
2618              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2619              blacklist++) {
2620                 if (dev->vendor == blacklist->vendor &&
2621                     dev->device == blacklist->device)
2622                         return -ENODEV;
2623         }
2624
2625         num_iomem = num_port = 0;
2626         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2627                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2628                         num_port++;
2629                         if (first_port == -1)
2630                                 first_port = i;
2631                 }
2632                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2633                         num_iomem++;
2634         }
2635
2636         /*
2637          * If there is 1 or 0 iomem regions, and exactly one port,
2638          * use it.  We guess the number of ports based on the IO
2639          * region size.
2640          */
2641         if (num_iomem <= 1 && num_port == 1) {
2642                 board->flags = first_port;
2643                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2644                 return 0;
2645         }
2646
2647         /*
2648          * Now guess if we've got a board which indexes by BARs.
2649          * Each IO BAR should be 8 bytes, and they should follow
2650          * consecutively.
2651          */
2652         first_port = -1;
2653         num_port = 0;
2654         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2655                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2656                     pci_resource_len(dev, i) == 8 &&
2657                     (first_port == -1 || (first_port + num_port) == i)) {
2658                         num_port++;
2659                         if (first_port == -1)
2660                                 first_port = i;
2661                 }
2662         }
2663
2664         if (num_port > 1) {
2665                 board->flags = first_port | FL_BASE_BARS;
2666                 board->num_ports = num_port;
2667                 return 0;
2668         }
2669
2670         return -ENODEV;
2671 }
2672
2673 static inline int
2674 serial_pci_matches(const struct pciserial_board *board,
2675                    const struct pciserial_board *guessed)
2676 {
2677         return
2678             board->num_ports == guessed->num_ports &&
2679             board->base_baud == guessed->base_baud &&
2680             board->uart_offset == guessed->uart_offset &&
2681             board->reg_shift == guessed->reg_shift &&
2682             board->first_offset == guessed->first_offset;
2683 }
2684
2685 struct serial_private *
2686 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2687 {
2688         struct uart_port serial_port;
2689         struct serial_private *priv;
2690         struct pci_serial_quirk *quirk;
2691         int rc, nr_ports, i;
2692
2693         nr_ports = board->num_ports;
2694
2695         /*
2696          * Find an init and setup quirks.
2697          */
2698         quirk = find_quirk(dev);
2699
2700         /*
2701          * Run the new-style initialization function.
2702          * The initialization function returns:
2703          *  <0  - error
2704          *   0  - use board->num_ports
2705          *  >0  - number of ports
2706          */
2707         if (quirk->init) {
2708                 rc = quirk->init(dev);
2709                 if (rc < 0) {
2710                         priv = ERR_PTR(rc);
2711                         goto err_out;
2712                 }
2713                 if (rc)
2714                         nr_ports = rc;
2715         }
2716
2717         priv = kzalloc(sizeof(struct serial_private) +
2718                        sizeof(unsigned int) * nr_ports,
2719                        GFP_KERNEL);
2720         if (!priv) {
2721                 priv = ERR_PTR(-ENOMEM);
2722                 goto err_deinit;
2723         }
2724
2725         priv->dev = dev;
2726         priv->quirk = quirk;
2727
2728         memset(&serial_port, 0, sizeof(struct uart_port));
2729         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2730         serial_port.uartclk = board->base_baud * 16;
2731         serial_port.irq = get_pci_irq(dev, board);
2732         serial_port.dev = &dev->dev;
2733
2734         for (i = 0; i < nr_ports; i++) {
2735                 if (quirk->setup(priv, board, &serial_port, i))
2736                         break;
2737
2738 #ifdef SERIAL_DEBUG_PCI
2739                 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2740                        serial_port.iobase, serial_port.irq, serial_port.iotype);
2741 #endif
2742
2743                 priv->line[i] = serial8250_register_port(&serial_port);
2744                 if (priv->line[i] < 0) {
2745                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2746                         break;
2747                 }
2748         }
2749         priv->nr = i;
2750         return priv;
2751
2752 err_deinit:
2753         if (quirk->exit)
2754                 quirk->exit(dev);
2755 err_out:
2756         return priv;
2757 }
2758 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2759
2760 void pciserial_remove_ports(struct serial_private *priv)
2761 {
2762         struct pci_serial_quirk *quirk;
2763         int i;
2764
2765         for (i = 0; i < priv->nr; i++)
2766                 serial8250_unregister_port(priv->line[i]);
2767
2768         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2769                 if (priv->remapped_bar[i])
2770                         iounmap(priv->remapped_bar[i]);
2771                 priv->remapped_bar[i] = NULL;
2772         }
2773
2774         /*
2775          * Find the exit quirks.
2776          */
2777         quirk = find_quirk(priv->dev);
2778         if (quirk->exit)
2779                 quirk->exit(priv->dev);
2780
2781         kfree(priv);
2782 }
2783 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2784
2785 void pciserial_suspend_ports(struct serial_private *priv)
2786 {
2787         int i;
2788
2789         for (i = 0; i < priv->nr; i++)
2790                 if (priv->line[i] >= 0)
2791                         serial8250_suspend_port(priv->line[i]);
2792 }
2793 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2794
2795 void pciserial_resume_ports(struct serial_private *priv)
2796 {
2797         int i;
2798
2799         /*
2800          * Ensure that the board is correctly configured.
2801          */
2802         if (priv->quirk->init)
2803                 priv->quirk->init(priv->dev);
2804
2805         for (i = 0; i < priv->nr; i++)
2806                 if (priv->line[i] >= 0)
2807                         serial8250_resume_port(priv->line[i]);
2808 }
2809 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2810
2811 /*
2812  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2813  * to the arrangement of serial ports on a PCI card.
2814  */
2815 static int __devinit
2816 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2817 {
2818         struct pci_serial_quirk *quirk;
2819         struct serial_private *priv;
2820         const struct pciserial_board *board;
2821         struct pciserial_board tmp;
2822         int rc;
2823
2824         quirk = find_quirk(dev);
2825         if (quirk->probe) {
2826                 rc = quirk->probe(dev);
2827                 if (rc)
2828                         return rc;
2829         }
2830
2831         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2832                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2833                         ent->driver_data);
2834                 return -EINVAL;
2835         }
2836
2837         board = &pci_boards[ent->driver_data];
2838
2839         rc = pci_enable_device(dev);
2840         pci_save_state(dev);
2841         if (rc)
2842                 return rc;
2843
2844         if (ent->driver_data == pbn_default) {
2845                 /*
2846                  * Use a copy of the pci_board entry for this;
2847                  * avoid changing entries in the table.
2848                  */
2849                 memcpy(&tmp, board, sizeof(struct pciserial_board));
2850                 board = &tmp;
2851
2852                 /*
2853                  * We matched one of our class entries.  Try to
2854                  * determine the parameters of this board.
2855                  */
2856                 rc = serial_pci_guess_board(dev, &tmp);
2857                 if (rc)
2858                         goto disable;
2859         } else {
2860                 /*
2861                  * We matched an explicit entry.  If we are able to
2862                  * detect this boards settings with our heuristic,
2863                  * then we no longer need this entry.
2864                  */
2865                 memcpy(&tmp, &pci_boards[pbn_default],
2866                        sizeof(struct pciserial_board));
2867                 rc = serial_pci_guess_board(dev, &tmp);
2868                 if (rc == 0 && serial_pci_matches(board, &tmp))
2869                         moan_device("Redundant entry in serial pci_table.",
2870                                     dev);
2871         }
2872
2873         priv = pciserial_init_ports(dev, board);
2874         if (!IS_ERR(priv)) {
2875                 pci_set_drvdata(dev, priv);
2876                 return 0;
2877         }
2878
2879         rc = PTR_ERR(priv);
2880
2881  disable:
2882         pci_disable_device(dev);
2883         return rc;
2884 }
2885
2886 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2887 {
2888         struct serial_private *priv = pci_get_drvdata(dev);
2889
2890         pci_set_drvdata(dev, NULL);
2891
2892         pciserial_remove_ports(priv);
2893
2894         pci_disable_device(dev);
2895 }
2896
2897 #ifdef CONFIG_PM
2898 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2899 {
2900         struct serial_private *priv = pci_get_drvdata(dev);
2901
2902         if (priv)
2903                 pciserial_suspend_ports(priv);
2904
2905         pci_save_state(dev);
2906         pci_set_power_state(dev, pci_choose_state(dev, state));
2907         return 0;
2908 }
2909
2910 static int pciserial_resume_one(struct pci_dev *dev)
2911 {
2912         int err;
2913         struct serial_private *priv = pci_get_drvdata(dev);
2914
2915         pci_set_power_state(dev, PCI_D0);
2916         pci_restore_state(dev);
2917
2918         if (priv) {
2919                 /*
2920                  * The device may have been disabled.  Re-enable it.
2921                  */
2922                 err = pci_enable_device(dev);
2923                 /* FIXME: We cannot simply error out here */
2924                 if (err)
2925                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2926                 pciserial_resume_ports(priv);
2927         }
2928         return 0;
2929 }
2930 #endif
2931
2932 static struct pci_device_id serial_pci_tbl[] = {
2933         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2934         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2935                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2936                 pbn_b2_8_921600 },
2937         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2938                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2939                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2940                 pbn_b1_8_1382400 },
2941         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2942                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2943                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2944                 pbn_b1_4_1382400 },
2945         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2946                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2947                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2948                 pbn_b1_2_1382400 },
2949         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2950                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2951                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2952                 pbn_b1_8_1382400 },
2953         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2954                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2955                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2956                 pbn_b1_4_1382400 },
2957         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2958                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2959                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2960                 pbn_b1_2_1382400 },
2961         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2962                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2963                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2964                 pbn_b1_8_921600 },
2965         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2966                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2967                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2968                 pbn_b1_8_921600 },
2969         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2970                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2971                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2972                 pbn_b1_4_921600 },
2973         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2974                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2975                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2976                 pbn_b1_4_921600 },
2977         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2978                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2979                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2980                 pbn_b1_2_921600 },
2981         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2982                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2983                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2984                 pbn_b1_8_921600 },
2985         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2986                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2987                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2988                 pbn_b1_8_921600 },
2989         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2990                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2991                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2992                 pbn_b1_4_921600 },
2993         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2994                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2995                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2996                 pbn_b1_2_1250000 },
2997         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2998                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2999                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3000                 pbn_b0_2_1843200 },
3001         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3002                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3003                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3004                 pbn_b0_4_1843200 },
3005         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3006                 PCI_VENDOR_ID_AFAVLAB,
3007                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3008                 pbn_b0_4_1152000 },
3009         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3010                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3011                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3012                 pbn_b0_2_1843200_200 },
3013         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3014                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3015                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3016                 pbn_b0_4_1843200_200 },
3017         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3018                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3019                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3020                 pbn_b0_8_1843200_200 },
3021         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3022                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3023                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3024                 pbn_b0_2_1843200_200 },
3025         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3026                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3027                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3028                 pbn_b0_4_1843200_200 },
3029         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3030                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3031                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3032                 pbn_b0_8_1843200_200 },
3033         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3034                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3035                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3036                 pbn_b0_2_1843200_200 },
3037         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3038                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3039                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3040                 pbn_b0_4_1843200_200 },
3041         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3042                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3043                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3044                 pbn_b0_8_1843200_200 },
3045         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3046                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3047                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3048                 pbn_b0_2_1843200_200 },
3049         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3050                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3051                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3052                 pbn_b0_4_1843200_200 },
3053         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3054                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3055                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3056                 pbn_b0_8_1843200_200 },
3057         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3058                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3059                 0, 0, pbn_exar_ibm_saturn },
3060
3061         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3062                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3063                 pbn_b2_bt_1_115200 },
3064         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3065                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3066                 pbn_b2_bt_2_115200 },
3067         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3068                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3069                 pbn_b2_bt_4_115200 },
3070         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3071                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3072                 pbn_b2_bt_2_115200 },
3073         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3074                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3075                 pbn_b2_bt_4_115200 },
3076         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3077                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3078                 pbn_b2_8_115200 },
3079         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3080                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3081                 pbn_b2_8_460800 },
3082         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3083                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3084                 pbn_b2_8_115200 },
3085
3086         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3087                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3088                 pbn_b2_bt_2_115200 },
3089         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3090                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3091                 pbn_b2_bt_2_921600 },
3092         /*
3093          * VScom SPCOM800, from sl@s.pl
3094          */
3095         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3096                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3097                 pbn_b2_8_921600 },
3098         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3099                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3100                 pbn_b2_4_921600 },
3101         /* Unknown card - subdevice 0x1584 */
3102         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3103                 PCI_VENDOR_ID_PLX,
3104                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3105                 pbn_b0_4_115200 },
3106         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3107                 PCI_SUBVENDOR_ID_KEYSPAN,
3108                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3109                 pbn_panacom },
3110         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3111                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3112                 pbn_panacom4 },
3113         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3114                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3115                 pbn_panacom2 },
3116         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3117                 PCI_VENDOR_ID_ESDGMBH,
3118                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3119                 pbn_b2_4_115200 },
3120         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3121                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3122                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3123                 pbn_b2_4_460800 },
3124         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3125                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3126                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3127                 pbn_b2_8_460800 },
3128         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3129                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3130                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3131                 pbn_b2_16_460800 },
3132         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3133                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3134                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3135                 pbn_b2_16_460800 },
3136         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3137                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3138                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3139                 pbn_b2_4_460800 },
3140         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3141                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3142                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3143                 pbn_b2_8_460800 },
3144         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3145                 PCI_SUBVENDOR_ID_EXSYS,
3146                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3147                 pbn_exsys_4055 },
3148         /*
3149          * Megawolf Romulus PCI Serial Card, from Mike Hudson
3150          * (Exoray@isys.ca)
3151          */
3152         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3153                 0x10b5, 0x106a, 0, 0,
3154                 pbn_plx_romulus },
3155         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3156                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3157                 pbn_b1_4_115200 },
3158         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3159                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3160                 pbn_b1_2_115200 },
3161         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3162                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3163                 pbn_b1_8_115200 },
3164         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3165                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3166                 pbn_b1_8_115200 },
3167         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3168                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3169                 0, 0,
3170                 pbn_b0_4_921600 },
3171         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3172                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3173                 0, 0,
3174                 pbn_b0_4_1152000 },
3175         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
3176                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3177                 pbn_b0_bt_2_921600 },
3178
3179                 /*
3180                  * The below card is a little controversial since it is the
3181                  * subject of a PCI vendor/device ID clash.  (See
3182                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3183                  * For now just used the hex ID 0x950a.
3184                  */
3185         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3186                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3187                 pbn_b0_2_115200 },
3188         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3189                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3190                 pbn_b0_2_1130000 },
3191         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3192                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3193                 pbn_b0_1_921600 },
3194         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3195                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3196                 pbn_b0_4_115200 },
3197         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3198                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3199                 pbn_b0_bt_2_921600 },
3200         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3201                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3202                 pbn_b2_8_1152000 },
3203
3204         /*
3205          * Oxford Semiconductor Inc. Tornado PCI express device range.
3206          */
3207         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
3208                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3209                 pbn_b0_1_4000000 },
3210         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
3211                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3212                 pbn_b0_1_4000000 },
3213         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
3214                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3215                 pbn_oxsemi_1_4000000 },
3216         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
3217                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3218                 pbn_oxsemi_1_4000000 },
3219         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
3220                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3221                 pbn_b0_1_4000000 },
3222         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
3223                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3224                 pbn_b0_1_4000000 },
3225         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
3226                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3227                 pbn_oxsemi_1_4000000 },
3228         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
3229                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3230                 pbn_oxsemi_1_4000000 },
3231         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
3232                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3233                 pbn_b0_1_4000000 },
3234         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
3235                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3236                 pbn_b0_1_4000000 },
3237         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
3238                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3239                 pbn_b0_1_4000000 },
3240         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
3241                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3242                 pbn_b0_1_4000000 },
3243         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
3244                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3245                 pbn_oxsemi_2_4000000 },
3246         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
3247                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3248                 pbn_oxsemi_2_4000000 },
3249         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
3250                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3251                 pbn_oxsemi_4_4000000 },
3252         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
3253                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3254                 pbn_oxsemi_4_4000000 },
3255         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
3256                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3257                 pbn_oxsemi_8_4000000 },
3258         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
3259                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3260                 pbn_oxsemi_8_4000000 },
3261         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
3262                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3263                 pbn_oxsemi_1_4000000 },
3264         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
3265                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3266                 pbn_oxsemi_1_4000000 },
3267         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
3268                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3269                 pbn_oxsemi_1_4000000 },
3270         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
3271                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3272                 pbn_oxsemi_1_4000000 },
3273         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
3274                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3275                 pbn_oxsemi_1_4000000 },
3276         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
3277                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3278                 pbn_oxsemi_1_4000000 },
3279         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
3280                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3281                 pbn_oxsemi_1_4000000 },
3282         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
3283                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3284                 pbn_oxsemi_1_4000000 },
3285         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
3286                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3287                 pbn_oxsemi_1_4000000 },
3288         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
3289                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3290                 pbn_oxsemi_1_4000000 },
3291         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
3292                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3293                 pbn_oxsemi_1_4000000 },
3294         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
3295                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3296                 pbn_oxsemi_1_4000000 },
3297         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
3298                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3299                 pbn_oxsemi_1_4000000 },
3300         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
3301                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3302                 pbn_oxsemi_1_4000000 },
3303         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
3304                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3305                 pbn_oxsemi_1_4000000 },
3306         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
3307                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3308                 pbn_oxsemi_1_4000000 },
3309         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
3310                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3311                 pbn_oxsemi_1_4000000 },
3312         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
3313                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3314                 pbn_oxsemi_1_4000000 },
3315         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
3316                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3317                 pbn_oxsemi_1_4000000 },
3318         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
3319                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3320                 pbn_oxsemi_1_4000000 },
3321         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
3322                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3323                 pbn_oxsemi_1_4000000 },
3324         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
3325                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3326                 pbn_oxsemi_1_4000000 },
3327         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
3328                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3329                 pbn_oxsemi_1_4000000 },
3330         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
3331                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3332                 pbn_oxsemi_1_4000000 },
3333         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
3334                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3335                 pbn_oxsemi_1_4000000 },
3336         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
3337                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3338                 pbn_oxsemi_1_4000000 },
3339         /*
3340          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3341          */
3342         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3343                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3344                 pbn_oxsemi_1_4000000 },
3345         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3346                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3347                 pbn_oxsemi_2_4000000 },
3348         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3349                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3350                 pbn_oxsemi_4_4000000 },
3351         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3352                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3353                 pbn_oxsemi_8_4000000 },
3354
3355         /*
3356          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3357          */
3358         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3359                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3360                 pbn_oxsemi_2_4000000 },
3361
3362         /*
3363          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3364          * from skokodyn@yahoo.com
3365          */
3366         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3367                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3368                 pbn_sbsxrsio },
3369         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3370                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3371                 pbn_sbsxrsio },
3372         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3373                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3374                 pbn_sbsxrsio },
3375         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3376                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3377                 pbn_sbsxrsio },
3378
3379         /*
3380          * Digitan DS560-558, from jimd@esoft.com
3381          */
3382         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3383                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3384                 pbn_b1_1_115200 },
3385
3386         /*
3387          * Titan Electronic cards
3388          *  The 400L and 800L have a custom setup quirk.
3389          */
3390         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3391                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3392                 pbn_b0_1_921600 },
3393         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3394                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3395                 pbn_b0_2_921600 },
3396         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3397                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3398                 pbn_b0_4_921600 },
3399         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3400                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3401                 pbn_b0_4_921600 },
3402         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3403                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3404                 pbn_b1_1_921600 },
3405         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3406                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3407                 pbn_b1_bt_2_921600 },
3408         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3409                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3410                 pbn_b0_bt_4_921600 },
3411         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3412                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3413                 pbn_b0_bt_8_921600 },
3414         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3415                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3416                 pbn_b4_bt_2_921600 },
3417         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3418                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3419                 pbn_b4_bt_4_921600 },
3420         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3421                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3422                 pbn_b4_bt_8_921600 },
3423         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3424                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3425                 pbn_b0_4_921600 },
3426         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3427                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3428                 pbn_b0_4_921600 },
3429         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3430                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3431                 pbn_b0_4_921600 },
3432         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3433                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3434                 pbn_oxsemi_1_4000000 },
3435         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3436                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3437                 pbn_oxsemi_2_4000000 },
3438         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3439                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3440                 pbn_oxsemi_4_4000000 },
3441         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3442                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3443                 pbn_oxsemi_8_4000000 },
3444         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3445                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3446                 pbn_oxsemi_2_4000000 },
3447         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3448                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3449                 pbn_oxsemi_2_4000000 },
3450         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
3451                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3452                 pbn_b0_4_921600 },
3453         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
3454                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3455                 pbn_b0_4_921600 },
3456         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
3457                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3458                 pbn_b0_4_921600 },
3459         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
3460                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3461                 pbn_b0_4_921600 },
3462
3463         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3464                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3465                 pbn_b2_1_460800 },
3466         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3467                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3468                 pbn_b2_1_460800 },
3469         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3470                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3471                 pbn_b2_1_460800 },
3472         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3473                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3474                 pbn_b2_bt_2_921600 },
3475         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3476                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3477                 pbn_b2_bt_2_921600 },
3478         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3479                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3480                 pbn_b2_bt_2_921600 },
3481         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3482                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3483                 pbn_b2_bt_4_921600 },
3484         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3485                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3486                 pbn_b2_bt_4_921600 },
3487         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3488                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3489                 pbn_b2_bt_4_921600 },
3490         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3491                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3492                 pbn_b0_1_921600 },
3493         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3494                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3495                 pbn_b0_1_921600 },
3496         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3497                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3498                 pbn_b0_1_921600 },
3499         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3500                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3501                 pbn_b0_bt_2_921600 },
3502         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3503                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3504                 pbn_b0_bt_2_921600 },
3505         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3506                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3507                 pbn_b0_bt_2_921600 },
3508         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3509                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3510                 pbn_b0_bt_4_921600 },
3511         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3512                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3513                 pbn_b0_bt_4_921600 },
3514         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3515                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3516                 pbn_b0_bt_4_921600 },
3517         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3518                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3519                 pbn_b0_bt_8_921600 },
3520         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3521                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3522                 pbn_b0_bt_8_921600 },
3523         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3524                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3525                 pbn_b0_bt_8_921600 },
3526
3527         /*
3528          * Computone devices submitted by Doug McNash dmcnash@computone.com
3529          */
3530         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3531                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3532                 0, 0, pbn_computone_4 },
3533         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3534                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3535                 0, 0, pbn_computone_8 },
3536         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3537                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3538                 0, 0, pbn_computone_6 },
3539
3540         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3541                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3542                 pbn_oxsemi },
3543         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3544                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3545                 pbn_b0_bt_1_921600 },
3546
3547         /*
3548          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3549          */
3550         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3551                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3552                 pbn_b0_bt_8_115200 },
3553         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3554                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3555                 pbn_b0_bt_8_115200 },
3556
3557         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3558                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3559                 pbn_b0_bt_2_115200 },
3560         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3561                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3562                 pbn_b0_bt_2_115200 },
3563         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3564                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3565                 pbn_b0_bt_2_115200 },
3566         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3567                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3568                 pbn_b0_bt_2_115200 },
3569         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3570                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3571                 pbn_b0_bt_2_115200 },
3572         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3573                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3574                 pbn_b0_bt_4_460800 },
3575         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3576                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3577                 pbn_b0_bt_4_460800 },
3578         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3579                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3580                 pbn_b0_bt_2_460800 },
3581         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3582                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3583                 pbn_b0_bt_2_460800 },
3584         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3585                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3586                 pbn_b0_bt_2_460800 },
3587         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3588                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3589                 pbn_b0_bt_1_115200 },
3590         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3591                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3592                 pbn_b0_bt_1_460800 },
3593
3594         /*
3595          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3596          * Cards are identified by their subsystem vendor IDs, which
3597          * (in hex) match the model number.
3598          *
3599          * Note that JC140x are RS422/485 cards which require ox950
3600          * ACR = 0x10, and as such are not currently fully supported.
3601          */
3602         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3603                 0x1204, 0x0004, 0, 0,
3604                 pbn_b0_4_921600 },
3605         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3606                 0x1208, 0x0004, 0, 0,
3607                 pbn_b0_4_921600 },
3608 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3609                 0x1402, 0x0002, 0, 0,
3610                 pbn_b0_2_921600 }, */
3611 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3612                 0x1404, 0x0004, 0, 0,
3613                 pbn_b0_4_921600 }, */
3614         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3615                 0x1208, 0x0004, 0, 0,
3616                 pbn_b0_4_921600 },
3617
3618         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3619                 0x1204, 0x0004, 0, 0,
3620                 pbn_b0_4_921600 },
3621         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3622                 0x1208, 0x0004, 0, 0,
3623                 pbn_b0_4_921600 },
3624         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3625                 0x1208, 0x0004, 0, 0,
3626                 pbn_b0_4_921600 },
3627         /*
3628          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3629          */
3630         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3631                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3632                 pbn_b1_1_1382400 },
3633
3634         /*
3635          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3636          */
3637         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3638                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3639                 pbn_b1_1_1382400 },
3640
3641         /*
3642          * RAStel 2 port modem, gerg@moreton.com.au
3643          */
3644         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3645                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3646                 pbn_b2_bt_2_115200 },
3647
3648         /*
3649          * EKF addition for i960 Boards form EKF with serial port
3650          */
3651         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3652                 0xE4BF, PCI_ANY_ID, 0, 0,
3653                 pbn_intel_i960 },
3654
3655         /*
3656          * Xircom Cardbus/Ethernet combos
3657          */
3658         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3659                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3660                 pbn_b0_1_115200 },
3661         /*
3662          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3663          */
3664         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3665                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3666                 pbn_b0_1_115200 },
3667
3668         /*
3669          * Untested PCI modems, sent in from various folks...
3670          */
3671
3672         /*
3673          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3674          */
3675         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
3676                 0x1048, 0x1500, 0, 0,
3677                 pbn_b1_1_115200 },
3678
3679         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3680                 0xFF00, 0, 0, 0,
3681                 pbn_sgi_ioc3 },
3682
3683         /*
3684          * HP Diva card
3685          */
3686         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3687                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3688                 pbn_b1_1_115200 },
3689         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3690                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3691                 pbn_b0_5_115200 },
3692         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3693                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3694                 pbn_b2_1_115200 },
3695
3696         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3697                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3698                 pbn_b3_2_115200 },
3699         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3700                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3701                 pbn_b3_4_115200 },
3702         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3703                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3704                 pbn_b3_8_115200 },
3705
3706         /*
3707          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3708          */
3709         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3710                 PCI_ANY_ID, PCI_ANY_ID,
3711                 0,
3712                 0, pbn_exar_XR17C152 },
3713         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3714                 PCI_ANY_ID, PCI_ANY_ID,
3715                 0,
3716                 0, pbn_exar_XR17C154 },
3717         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3718                 PCI_ANY_ID, PCI_ANY_ID,
3719                 0,
3720                 0, pbn_exar_XR17C158 },
3721
3722         /*
3723          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3724          */
3725         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3726                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3727                 pbn_b0_1_115200 },
3728         /*
3729          * ITE
3730          */
3731         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3732                 PCI_ANY_ID, PCI_ANY_ID,
3733                 0, 0,
3734                 pbn_b1_bt_1_115200 },
3735
3736         /*
3737          * IntaShield IS-200
3738          */
3739         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3740                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
3741                 pbn_b2_2_115200 },
3742         /*
3743          * IntaShield IS-400
3744          */
3745         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3746                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
3747                 pbn_b2_4_115200 },
3748         /*
3749          * Perle PCI-RAS cards
3750          */
3751         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3752                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3753                 0, 0, pbn_b2_4_921600 },
3754         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3755                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3756                 0, 0, pbn_b2_8_921600 },
3757
3758         /*
3759          * Mainpine series cards: Fairly standard layout but fools
3760          * parts of the autodetect in some cases and uses otherwise
3761          * unmatched communications subclasses in the PCI Express case
3762          */
3763
3764         {       /* RockForceDUO */
3765                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3766                 PCI_VENDOR_ID_MAINPINE, 0x0200,
3767                 0, 0, pbn_b0_2_115200 },
3768         {       /* RockForceQUATRO */
3769                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3770                 PCI_VENDOR_ID_MAINPINE, 0x0300,
3771                 0, 0, pbn_b0_4_115200 },
3772         {       /* RockForceDUO+ */
3773                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3774                 PCI_VENDOR_ID_MAINPINE, 0x0400,
3775                 0, 0, pbn_b0_2_115200 },
3776         {       /* RockForceQUATRO+ */
3777                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3778                 PCI_VENDOR_ID_MAINPINE, 0x0500,
3779                 0, 0, pbn_b0_4_115200 },
3780         {       /* RockForce+ */
3781                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3782                 PCI_VENDOR_ID_MAINPINE, 0x0600,
3783                 0, 0, pbn_b0_2_115200 },
3784         {       /* RockForce+ */
3785                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3786                 PCI_VENDOR_ID_MAINPINE, 0x0700,
3787                 0, 0, pbn_b0_4_115200 },
3788         {       /* RockForceOCTO+ */
3789                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3790                 PCI_VENDOR_ID_MAINPINE, 0x0800,
3791                 0, 0, pbn_b0_8_115200 },
3792         {       /* RockForceDUO+ */
3793                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3794                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3795                 0, 0, pbn_b0_2_115200 },
3796         {       /* RockForceQUARTRO+ */
3797                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3798                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3799                 0, 0, pbn_b0_4_115200 },
3800         {       /* RockForceOCTO+ */
3801                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3802                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3803                 0, 0, pbn_b0_8_115200 },
3804         {       /* RockForceD1 */
3805                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3806                 PCI_VENDOR_ID_MAINPINE, 0x2000,
3807                 0, 0, pbn_b0_1_115200 },
3808         {       /* RockForceF1 */
3809                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3810                 PCI_VENDOR_ID_MAINPINE, 0x2100,
3811                 0, 0, pbn_b0_1_115200 },
3812         {       /* RockForceD2 */
3813                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3814                 PCI_VENDOR_ID_MAINPINE, 0x2200,
3815                 0, 0, pbn_b0_2_115200 },
3816         {       /* RockForceF2 */
3817                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3818                 PCI_VENDOR_ID_MAINPINE, 0x2300,
3819                 0, 0, pbn_b0_2_115200 },
3820         {       /* RockForceD4 */
3821                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3822                 PCI_VENDOR_ID_MAINPINE, 0x2400,
3823                 0, 0, pbn_b0_4_115200 },
3824         {       /* RockForceF4 */
3825                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3826                 PCI_VENDOR_ID_MAINPINE, 0x2500,
3827                 0, 0, pbn_b0_4_115200 },
3828         {       /* RockForceD8 */
3829                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3830                 PCI_VENDOR_ID_MAINPINE, 0x2600,
3831                 0, 0, pbn_b0_8_115200 },
3832         {       /* RockForceF8 */
3833                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3834                 PCI_VENDOR_ID_MAINPINE, 0x2700,
3835                 0, 0, pbn_b0_8_115200 },
3836         {       /* IQ Express D1 */
3837                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3838                 PCI_VENDOR_ID_MAINPINE, 0x3000,
3839                 0, 0, pbn_b0_1_115200 },
3840         {       /* IQ Express F1 */
3841                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3842                 PCI_VENDOR_ID_MAINPINE, 0x3100,
3843                 0, 0, pbn_b0_1_115200 },
3844         {       /* IQ Express D2 */
3845                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3846                 PCI_VENDOR_ID_MAINPINE, 0x3200,
3847                 0, 0, pbn_b0_2_115200 },
3848         {       /* IQ Express F2 */
3849                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3850                 PCI_VENDOR_ID_MAINPINE, 0x3300,
3851                 0, 0, pbn_b0_2_115200 },
3852         {       /* IQ Express D4 */
3853                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3854                 PCI_VENDOR_ID_MAINPINE, 0x3400,
3855                 0, 0, pbn_b0_4_115200 },
3856         {       /* IQ Express F4 */
3857                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3858                 PCI_VENDOR_ID_MAINPINE, 0x3500,
3859                 0, 0, pbn_b0_4_115200 },
3860         {       /* IQ Express D8 */
3861                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3862                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3863                 0, 0, pbn_b0_8_115200 },
3864         {       /* IQ Express F8 */
3865                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3866                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3867                 0, 0, pbn_b0_8_115200 },
3868
3869
3870         /*
3871          * PA Semi PA6T-1682M on-chip UART
3872          */
3873         {       PCI_VENDOR_ID_PASEMI, 0xa004,
3874                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3875                 pbn_pasemi_1682M },
3876
3877         /*
3878          * National Instruments
3879          */
3880         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3881                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3882                 pbn_b1_16_115200 },
3883         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3884                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3885                 pbn_b1_8_115200 },
3886         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3887                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3888                 pbn_b1_bt_4_115200 },
3889         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3890                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3891                 pbn_b1_bt_2_115200 },
3892         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3893                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3894                 pbn_b1_bt_4_115200 },
3895         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3896                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3897                 pbn_b1_bt_2_115200 },
3898         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3899                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3900                 pbn_b1_16_115200 },
3901         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3902                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3903                 pbn_b1_8_115200 },
3904         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3905                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3906                 pbn_b1_bt_4_115200 },
3907         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3908                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3909                 pbn_b1_bt_2_115200 },
3910         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3911                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3912                 pbn_b1_bt_4_115200 },
3913         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3914                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3915                 pbn_b1_bt_2_115200 },
3916         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3917                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3918                 pbn_ni8430_2 },
3919         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3920                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3921                 pbn_ni8430_2 },
3922         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3923                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3924                 pbn_ni8430_4 },
3925         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3926                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3927                 pbn_ni8430_4 },
3928         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3929                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3930                 pbn_ni8430_8 },
3931         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3932                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3933                 pbn_ni8430_8 },
3934         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3935                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3936                 pbn_ni8430_16 },
3937         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3938                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3939                 pbn_ni8430_16 },
3940         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3941                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3942                 pbn_ni8430_2 },
3943         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3944                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3945                 pbn_ni8430_2 },
3946         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3947                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3948                 pbn_ni8430_4 },
3949         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3950                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3951                 pbn_ni8430_4 },
3952
3953         /*
3954         * ADDI-DATA GmbH communication cards <info@addi-data.com>
3955         */
3956         {       PCI_VENDOR_ID_ADDIDATA,
3957                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3958                 PCI_ANY_ID,
3959                 PCI_ANY_ID,
3960                 0,
3961                 0,
3962                 pbn_b0_4_115200 },
3963
3964         {       PCI_VENDOR_ID_ADDIDATA,
3965                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3966                 PCI_ANY_ID,
3967                 PCI_ANY_ID,
3968                 0,
3969                 0,
3970                 pbn_b0_2_115200 },
3971
3972         {       PCI_VENDOR_ID_ADDIDATA,
3973                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3974                 PCI_ANY_ID,
3975                 PCI_ANY_ID,
3976                 0,
3977                 0,
3978                 pbn_b0_1_115200 },
3979
3980         {       PCI_VENDOR_ID_ADDIDATA_OLD,
3981                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3982                 PCI_ANY_ID,
3983                 PCI_ANY_ID,
3984                 0,
3985                 0,
3986                 pbn_b1_8_115200 },
3987
3988         {       PCI_VENDOR_ID_ADDIDATA,
3989                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3990                 PCI_ANY_ID,
3991                 PCI_ANY_ID,
3992                 0,
3993                 0,
3994                 pbn_b0_4_115200 },
3995
3996         {       PCI_VENDOR_ID_ADDIDATA,
3997                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3998                 PCI_ANY_ID,
3999                 PCI_ANY_ID,
4000                 0,
4001                 0,
4002                 pbn_b0_2_115200 },
4003
4004         {       PCI_VENDOR_ID_ADDIDATA,
4005                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4006                 PCI_ANY_ID,
4007                 PCI_ANY_ID,
4008                 0,
4009                 0,
4010                 pbn_b0_1_115200 },
4011
4012         {       PCI_VENDOR_ID_ADDIDATA,
4013                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4014                 PCI_ANY_ID,
4015                 PCI_ANY_ID,
4016                 0,
4017                 0,
4018                 pbn_b0_4_115200 },
4019
4020         {       PCI_VENDOR_ID_ADDIDATA,
4021                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4022                 PCI_ANY_ID,
4023                 PCI_ANY_ID,
4024                 0,
4025                 0,
4026                 pbn_b0_2_115200 },
4027
4028         {       PCI_VENDOR_ID_ADDIDATA,
4029                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4030                 PCI_ANY_ID,
4031                 PCI_ANY_ID,
4032                 0,
4033                 0,
4034                 pbn_b0_1_115200 },
4035
4036         {       PCI_VENDOR_ID_ADDIDATA,
4037                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4038                 PCI_ANY_ID,
4039                 PCI_ANY_ID,
4040                 0,
4041                 0,
4042                 pbn_b0_8_115200 },
4043
4044         {       PCI_VENDOR_ID_ADDIDATA,
4045                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4046                 PCI_ANY_ID,
4047                 PCI_ANY_ID,
4048                 0,
4049                 0,
4050                 pbn_ADDIDATA_PCIe_4_3906250 },
4051
4052         {       PCI_VENDOR_ID_ADDIDATA,
4053                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4054                 PCI_ANY_ID,
4055                 PCI_ANY_ID,
4056                 0,
4057                 0,
4058                 pbn_ADDIDATA_PCIe_2_3906250 },
4059
4060         {       PCI_VENDOR_ID_ADDIDATA,
4061                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4062                 PCI_ANY_ID,
4063                 PCI_ANY_ID,
4064                 0,
4065                 0,
4066                 pbn_ADDIDATA_PCIe_1_3906250 },
4067
4068         {       PCI_VENDOR_ID_ADDIDATA,
4069                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4070                 PCI_ANY_ID,
4071                 PCI_ANY_ID,
4072                 0,
4073                 0,
4074                 pbn_ADDIDATA_PCIe_8_3906250 },
4075
4076         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4077                 PCI_VENDOR_ID_IBM, 0x0299,
4078                 0, 0, pbn_b0_bt_2_115200 },
4079
4080         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4081                 0xA000, 0x1000,
4082                 0, 0, pbn_b0_1_115200 },
4083
4084         /* the 9901 is a rebranded 9912 */
4085         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4086                 0xA000, 0x1000,
4087                 0, 0, pbn_b0_1_115200 },
4088
4089         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4090                 0xA000, 0x1000,
4091                 0, 0, pbn_b0_1_115200 },
4092
4093         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4094                 0xA000, 0x1000,
4095                 0, 0, pbn_b0_1_115200 },
4096
4097         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4098                 0xA000, 0x1000,
4099                 0, 0, pbn_b0_1_115200 },
4100
4101         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4102                 0xA000, 0x3002,
4103                 0, 0, pbn_NETMOS9900_2s_115200 },
4104
4105         /*
4106          * Best Connectivity and Rosewill PCI Multi I/O cards
4107          */
4108
4109         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4110                 0xA000, 0x1000,
4111                 0, 0, pbn_b0_1_115200 },
4112
4113         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4114                 0xA000, 0x3002,
4115                 0, 0, pbn_b0_bt_2_115200 },
4116
4117         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4118                 0xA000, 0x3004,
4119                 0, 0, pbn_b0_bt_4_115200 },
4120         /* Intel CE4100 */
4121         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4122                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
4123                 pbn_ce4100_1_115200 },
4124
4125         /*
4126          * Cronyx Omega PCI
4127          */
4128         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4129                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4130                 pbn_omegapci },
4131
4132         /*
4133          * These entries match devices with class COMMUNICATION_SERIAL,
4134          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4135          */
4136         {       PCI_ANY_ID, PCI_ANY_ID,
4137                 PCI_ANY_ID, PCI_ANY_ID,
4138                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4139                 0xffff00, pbn_default },
4140         {       PCI_ANY_ID, PCI_ANY_ID,
4141                 PCI_ANY_ID, PCI_ANY_ID,
4142                 PCI_CLASS_COMMUNICATION_MODEM << 8,
4143                 0xffff00, pbn_default },
4144         {       PCI_ANY_ID, PCI_ANY_ID,
4145                 PCI_ANY_ID, PCI_ANY_ID,
4146                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4147                 0xffff00, pbn_default },
4148         { 0, }
4149 };
4150
4151 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4152                                                 pci_channel_state_t state)
4153 {
4154         struct serial_private *priv = pci_get_drvdata(dev);
4155
4156         if (state == pci_channel_io_perm_failure)
4157                 return PCI_ERS_RESULT_DISCONNECT;
4158
4159         if (priv)
4160                 pciserial_suspend_ports(priv);
4161
4162         pci_disable_device(dev);
4163
4164         return PCI_ERS_RESULT_NEED_RESET;
4165 }
4166
4167 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4168 {
4169         int rc;
4170
4171         rc = pci_enable_device(dev);
4172
4173         if (rc)
4174                 return PCI_ERS_RESULT_DISCONNECT;
4175
4176         pci_restore_state(dev);
4177         pci_save_state(dev);
4178
4179         return PCI_ERS_RESULT_RECOVERED;
4180 }
4181
4182 static void serial8250_io_resume(struct pci_dev *dev)
4183 {
4184         struct serial_private *priv = pci_get_drvdata(dev);
4185
4186         if (priv)
4187                 pciserial_resume_ports(priv);
4188 }
4189
4190 static struct pci_error_handlers serial8250_err_handler = {
4191         .error_detected = serial8250_io_error_detected,
4192         .slot_reset = serial8250_io_slot_reset,
4193         .resume = serial8250_io_resume,
4194 };
4195
4196 static struct pci_driver serial_pci_driver = {
4197         .name           = "serial",
4198         .probe          = pciserial_init_one,
4199         .remove         = __devexit_p(pciserial_remove_one),
4200 #ifdef CONFIG_PM
4201         .suspend        = pciserial_suspend_one,
4202         .resume         = pciserial_resume_one,
4203 #endif
4204         .id_table       = serial_pci_tbl,
4205         .err_handler    = &serial8250_err_handler,
4206 };
4207
4208 static int __init serial8250_pci_init(void)
4209 {
4210         return pci_register_driver(&serial_pci_driver);
4211 }
4212
4213 static void __exit serial8250_pci_exit(void)
4214 {
4215         pci_unregister_driver(&serial_pci_driver);
4216 }
4217
4218 module_init(serial8250_pci_init);
4219 module_exit(serial8250_pci_exit);
4220
4221 MODULE_LICENSE("GPL");
4222 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4223 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);