drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/of.h>
  30 #include <linux/of_gpio.h>
  31 #include <linux/of_device.h>
  32 #include <linux/mmc/host.h>
  33 #include <linux/mmc/core.h>
  34 #include <linux/mmc/mmc.h>
  35 #include <linux/io.h>
  36 #include <linux/semaphore.h>
  37 #include <linux/gpio.h>
  38 #include <linux/regulator/consumer.h>
  39 #include <linux/pm_runtime.h>
  40 #include <plat/dma.h>
  41 #include <mach/hardware.h>
  42 #include <plat/board.h>
  43 #include <plat/mmc.h>
  44 #include <plat/cpu.h>
  45
  46 /* OMAP HSMMC Host Controller Registers */
  47 #define OMAP_HSMMC_SYSCONFIG    0x0010
  48 #define OMAP_HSMMC_SYSSTATUS    0x0014
  49 #define OMAP_HSMMC_CON          0x002C
  50 #define OMAP_HSMMC_BLK          0x0104
  51 #define OMAP_HSMMC_ARG          0x0108
  52 #define OMAP_HSMMC_CMD          0x010C
  53 #define OMAP_HSMMC_RSP10        0x0110
  54 #define OMAP_HSMMC_RSP32        0x0114
  55 #define OMAP_HSMMC_RSP54        0x0118
  56 #define OMAP_HSMMC_RSP76        0x011C
  57 #define OMAP_HSMMC_DATA         0x0120
  58 #define OMAP_HSMMC_HCTL         0x0128
  59 #define OMAP_HSMMC_SYSCTL       0x012C
  60 #define OMAP_HSMMC_STAT         0x0130
  61 #define OMAP_HSMMC_IE           0x0134
  62 #define OMAP_HSMMC_ISE          0x0138
  63 #define OMAP_HSMMC_CAPA         0x0140
  64
  65 #define VS18                    (1 << 26)
  66 #define VS30                    (1 << 25)
  67 #define SDVS18                  (0x5 << 9)
  68 #define SDVS30                  (0x6 << 9)
  69 #define SDVS33                  (0x7 << 9)
  70 #define SDVS_MASK               0x00000E00
  71 #define SDVSCLR                 0xFFFFF1FF
  72 #define SDVSDET                 0x00000400
  73 #define AUTOIDLE                0x1
  74 #define SDBP                    (1 << 8)
  75 #define DTO                     0xe
  76 #define ICE                     0x1
  77 #define ICS                     0x2
  78 #define CEN                     (1 << 2)
  79 #define CLKD_MASK               0x0000FFC0
  80 #define CLKD_SHIFT              6
  81 #define DTO_MASK                0x000F0000
  82 #define DTO_SHIFT               16
  83 #define INT_EN_MASK             0x307F0033
  84 #define BWR_ENABLE              (1 << 4)
  85 #define BRR_ENABLE              (1 << 5)
  86 #define DTO_ENABLE              (1 << 20)
  87 #define INIT_STREAM             (1 << 1)
  88 #define DP_SELECT               (1 << 21)
  89 #define DDIR                    (1 << 4)
  90 #define DMA_EN                  0x1
  91 #define MSBS                    (1 << 5)
  92 #define BCE                     (1 << 1)
  93 #define FOUR_BIT                (1 << 1)
  94 #define DW8                     (1 << 5)
  95 #define CC                      0x1
  96 #define TC                      0x02
  97 #define OD                      0x1
  98 #define ERR                     (1 << 15)
  99 #define CMD_TIMEOUT             (1 << 16)
 100 #define DATA_TIMEOUT            (1 << 20)
 101 #define CMD_CRC                 (1 << 17)
 102 #define DATA_CRC                (1 << 21)
 103 #define CARD_ERR                (1 << 28)
 104 #define STAT_CLEAR              0xFFFFFFFF
 105 #define INIT_STREAM_CMD         0x00000000
 106 #define DUAL_VOLT_OCR_BIT       7
 107 #define SRC                     (1 << 25)
 108 #define SRD                     (1 << 26)
 109 #define SOFTRESET               (1 << 1)
 110 #define RESETDONE               (1 << 0)
 111
 112 #define MMC_AUTOSUSPEND_DELAY   100
 113 #define MMC_TIMEOUT_MS          20
 114 #define OMAP_MMC_MIN_CLOCK      400000
 115 #define OMAP_MMC_MAX_CLOCK      52000000
 116 #define DRIVER_NAME             "omap_hsmmc"
 117
 118 /*
 119  * One controller can have multiple slots, like on some omap boards using
 120  * omap.c controller driver. Luckily this is not currently done on any known
 121  * omap_hsmmc.c device.
 122  */
 123 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 124
 125 /*
 126  * MMC Host controller read/write API's
 127  */
 128 #define OMAP_HSMMC_READ(base, reg)      \
 129         __raw_readl((base) + OMAP_HSMMC_##reg)
 130
 131 #define OMAP_HSMMC_WRITE(base, reg, val) \
 132         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 133
 134 struct omap_hsmmc_next {
 135         unsigned int    dma_len;
 136         s32             cookie;
 137 };
 138
 139 struct omap_hsmmc_host {
 140         struct  device          *dev;
 141         struct  mmc_host        *mmc;
 142         struct  mmc_request     *mrq;
 143         struct  mmc_command     *cmd;
 144         struct  mmc_data        *data;
 145         struct  clk             *fclk;
 146         struct  clk             *dbclk;
 147         /*
 148          * vcc == configured supply
 149          * vcc_aux == optional
 150          *   -  MMC1, supply for DAT4..DAT7
 151          *   -  MMC2/MMC2, external level shifter voltage supply, for
 152          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 153          */
 154         struct  regulator       *vcc;
 155         struct  regulator       *vcc_aux;
 156         void    __iomem         *base;
 157         resource_size_t         mapbase;
 158         spinlock_t              irq_lock; /* Prevent races with irq handler */
 159         unsigned int            dma_len;
 160         unsigned int            dma_sg_idx;
 161         unsigned char           bus_mode;
 162         unsigned char           power_mode;
 163         u32                     *buffer;
 164         u32                     bytesleft;
 165         int                     suspended;
 166         int                     irq;
 167         int                     use_dma, dma_ch;
 168         int                     dma_line_tx, dma_line_rx;
 169         int                     slot_id;
 170         int                     got_dbclk;
 171         int                     response_busy;
 172         int                     context_loss;
 173         int                     vdd;
 174         int                     protect_card;
 175         int                     reqs_blocked;
 176         int                     use_reg;
 177         int                     req_in_progress;
 178         struct omap_hsmmc_next  next_data;
 179
 180         struct  omap_mmc_platform_data  *pdata;
 181 };
 182
 183 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 184 {
 185         struct omap_mmc_platform_data *mmc = dev->platform_data;
 186
 187         /* NOTE: assumes card detect signal is active-low */
 188         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 189 }
 190
 191 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 192 {
 193         struct omap_mmc_platform_data *mmc = dev->platform_data;
 194
 195         /* NOTE: assumes write protect signal is active-high */
 196         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 197 }
 198
 199 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 200 {
 201         struct omap_mmc_platform_data *mmc = dev->platform_data;
 202
 203         /* NOTE: assumes card detect signal is active-low */
 204         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 205 }
 206
 207 #ifdef CONFIG_PM
 208
 209 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 210 {
 211         struct omap_mmc_platform_data *mmc = dev->platform_data;
 212
 213         disable_irq(mmc->slots[0].card_detect_irq);
 214         return 0;
 215 }
 216
 217 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 218 {
 219         struct omap_mmc_platform_data *mmc = dev->platform_data;
 220
 221         enable_irq(mmc->slots[0].card_detect_irq);
 222         return 0;
 223 }
 224
 225 #else
 226
 227 #define omap_hsmmc_suspend_cdirq        NULL
 228 #define omap_hsmmc_resume_cdirq         NULL
 229
 230 #endif
 231
 232 #ifdef CONFIG_REGULATOR
 233
 234 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
 235                                    int vdd)
 236 {
 237         struct omap_hsmmc_host *host =
 238                 platform_get_drvdata(to_platform_device(dev));
 239         int ret = 0;
 240
 241         /*
 242          * If we don't see a Vcc regulator, assume it's a fixed
 243          * voltage always-on regulator.
 244          */
 245         if (!host->vcc)
 246                 return 0;
 247         /*
 248          * With DT, never turn OFF the regulator. This is because
 249          * the pbias cell programming support is still missing when
 250          * booting with Device tree
 251          */
 252         if (of_have_populated_dt() && !vdd)
 253                 return 0;
 254
 255         if (mmc_slot(host).before_set_reg)
 256                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 257
 258         /*
 259          * Assume Vcc regulator is used only to power the card ... OMAP
 260          * VDDS is used to power the pins, optionally with a transceiver to
 261          * support cards using voltages other than VDDS (1.8V nominal).  When a
 262          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 263          *
 264          * In some cases this regulator won't support enable/disable;
 265          * e.g. it's a fixed rail for a WLAN chip.
 266          *
 267          * In other cases vcc_aux switches interface power.  Example, for
 268          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 269          * chips/cards need an interface voltage rail too.
 270          */
 271         if (power_on) {
 272                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 273                 /* Enable interface voltage rail, if needed */
 274                 if (ret == 0 && host->vcc_aux) {
 275                         ret = regulator_enable(host->vcc_aux);
 276                         if (ret < 0)
 277                                 ret = mmc_regulator_set_ocr(host->mmc,
 278                                                         host->vcc, 0);
 279                 }
 280         } else {
 281                 /* Shut down the rail */
 282                 if (host->vcc_aux)
 283                         ret = regulator_disable(host->vcc_aux);
 284                 if (!ret) {
 285                         /* Then proceed to shut down the local regulator */
 286                         ret = mmc_regulator_set_ocr(host->mmc,
 287                                                 host->vcc, 0);
 288                 }
 289         }
 290
 291         if (mmc_slot(host).after_set_reg)
 292                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 293
 294         return ret;
 295 }
 296
 297 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 298 {
 299         struct regulator *reg;
 300         int ocr_value = 0;
 301
 302         mmc_slot(host).set_power = omap_hsmmc_set_power;
 303
 304         reg = regulator_get(host->dev, "vmmc");
 305         if (IS_ERR(reg)) {
 306                 dev_dbg(host->dev, "vmmc regulator missing\n");
 307         } else {
 308                 host->vcc = reg;
 309                 ocr_value = mmc_regulator_get_ocrmask(reg);
 310                 if (!mmc_slot(host).ocr_mask) {
 311                         mmc_slot(host).ocr_mask = ocr_value;
 312                 } else {
 313                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
 314                                 dev_err(host->dev, "ocrmask %x is not supported\n",
 315                                         mmc_slot(host).ocr_mask);
 316                                 mmc_slot(host).ocr_mask = 0;
 317                                 return -EINVAL;
 318                         }
 319                 }
 320
 321                 /* Allow an aux regulator */
 322                 reg = regulator_get(host->dev, "vmmc_aux");
 323                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 324
 325                 /* For eMMC do not power off when not in sleep state */
 326                 if (mmc_slot(host).no_regulator_off_init)
 327                         return 0;
 328                 /*
 329                 * UGLY HACK:  workaround regulator framework bugs.
 330                 * When the bootloader leaves a supply active, it's
 331                 * initialized with zero usecount ... and we can't
 332                 * disable it without first enabling it.  Until the
 333                 * framework is fixed, we need a workaround like this
 334                 * (which is safe for MMC, but not in general).
 335                 */
 336                 if (regulator_is_enabled(host->vcc) > 0 ||
 337                     (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 338                         int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
 339
 340                         mmc_slot(host).set_power(host->dev, host->slot_id,
 341                                                  1, vdd);
 342                         mmc_slot(host).set_power(host->dev, host->slot_id,
 343                                                  0, 0);
 344                 }
 345         }
 346
 347         return 0;
 348 }
 349
 350 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 351 {
 352         regulator_put(host->vcc);
 353         regulator_put(host->vcc_aux);
 354         mmc_slot(host).set_power = NULL;
 355 }
 356
 357 static inline int omap_hsmmc_have_reg(void)
 358 {
 359         return 1;
 360 }
 361
 362 #else
 363
 364 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 365 {
 366         return -EINVAL;
 367 }
 368
 369 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 370 {
 371 }
 372
 373 static inline int omap_hsmmc_have_reg(void)
 374 {
 375         return 0;
 376 }
 377
 378 #endif
 379
 380 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 381 {
 382         int ret;
 383
 384         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
 385                 if (pdata->slots[0].cover)
 386                         pdata->slots[0].get_cover_state =
 387                                         omap_hsmmc_get_cover_state;
 388                 else
 389                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 390                 pdata->slots[0].card_detect_irq =
 391                                 gpio_to_irq(pdata->slots[0].switch_pin);
 392                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
 393                 if (ret)
 394                         return ret;
 395                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
 396                 if (ret)
 397                         goto err_free_sp;
 398         } else
 399                 pdata->slots[0].switch_pin = -EINVAL;
 400
 401         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 402                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
 403                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
 404                 if (ret)
 405                         goto err_free_cd;
 406                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
 407                 if (ret)
 408                         goto err_free_wp;
 409         } else
 410                 pdata->slots[0].gpio_wp = -EINVAL;
 411
 412         return 0;
 413
 414 err_free_wp:
 415         gpio_free(pdata->slots[0].gpio_wp);
 416 err_free_cd:
 417         if (gpio_is_valid(pdata->slots[0].switch_pin))
 418 err_free_sp:
 419                 gpio_free(pdata->slots[0].switch_pin);
 420         return ret;
 421 }
 422
 423 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
 424 {
 425         if (gpio_is_valid(pdata->slots[0].gpio_wp))
 426                 gpio_free(pdata->slots[0].gpio_wp);
 427         if (gpio_is_valid(pdata->slots[0].switch_pin))
 428                 gpio_free(pdata->slots[0].switch_pin);
 429 }
 430
 431 /*
 432  * Start clock to the card
 433  */
 434 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 435 {
 436         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 437                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 438 }
 439
 440 /*
 441  * Stop clock to the card
 442  */
 443 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 444 {
 445         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 446                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 447         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 448                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 449 }
 450
 451 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 452                                   struct mmc_command *cmd)
 453 {
 454         unsigned int irq_mask;
 455
 456         if (host->use_dma)
 457                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
 458         else
 459                 irq_mask = INT_EN_MASK;
 460
 461         /* Disable timeout for erases */
 462         if (cmd->opcode == MMC_ERASE)
 463                 irq_mask &= ~DTO_ENABLE;
 464
 465         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 466         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 467         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 468 }
 469
 470 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 471 {
 472         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 473         OMAP_HSMMC_WRITE(host->base, IE, 0);
 474         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 475 }
 476
 477 /* Calculate divisor for the given clock frequency */
 478 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
 479 {
 480         u16 dsor = 0;
 481
 482         if (ios->clock) {
 483                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
 484                 if (dsor > 250)
 485                         dsor = 250;
 486         }
 487
 488         return dsor;
 489 }
 490
 491 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 492 {
 493         struct mmc_ios *ios = &host->mmc->ios;
 494         unsigned long regval;
 495         unsigned long timeout;
 496
 497         dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 498
 499         omap_hsmmc_stop_clock(host);
 500
 501         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 502         regval = regval & ~(CLKD_MASK | DTO_MASK);
 503         regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
 504         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 505         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 506                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 507
 508         /* Wait till the ICS bit is set */
 509         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 510         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 511                 && time_before(jiffies, timeout))
 512                 cpu_relax();
 513
 514         omap_hsmmc_start_clock(host);
 515 }
 516
 517 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 518 {
 519         struct mmc_ios *ios = &host->mmc->ios;
 520         u32 con;
 521
 522         con = OMAP_HSMMC_READ(host->base, CON);
 523         switch (ios->bus_width) {
 524         case MMC_BUS_WIDTH_8:
 525                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 526                 break;
 527         case MMC_BUS_WIDTH_4:
 528                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 529                 OMAP_HSMMC_WRITE(host->base, HCTL,
 530                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 531                 break;
 532         case MMC_BUS_WIDTH_1:
 533                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 534                 OMAP_HSMMC_WRITE(host->base, HCTL,
 535                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 536                 break;
 537         }
 538 }
 539
 540 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 541 {
 542         struct mmc_ios *ios = &host->mmc->ios;
 543         u32 con;
 544
 545         con = OMAP_HSMMC_READ(host->base, CON);
 546         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 547                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 548         else
 549                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 550 }
 551
 552 #ifdef CONFIG_PM
 553
 554 /*
 555  * Restore the MMC host context, if it was lost as result of a
 556  * power state change.
 557  */
 558 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 559 {
 560         struct mmc_ios *ios = &host->mmc->ios;
 561         struct omap_mmc_platform_data *pdata = host->pdata;
 562         int context_loss = 0;
 563         u32 hctl, capa;
 564         unsigned long timeout;
 565
 566         if (pdata->get_context_loss_count) {
 567                 context_loss = pdata->get_context_loss_count(host->dev);
 568                 if (context_loss < 0)
 569                         return 1;
 570         }
 571
 572         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 573                 context_loss == host->context_loss ? "not " : "");
 574         if (host->context_loss == context_loss)
 575                 return 1;
 576
 577         /* Wait for hardware reset */
 578         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 579         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 580                 && time_before(jiffies, timeout))
 581                 ;
 582
 583         /* Do software reset */
 584         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 585         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 586         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 587                 && time_before(jiffies, timeout))
 588                 ;
 589
 590         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 591                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 592
 593         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 594                 if (host->power_mode != MMC_POWER_OFF &&
 595                     (1 << ios->vdd) <= MMC_VDD_23_24)
 596                         hctl = SDVS18;
 597                 else
 598                         hctl = SDVS30;
 599                 capa = VS30 | VS18;
 600         } else {
 601                 hctl = SDVS18;
 602                 capa = VS18;
 603         }
 604
 605         OMAP_HSMMC_WRITE(host->base, HCTL,
 606                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 607
 608         OMAP_HSMMC_WRITE(host->base, CAPA,
 609                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 610
 611         OMAP_HSMMC_WRITE(host->base, HCTL,
 612                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 613
 614         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 615         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 616                 && time_before(jiffies, timeout))
 617                 ;
 618
 619         omap_hsmmc_disable_irq(host);
 620
 621         /* Do not initialize card-specific things if the power is off */
 622         if (host->power_mode == MMC_POWER_OFF)
 623                 goto out;
 624
 625         omap_hsmmc_set_bus_width(host);
 626
 627         omap_hsmmc_set_clock(host);
 628
 629         omap_hsmmc_set_bus_mode(host);
 630
 631 out:
 632         host->context_loss = context_loss;
 633
 634         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 635         return 0;
 636 }
 637
 638 /*
 639  * Save the MMC host context (store the number of power state changes so far).
 640  */
 641 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 642 {
 643         struct omap_mmc_platform_data *pdata = host->pdata;
 644         int context_loss;
 645
 646         if (pdata->get_context_loss_count) {
 647                 context_loss = pdata->get_context_loss_count(host->dev);
 648                 if (context_loss < 0)
 649                         return;
 650                 host->context_loss = context_loss;
 651         }
 652 }
 653
 654 #else
 655
 656 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 657 {
 658         return 0;
 659 }
 660
 661 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 662 {
 663 }
 664
 665 #endif
 666
 667 /*
 668  * Send init stream sequence to card
 669  * before sending IDLE command
 670  */
 671 static void send_init_stream(struct omap_hsmmc_host *host)
 672 {
 673         int reg = 0;
 674         unsigned long timeout;
 675
 676         if (host->protect_card)
 677                 return;
 678
 679         disable_irq(host->irq);
 680
 681         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 682         OMAP_HSMMC_WRITE(host->base, CON,
 683                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 684         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 685
 686         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 687         while ((reg != CC) && time_before(jiffies, timeout))
 688                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 689
 690         OMAP_HSMMC_WRITE(host->base, CON,
 691                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 692
 693         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 694         OMAP_HSMMC_READ(host->base, STAT);
 695
 696         enable_irq(host->irq);
 697 }
 698
 699 static inline
 700 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 701 {
 702         int r = 1;
 703
 704         if (mmc_slot(host).get_cover_state)
 705                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 706         return r;
 707 }
 708
 709 static ssize_t
 710 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 711                            char *buf)
 712 {
 713         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 714         struct omap_hsmmc_host *host = mmc_priv(mmc);
 715
 716         return sprintf(buf, "%s\n",
 717                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 718 }
 719
 720 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 721
 722 static ssize_t
 723 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 724                         char *buf)
 725 {
 726         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 727         struct omap_hsmmc_host *host = mmc_priv(mmc);
 728
 729         return sprintf(buf, "%s\n", mmc_slot(host).name);
 730 }
 731
 732 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 733
 734 /*
 735  * Configure the response type and send the cmd.
 736  */
 737 static void
 738 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 739         struct mmc_data *data)
 740 {
 741         int cmdreg = 0, resptype = 0, cmdtype = 0;
 742
 743         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 744                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 745         host->cmd = cmd;
 746
 747         omap_hsmmc_enable_irq(host, cmd);
 748
 749         host->response_busy = 0;
 750         if (cmd->flags & MMC_RSP_PRESENT) {
 751                 if (cmd->flags & MMC_RSP_136)
 752                         resptype = 1;
 753                 else if (cmd->flags & MMC_RSP_BUSY) {
 754                         resptype = 3;
 755                         host->response_busy = 1;
 756                 } else
 757                         resptype = 2;
 758         }
 759
 760         /*
 761          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 762          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 763          * a val of 0x3, rest 0x0.
 764          */
 765         if (cmd == host->mrq->stop)
 766                 cmdtype = 0x3;
 767
 768         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 769
 770         if (data) {
 771                 cmdreg |= DP_SELECT | MSBS | BCE;
 772                 if (data->flags & MMC_DATA_READ)
 773                         cmdreg |= DDIR;
 774                 else
 775                         cmdreg &= ~(DDIR);
 776         }
 777
 778         if (host->use_dma)
 779                 cmdreg |= DMA_EN;
 780
 781         host->req_in_progress = 1;
 782
 783         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 784         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 785 }
 786
 787 static int
 788 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 789 {
 790         if (data->flags & MMC_DATA_WRITE)
 791                 return DMA_TO_DEVICE;
 792         else
 793                 return DMA_FROM_DEVICE;
 794 }
 795
 796 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 797 {
 798         int dma_ch;
 799
 800         spin_lock(&host->irq_lock);
 801         host->req_in_progress = 0;
 802         dma_ch = host->dma_ch;
 803         spin_unlock(&host->irq_lock);
 804
 805         omap_hsmmc_disable_irq(host);
 806         /* Do not complete the request if DMA is still in progress */
 807         if (mrq->data && host->use_dma && dma_ch != -1)
 808                 return;
 809         host->mrq = NULL;
 810         mmc_request_done(host->mmc, mrq);
 811 }
 812
 813 /*
 814  * Notify the transfer complete to MMC core
 815  */
 816 static void
 817 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 818 {
 819         if (!data) {
 820                 struct mmc_request *mrq = host->mrq;
 821
 822                 /* TC before CC from CMD6 - don't know why, but it happens */
 823                 if (host->cmd && host->cmd->opcode == 6 &&
 824                     host->response_busy) {
 825                         host->response_busy = 0;
 826                         return;
 827                 }
 828
 829                 omap_hsmmc_request_done(host, mrq);
 830                 return;
 831         }
 832
 833         host->data = NULL;
 834
 835         if (!data->error)
 836                 data->bytes_xfered += data->blocks * (data->blksz);
 837         else
 838                 data->bytes_xfered = 0;
 839
 840         if (!data->stop) {
 841                 omap_hsmmc_request_done(host, data->mrq);
 842                 return;
 843         }
 844         omap_hsmmc_start_command(host, data->stop, NULL);
 845 }
 846
 847 /*
 848  * Notify the core about command completion
 849  */
 850 static void
 851 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 852 {
 853         host->cmd = NULL;
 854
 855         if (cmd->flags & MMC_RSP_PRESENT) {
 856                 if (cmd->flags & MMC_RSP_136) {
 857                         /* response type 2 */
 858                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 859                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 860                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 861                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 862                 } else {
 863                         /* response types 1, 1b, 3, 4, 5, 6 */
 864                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 865                 }
 866         }
 867         if ((host->data == NULL && !host->response_busy) || cmd->error)
 868                 omap_hsmmc_request_done(host, cmd->mrq);
 869 }
 870
 871 /*
 872  * DMA clean up for command errors
 873  */
 874 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 875 {
 876         int dma_ch;
 877
 878         host->data->error = errno;
 879
 880         spin_lock(&host->irq_lock);
 881         dma_ch = host->dma_ch;
 882         host->dma_ch = -1;
 883         spin_unlock(&host->irq_lock);
 884
 885         if (host->use_dma && dma_ch != -1) {
 886                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
 887                         host->data->sg_len,
 888                         omap_hsmmc_get_dma_dir(host, host->data));
 889                 omap_free_dma(dma_ch);
 890                 host->data->host_cookie = 0;
 891         }
 892         host->data = NULL;
 893 }
 894
 895 /*
 896  * Readable error output
 897  */
 898 #ifdef CONFIG_MMC_DEBUG
 899 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
 900 {
 901         /* --- means reserved bit without definition at documentation */
 902         static const char *omap_hsmmc_status_bits[] = {
 903                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
 904                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
 905                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
 906                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
 907         };
 908         char res[256];
 909         char *buf = res;
 910         int len, i;
 911
 912         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 913         buf += len;
 914
 915         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
 916                 if (status & (1 << i)) {
 917                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
 918                         buf += len;
 919                 }
 920
 921         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 922 }
 923 #else
 924 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
 925                                              u32 status)
 926 {
 927 }
 928 #endif  /* CONFIG_MMC_DEBUG */
 929
 930 /*
 931  * MMC controller internal state machines reset
 932  *
 933  * Used to reset command or data internal state machines, using respectively
 934  *  SRC or SRD bit of SYSCTL register
 935  * Can be called from interrupt context
 936  */
 937 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
 938                                                    unsigned long bit)
 939 {
 940         unsigned long i = 0;
 941         unsigned long limit = (loops_per_jiffy *
 942                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 943
 944         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 945                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 946
 947         /*
 948          * OMAP4 ES2 and greater has an updated reset logic.
 949          * Monitor a 0->1 transition first
 950          */
 951         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
 952                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
 953                                         && (i++ < limit))
 954                         cpu_relax();
 955         }
 956         i = 0;
 957
 958         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 959                 (i++ < limit))
 960                 cpu_relax();
 961
 962         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 963                 dev_err(mmc_dev(host->mmc),
 964                         "Timeout waiting on controller reset in %s\n",
 965                         __func__);
 966 }
 967
 968 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
 969 {
 970         struct mmc_data *data;
 971         int end_cmd = 0, end_trans = 0;
 972
 973         if (!host->req_in_progress) {
 974                 do {
 975                         OMAP_HSMMC_WRITE(host->base, STAT, status);
 976                         /* Flush posted write */
 977                         status = OMAP_HSMMC_READ(host->base, STAT);
 978                 } while (status & INT_EN_MASK);
 979                 return;
 980         }
 981
 982         data = host->data;
 983         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 984
 985         if (status & ERR) {
 986                 omap_hsmmc_dbg_report_irq(host, status);
 987                 if ((status & CMD_TIMEOUT) ||
 988                         (status & CMD_CRC)) {
 989                         if (host->cmd) {
 990                                 if (status & CMD_TIMEOUT) {
 991                                         omap_hsmmc_reset_controller_fsm(host,
 992                                                                         SRC);
 993                                         host->cmd->error = -ETIMEDOUT;
 994                                 } else {
 995                                         host->cmd->error = -EILSEQ;
 996                                 }
 997                                 end_cmd = 1;
 998                         }
 999                         if (host->data || host->response_busy) {
1000                                 if (host->data)
1001                                         omap_hsmmc_dma_cleanup(host,
1002                                                                 -ETIMEDOUT);
1003                                 host->response_busy = 0;
1004                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1005                         }
1006                 }
1007                 if ((status & DATA_TIMEOUT) ||
1008                         (status & DATA_CRC)) {
1009                         if (host->data || host->response_busy) {
1010                                 int err = (status & DATA_TIMEOUT) ?
1011                                                 -ETIMEDOUT : -EILSEQ;
1012
1013                                 if (host->data)
1014                                         omap_hsmmc_dma_cleanup(host, err);
1015                                 else
1016                                         host->mrq->cmd->error = err;
1017                                 host->response_busy = 0;
1018                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1019                                 end_trans = 1;
1020                         }
1021                 }
1022                 if (status & CARD_ERR) {
1023                         dev_dbg(mmc_dev(host->mmc),
1024                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1025                         if (host->cmd)
1026                                 end_cmd = 1;
1027                         if (host->data)
1028                                 end_trans = 1;
1029                 }
1030         }
1031
1032         OMAP_HSMMC_WRITE(host->base, STAT, status);
1033
1034         if (end_cmd || ((status & CC) && host->cmd))
1035                 omap_hsmmc_cmd_done(host, host->cmd);
1036         if ((end_trans || (status & TC)) && host->mrq)
1037                 omap_hsmmc_xfer_done(host, data);
1038 }
1039
1040 /*
1041  * MMC controller IRQ handler
1042  */
1043 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1044 {
1045         struct omap_hsmmc_host *host = dev_id;
1046         int status;
1047
1048         status = OMAP_HSMMC_READ(host->base, STAT);
1049         do {
1050                 omap_hsmmc_do_irq(host, status);
1051                 /* Flush posted write */
1052                 status = OMAP_HSMMC_READ(host->base, STAT);
1053         } while (status & INT_EN_MASK);
1054
1055         return IRQ_HANDLED;
1056 }
1057
1058 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1059 {
1060         unsigned long i;
1061
1062         OMAP_HSMMC_WRITE(host->base, HCTL,
1063                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1064         for (i = 0; i < loops_per_jiffy; i++) {
1065                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1066                         break;
1067                 cpu_relax();
1068         }
1069 }
1070
1071 /*
1072  * Switch MMC interface voltage ... only relevant for MMC1.
1073  *
1074  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1075  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1076  * Some chips, like eMMC ones, use internal transceivers.
1077  */
1078 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1079 {
1080         u32 reg_val = 0;
1081         int ret;
1082
1083         /* Disable the clocks */
1084         pm_runtime_put_sync(host->dev);
1085         if (host->got_dbclk)
1086                 clk_disable(host->dbclk);
1087
1088         /* Turn the power off */
1089         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1090
1091         /* Turn the power ON with given VDD 1.8 or 3.0v */
1092         if (!ret)
1093                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1094                                                vdd);
1095         pm_runtime_get_sync(host->dev);
1096         if (host->got_dbclk)
1097                 clk_enable(host->dbclk);
1098
1099         if (ret != 0)
1100                 goto err;
1101
1102         OMAP_HSMMC_WRITE(host->base, HCTL,
1103                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1104         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1105
1106         /*
1107          * If a MMC dual voltage card is detected, the set_ios fn calls
1108          * this fn with VDD bit set for 1.8V. Upon card removal from the
1109          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1110          *
1111          * Cope with a bit of slop in the range ... per data sheets:
1112          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1113          *    but recommended values are 1.71V to 1.89V
1114          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1115          *    but recommended values are 2.7V to 3.3V
1116          *
1117          * Board setup code shouldn't permit anything very out-of-range.
1118          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1119          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1120          */
1121         if ((1 << vdd) <= MMC_VDD_23_24)
1122                 reg_val |= SDVS18;
1123         else
1124                 reg_val |= SDVS30;
1125
1126         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1127         set_sd_bus_power(host);
1128
1129         return 0;
1130 err:
1131         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1132         return ret;
1133 }
1134
1135 /* Protect the card while the cover is open */
1136 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1137 {
1138         if (!mmc_slot(host).get_cover_state)
1139                 return;
1140
1141         host->reqs_blocked = 0;
1142         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1143                 if (host->protect_card) {
1144                         dev_info(host->dev, "%s: cover is closed, "
1145                                          "card is now accessible\n",
1146                                          mmc_hostname(host->mmc));
1147                         host->protect_card = 0;
1148                 }
1149         } else {
1150                 if (!host->protect_card) {
1151                         dev_info(host->dev, "%s: cover is open, "
1152                                          "card is now inaccessible\n",
1153                                          mmc_hostname(host->mmc));
1154                         host->protect_card = 1;
1155                 }
1156         }
1157 }
1158
1159 /*
1160  * irq handler to notify the core about card insertion/removal
1161  */
1162 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1163 {
1164         struct omap_hsmmc_host *host = dev_id;
1165         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1166         int carddetect;
1167
1168         if (host->suspended)
1169                 return IRQ_HANDLED;
1170
1171         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1172
1173         if (slot->card_detect)
1174                 carddetect = slot->card_detect(host->dev, host->slot_id);
1175         else {
1176                 omap_hsmmc_protect_card(host);
1177                 carddetect = -ENOSYS;
1178         }
1179
1180         if (carddetect)
1181                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1182         else
1183                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1184         return IRQ_HANDLED;
1185 }
1186
1187 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1188                                      struct mmc_data *data)
1189 {
1190         int sync_dev;
1191
1192         if (data->flags & MMC_DATA_WRITE)
1193                 sync_dev = host->dma_line_tx;
1194         else
1195                 sync_dev = host->dma_line_rx;
1196         return sync_dev;
1197 }
1198
1199 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1200                                        struct mmc_data *data,
1201                                        struct scatterlist *sgl)
1202 {
1203         int blksz, nblk, dma_ch;
1204
1205         dma_ch = host->dma_ch;
1206         if (data->flags & MMC_DATA_WRITE) {
1207                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1208                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1209                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1210                         sg_dma_address(sgl), 0, 0);
1211         } else {
1212                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1213                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1214                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1215                         sg_dma_address(sgl), 0, 0);
1216         }
1217
1218         blksz = host->data->blksz;
1219         nblk = sg_dma_len(sgl) / blksz;
1220
1221         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1222                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1223                         omap_hsmmc_get_dma_sync_dev(host, data),
1224                         !(data->flags & MMC_DATA_WRITE));
1225
1226         omap_start_dma(dma_ch);
1227 }
1228
1229 /*
1230  * DMA call back function
1231  */
1232 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1233 {
1234         struct omap_hsmmc_host *host = cb_data;
1235         struct mmc_data *data;
1236         int dma_ch, req_in_progress;
1237
1238         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1239                 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1240                         ch_status);
1241                 return;
1242         }
1243
1244         spin_lock(&host->irq_lock);
1245         if (host->dma_ch < 0) {
1246                 spin_unlock(&host->irq_lock);
1247                 return;
1248         }
1249
1250         data = host->mrq->data;
1251         host->dma_sg_idx++;
1252         if (host->dma_sg_idx < host->dma_len) {
1253                 /* Fire up the next transfer. */
1254                 omap_hsmmc_config_dma_params(host, data,
1255                                            data->sg + host->dma_sg_idx);
1256                 spin_unlock(&host->irq_lock);
1257                 return;
1258         }
1259
1260         if (!data->host_cookie)
1261                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1262                              omap_hsmmc_get_dma_dir(host, data));
1263
1264         req_in_progress = host->req_in_progress;
1265         dma_ch = host->dma_ch;
1266         host->dma_ch = -1;
1267         spin_unlock(&host->irq_lock);
1268
1269         omap_free_dma(dma_ch);
1270
1271         /* If DMA has finished after TC, complete the request */
1272         if (!req_in_progress) {
1273                 struct mmc_request *mrq = host->mrq;
1274
1275                 host->mrq = NULL;
1276                 mmc_request_done(host->mmc, mrq);
1277         }
1278 }
1279
1280 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1281                                        struct mmc_data *data,
1282                                        struct omap_hsmmc_next *next)
1283 {
1284         int dma_len;
1285
1286         if (!next && data->host_cookie &&
1287             data->host_cookie != host->next_data.cookie) {
1288                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1289                        " host->next_data.cookie %d\n",
1290                        __func__, data->host_cookie, host->next_data.cookie);
1291                 data->host_cookie = 0;
1292         }
1293
1294         /* Check if next job is already prepared */
1295         if (next ||
1296             (!next && data->host_cookie != host->next_data.cookie)) {
1297                 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1298                                      data->sg_len,
1299                                      omap_hsmmc_get_dma_dir(host, data));
1300
1301         } else {
1302                 dma_len = host->next_data.dma_len;
1303                 host->next_data.dma_len = 0;
1304         }
1305
1306
1307         if (dma_len == 0)
1308                 return -EINVAL;
1309
1310         if (next) {
1311                 next->dma_len = dma_len;
1312                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1313         } else
1314                 host->dma_len = dma_len;
1315
1316         return 0;
1317 }
1318
1319 /*
1320  * Routine to configure and start DMA for the MMC card
1321  */
1322 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1323                                         struct mmc_request *req)
1324 {
1325         int dma_ch = 0, ret = 0, i;
1326         struct mmc_data *data = req->data;
1327
1328         /* Sanity check: all the SG entries must be aligned by block size. */
1329         for (i = 0; i < data->sg_len; i++) {
1330                 struct scatterlist *sgl;
1331
1332                 sgl = data->sg + i;
1333                 if (sgl->length % data->blksz)
1334                         return -EINVAL;
1335         }
1336         if ((data->blksz % 4) != 0)
1337                 /* REVISIT: The MMC buffer increments only when MSB is written.
1338                  * Return error for blksz which is non multiple of four.
1339                  */
1340                 return -EINVAL;
1341
1342         BUG_ON(host->dma_ch != -1);
1343
1344         ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1345                                "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1346         if (ret != 0) {
1347                 dev_err(mmc_dev(host->mmc),
1348                         "%s: omap_request_dma() failed with %d\n",
1349                         mmc_hostname(host->mmc), ret);
1350                 return ret;
1351         }
1352         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1353         if (ret)
1354                 return ret;
1355
1356         host->dma_ch = dma_ch;
1357         host->dma_sg_idx = 0;
1358
1359         omap_hsmmc_config_dma_params(host, data, data->sg);
1360
1361         return 0;
1362 }
1363
1364 static void set_data_timeout(struct omap_hsmmc_host *host,
1365                              unsigned int timeout_ns,
1366                              unsigned int timeout_clks)
1367 {
1368         unsigned int timeout, cycle_ns;
1369         uint32_t reg, clkd, dto = 0;
1370
1371         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1372         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1373         if (clkd == 0)
1374                 clkd = 1;
1375
1376         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1377         timeout = timeout_ns / cycle_ns;
1378         timeout += timeout_clks;
1379         if (timeout) {
1380                 while ((timeout & 0x80000000) == 0) {
1381                         dto += 1;
1382                         timeout <<= 1;
1383                 }
1384                 dto = 31 - dto;
1385                 timeout <<= 1;
1386                 if (timeout && dto)
1387                         dto += 1;
1388                 if (dto >= 13)
1389                         dto -= 13;
1390                 else
1391                         dto = 0;
1392                 if (dto > 14)
1393                         dto = 14;
1394         }
1395
1396         reg &= ~DTO_MASK;
1397         reg |= dto << DTO_SHIFT;
1398         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1399 }
1400
1401 /*
1402  * Configure block length for MMC/SD cards and initiate the transfer.
1403  */
1404 static int
1405 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1406 {
1407         int ret;
1408         host->data = req->data;
1409
1410         if (req->data == NULL) {
1411                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1412                 /*
1413                  * Set an arbitrary 100ms data timeout for commands with
1414                  * busy signal.
1415                  */
1416                 if (req->cmd->flags & MMC_RSP_BUSY)
1417                         set_data_timeout(host, 100000000U, 0);
1418                 return 0;
1419         }
1420
1421         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1422                                         | (req->data->blocks << 16));
1423         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1424
1425         if (host->use_dma) {
1426                 ret = omap_hsmmc_start_dma_transfer(host, req);
1427                 if (ret != 0) {
1428                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1429                         return ret;
1430                 }
1431         }
1432         return 0;
1433 }
1434
1435 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1436                                 int err)
1437 {
1438         struct omap_hsmmc_host *host = mmc_priv(mmc);
1439         struct mmc_data *data = mrq->data;
1440
1441         if (host->use_dma) {
1442                 if (data->host_cookie)
1443                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1444                                      data->sg_len,
1445                                      omap_hsmmc_get_dma_dir(host, data));
1446                 data->host_cookie = 0;
1447         }
1448 }
1449
1450 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1451                                bool is_first_req)
1452 {
1453         struct omap_hsmmc_host *host = mmc_priv(mmc);
1454
1455         if (mrq->data->host_cookie) {
1456                 mrq->data->host_cookie = 0;
1457                 return ;
1458         }
1459
1460         if (host->use_dma)
1461                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1462                                                 &host->next_data))
1463                         mrq->data->host_cookie = 0;
1464 }
1465
1466 /*
1467  * Request function. for read/write operation
1468  */
1469 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1470 {
1471         struct omap_hsmmc_host *host = mmc_priv(mmc);
1472         int err;
1473
1474         BUG_ON(host->req_in_progress);
1475         BUG_ON(host->dma_ch != -1);
1476         if (host->protect_card) {
1477                 if (host->reqs_blocked < 3) {
1478                         /*
1479                          * Ensure the controller is left in a consistent
1480                          * state by resetting the command and data state
1481                          * machines.
1482                          */
1483                         omap_hsmmc_reset_controller_fsm(host, SRD);
1484                         omap_hsmmc_reset_controller_fsm(host, SRC);
1485                         host->reqs_blocked += 1;
1486                 }
1487                 req->cmd->error = -EBADF;
1488                 if (req->data)
1489                         req->data->error = -EBADF;
1490                 req->cmd->retries = 0;
1491                 mmc_request_done(mmc, req);
1492                 return;
1493         } else if (host->reqs_blocked)
1494                 host->reqs_blocked = 0;
1495         WARN_ON(host->mrq != NULL);
1496         host->mrq = req;
1497         err = omap_hsmmc_prepare_data(host, req);
1498         if (err) {
1499                 req->cmd->error = err;
1500                 if (req->data)
1501                         req->data->error = err;
1502                 host->mrq = NULL;
1503                 mmc_request_done(mmc, req);
1504                 return;
1505         }
1506
1507         omap_hsmmc_start_command(host, req->cmd, req->data);
1508 }
1509
1510 /* Routine to configure clock values. Exposed API to core */
1511 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1512 {
1513         struct omap_hsmmc_host *host = mmc_priv(mmc);
1514         int do_send_init_stream = 0;
1515
1516         pm_runtime_get_sync(host->dev);
1517
1518         if (ios->power_mode != host->power_mode) {
1519                 switch (ios->power_mode) {
1520                 case MMC_POWER_OFF:
1521                         mmc_slot(host).set_power(host->dev, host->slot_id,
1522                                                  0, 0);
1523                         host->vdd = 0;
1524                         break;
1525                 case MMC_POWER_UP:
1526                         mmc_slot(host).set_power(host->dev, host->slot_id,
1527                                                  1, ios->vdd);
1528                         host->vdd = ios->vdd;
1529                         break;
1530                 case MMC_POWER_ON:
1531                         do_send_init_stream = 1;
1532                         break;
1533                 }
1534                 host->power_mode = ios->power_mode;
1535         }
1536
1537         /* FIXME: set registers based only on changes to ios */
1538
1539         omap_hsmmc_set_bus_width(host);
1540
1541         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1542                 /* Only MMC1 can interface at 3V without some flavor
1543                  * of external transceiver; but they all handle 1.8V.
1544                  */
1545                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1546                         (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1547                         /*
1548                          * With pbias cell programming missing, this
1549                          * can't be allowed when booting with device
1550                          * tree.
1551                          */
1552                         (!of_have_populated_dt())) {
1553                                 /*
1554                                  * The mmc_select_voltage fn of the core does
1555                                  * not seem to set the power_mode to
1556                                  * MMC_POWER_UP upon recalculating the voltage.
1557                                  * vdd 1.8v.
1558                                  */
1559                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1560                                 dev_dbg(mmc_dev(host->mmc),
1561                                                 "Switch operation failed\n");
1562                 }
1563         }
1564
1565         omap_hsmmc_set_clock(host);
1566
1567         if (do_send_init_stream)
1568                 send_init_stream(host);
1569
1570         omap_hsmmc_set_bus_mode(host);
1571
1572         pm_runtime_put_autosuspend(host->dev);
1573 }
1574
1575 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1576 {
1577         struct omap_hsmmc_host *host = mmc_priv(mmc);
1578
1579         if (!mmc_slot(host).card_detect)
1580                 return -ENOSYS;
1581         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1582 }
1583
1584 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1585 {
1586         struct omap_hsmmc_host *host = mmc_priv(mmc);
1587
1588         if (!mmc_slot(host).get_ro)
1589                 return -ENOSYS;
1590         return mmc_slot(host).get_ro(host->dev, 0);
1591 }
1592
1593 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1594 {
1595         struct omap_hsmmc_host *host = mmc_priv(mmc);
1596
1597         if (mmc_slot(host).init_card)
1598                 mmc_slot(host).init_card(card);
1599 }
1600
1601 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1602 {
1603         u32 hctl, capa, value;
1604
1605         /* Only MMC1 supports 3.0V */
1606         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1607                 hctl = SDVS30;
1608                 capa = VS30 | VS18;
1609         } else {
1610                 hctl = SDVS18;
1611                 capa = VS18;
1612         }
1613
1614         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1615         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1616
1617         value = OMAP_HSMMC_READ(host->base, CAPA);
1618         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1619
1620         /* Set the controller to AUTO IDLE mode */
1621         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1622         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1623
1624         /* Set SD bus power bit */
1625         set_sd_bus_power(host);
1626 }
1627
1628 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1629 {
1630         struct omap_hsmmc_host *host = mmc_priv(mmc);
1631
1632         pm_runtime_get_sync(host->dev);
1633
1634         return 0;
1635 }
1636
1637 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1638 {
1639         struct omap_hsmmc_host *host = mmc_priv(mmc);
1640
1641         pm_runtime_mark_last_busy(host->dev);
1642         pm_runtime_put_autosuspend(host->dev);
1643
1644         return 0;
1645 }
1646
1647 static const struct mmc_host_ops omap_hsmmc_ops = {
1648         .enable = omap_hsmmc_enable_fclk,
1649         .disable = omap_hsmmc_disable_fclk,
1650         .post_req = omap_hsmmc_post_req,
1651         .pre_req = omap_hsmmc_pre_req,
1652         .request = omap_hsmmc_request,
1653         .set_ios = omap_hsmmc_set_ios,
1654         .get_cd = omap_hsmmc_get_cd,
1655         .get_ro = omap_hsmmc_get_ro,
1656         .init_card = omap_hsmmc_init_card,
1657         /* NYET -- enable_sdio_irq */
1658 };
1659
1660 #ifdef CONFIG_DEBUG_FS
1661
1662 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1663 {
1664         struct mmc_host *mmc = s->private;
1665         struct omap_hsmmc_host *host = mmc_priv(mmc);
1666         int context_loss = 0;
1667
1668         if (host->pdata->get_context_loss_count)
1669                 context_loss = host->pdata->get_context_loss_count(host->dev);
1670
1671         seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1672                         mmc->index, host->context_loss, context_loss);
1673
1674         if (host->suspended) {
1675                 seq_printf(s, "host suspended, can't read registers\n");
1676                 return 0;
1677         }
1678
1679         pm_runtime_get_sync(host->dev);
1680
1681         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1682                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1683         seq_printf(s, "CON:\t\t0x%08x\n",
1684                         OMAP_HSMMC_READ(host->base, CON));
1685         seq_printf(s, "HCTL:\t\t0x%08x\n",
1686                         OMAP_HSMMC_READ(host->base, HCTL));
1687         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1688                         OMAP_HSMMC_READ(host->base, SYSCTL));
1689         seq_printf(s, "IE:\t\t0x%08x\n",
1690                         OMAP_HSMMC_READ(host->base, IE));
1691         seq_printf(s, "ISE:\t\t0x%08x\n",
1692                         OMAP_HSMMC_READ(host->base, ISE));
1693         seq_printf(s, "CAPA:\t\t0x%08x\n",
1694                         OMAP_HSMMC_READ(host->base, CAPA));
1695
1696         pm_runtime_mark_last_busy(host->dev);
1697         pm_runtime_put_autosuspend(host->dev);
1698
1699         return 0;
1700 }
1701
1702 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1703 {
1704         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1705 }
1706
1707 static const struct file_operations mmc_regs_fops = {
1708         .open           = omap_hsmmc_regs_open,
1709         .read           = seq_read,
1710         .llseek         = seq_lseek,
1711         .release        = single_release,
1712 };
1713
1714 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1715 {
1716         if (mmc->debugfs_root)
1717                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1718                         mmc, &mmc_regs_fops);
1719 }
1720
1721 #else
1722
1723 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1724 {
1725 }
1726
1727 #endif
1728
1729 #ifdef CONFIG_OF
1730 static u16 omap4_reg_offset = 0x100;
1731
1732 static const struct of_device_id omap_mmc_of_match[] = {
1733         {
1734                 .compatible = "ti,omap2-hsmmc",
1735         },
1736         {
1737                 .compatible = "ti,omap3-hsmmc",
1738         },
1739         {
1740                 .compatible = "ti,omap4-hsmmc",
1741                 .data = &omap4_reg_offset,
1742         },
1743         {},
1744 }
1745 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1746
1747 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1748 {
1749         struct omap_mmc_platform_data *pdata;
1750         struct device_node *np = dev->of_node;
1751         u32 bus_width;
1752
1753         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1754         if (!pdata)
1755                 return NULL; /* out of memory */
1756
1757         if (of_find_property(np, "ti,dual-volt", NULL))
1758                 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1759
1760         /* This driver only supports 1 slot */
1761         pdata->nr_slots = 1;
1762         pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1763         pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1764
1765         if (of_find_property(np, "ti,non-removable", NULL)) {
1766                 pdata->slots[0].nonremovable = true;
1767                 pdata->slots[0].no_regulator_off_init = true;
1768         }
1769         of_property_read_u32(np, "ti,bus-width", &bus_width);
1770         if (bus_width == 4)
1771                 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1772         else if (bus_width == 8)
1773                 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1774
1775         if (of_find_property(np, "ti,needs-special-reset", NULL))
1776                 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1777
1778         return pdata;
1779 }
1780 #else
1781 static inline struct omap_mmc_platform_data
1782                         *of_get_hsmmc_pdata(struct device *dev)
1783 {
1784         return NULL;
1785 }
1786 #endif
1787
1788 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1789 {
1790         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1791         struct mmc_host *mmc;
1792         struct omap_hsmmc_host *host = NULL;
1793         struct resource *res;
1794         int ret, irq;
1795         const struct of_device_id *match;
1796
1797         match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1798         if (match) {
1799                 pdata = of_get_hsmmc_pdata(&pdev->dev);
1800                 if (match->data) {
1801                         u16 *offsetp = match->data;
1802                         pdata->reg_offset = *offsetp;
1803                 }
1804         }
1805
1806         if (pdata == NULL) {
1807                 dev_err(&pdev->dev, "Platform Data is missing\n");
1808                 return -ENXIO;
1809         }
1810
1811         if (pdata->nr_slots == 0) {
1812                 dev_err(&pdev->dev, "No Slots\n");
1813                 return -ENXIO;
1814         }
1815
1816         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1817         irq = platform_get_irq(pdev, 0);
1818         if (res == NULL || irq < 0)
1819                 return -ENXIO;
1820
1821         res->start += pdata->reg_offset;
1822         res->end += pdata->reg_offset;
1823         res = request_mem_region(res->start, resource_size(res), pdev->name);
1824         if (res == NULL)
1825                 return -EBUSY;
1826
1827         ret = omap_hsmmc_gpio_init(pdata);
1828         if (ret)
1829                 goto err;
1830
1831         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1832         if (!mmc) {
1833                 ret = -ENOMEM;
1834                 goto err_alloc;
1835         }
1836
1837         host            = mmc_priv(mmc);
1838         host->mmc       = mmc;
1839         host->pdata     = pdata;
1840         host->dev       = &pdev->dev;
1841         host->use_dma   = 1;
1842         host->dev->dma_mask = &pdata->dma_mask;
1843         host->dma_ch    = -1;
1844         host->irq       = irq;
1845         host->slot_id   = 0;
1846         host->mapbase   = res->start;
1847         host->base      = ioremap(host->mapbase, SZ_4K);
1848         host->power_mode = MMC_POWER_OFF;
1849         host->next_data.cookie = 1;
1850
1851         platform_set_drvdata(pdev, host);
1852
1853         mmc->ops        = &omap_hsmmc_ops;
1854
1855         /*
1856          * If regulator_disable can only put vcc_aux to sleep then there is
1857          * no off state.
1858          */
1859         if (mmc_slot(host).vcc_aux_disable_is_sleep)
1860                 mmc_slot(host).no_off = 1;
1861
1862         mmc->f_min = OMAP_MMC_MIN_CLOCK;
1863
1864         if (pdata->max_freq > 0)
1865                 mmc->f_max = pdata->max_freq;
1866         else
1867                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1868
1869         spin_lock_init(&host->irq_lock);
1870
1871         host->fclk = clk_get(&pdev->dev, "fck");
1872         if (IS_ERR(host->fclk)) {
1873                 ret = PTR_ERR(host->fclk);
1874                 host->fclk = NULL;
1875                 goto err1;
1876         }
1877
1878         omap_hsmmc_context_save(host);
1879
1880         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1881                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1882                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1883         }
1884
1885         pm_runtime_enable(host->dev);
1886         pm_runtime_get_sync(host->dev);
1887         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1888         pm_runtime_use_autosuspend(host->dev);
1889
1890         if (cpu_is_omap2430()) {
1891                 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1892                 /*
1893                  * MMC can still work without debounce clock.
1894                  */
1895                 if (IS_ERR(host->dbclk))
1896                         dev_warn(mmc_dev(host->mmc),
1897                                 "Failed to get debounce clock\n");
1898                 else
1899                         host->got_dbclk = 1;
1900
1901                 if (host->got_dbclk)
1902                         if (clk_enable(host->dbclk) != 0)
1903                                 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1904                                                         " clk failed\n");
1905         }
1906
1907         /* Since we do only SG emulation, we can have as many segs
1908          * as we want. */
1909         mmc->max_segs = 1024;
1910
1911         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1912         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1913         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1914         mmc->max_seg_size = mmc->max_req_size;
1915
1916         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1917                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1918
1919         mmc->caps |= mmc_slot(host).caps;
1920         if (mmc->caps & MMC_CAP_8_BIT_DATA)
1921                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1922
1923         if (mmc_slot(host).nonremovable)
1924                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1925
1926         mmc->pm_caps = mmc_slot(host).pm_caps;
1927
1928         omap_hsmmc_conf_bus_power(host);
1929
1930         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1931         if (!res) {
1932                 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1933                 goto err_irq;
1934         }
1935         host->dma_line_tx = res->start;
1936
1937         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1938         if (!res) {
1939                 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1940                 goto err_irq;
1941         }
1942         host->dma_line_rx = res->start;
1943
1944         /* Request IRQ for MMC operations */
1945         ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1946                         mmc_hostname(mmc), host);
1947         if (ret) {
1948                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1949                 goto err_irq;
1950         }
1951
1952         if (pdata->init != NULL) {
1953                 if (pdata->init(&pdev->dev) != 0) {
1954                         dev_dbg(mmc_dev(host->mmc),
1955                                 "Unable to configure MMC IRQs\n");
1956                         goto err_irq_cd_init;
1957                 }
1958         }
1959
1960         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1961                 ret = omap_hsmmc_reg_get(host);
1962                 if (ret)
1963                         goto err_reg;
1964                 host->use_reg = 1;
1965         }
1966
1967         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1968
1969         /* Request IRQ for card detect */
1970         if ((mmc_slot(host).card_detect_irq)) {
1971                 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1972                                            NULL,
1973                                            omap_hsmmc_detect,
1974                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1975                                            mmc_hostname(mmc), host);
1976                 if (ret) {
1977                         dev_dbg(mmc_dev(host->mmc),
1978                                 "Unable to grab MMC CD IRQ\n");
1979                         goto err_irq_cd;
1980                 }
1981                 pdata->suspend = omap_hsmmc_suspend_cdirq;
1982                 pdata->resume = omap_hsmmc_resume_cdirq;
1983         }
1984
1985         omap_hsmmc_disable_irq(host);
1986
1987         omap_hsmmc_protect_card(host);
1988
1989         mmc_add_host(mmc);
1990
1991         if (mmc_slot(host).name != NULL) {
1992                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1993                 if (ret < 0)
1994                         goto err_slot_name;
1995         }
1996         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
1997                 ret = device_create_file(&mmc->class_dev,
1998                                         &dev_attr_cover_switch);
1999                 if (ret < 0)
2000                         goto err_slot_name;
2001         }
2002
2003         omap_hsmmc_debugfs(mmc);
2004         pm_runtime_mark_last_busy(host->dev);
2005         pm_runtime_put_autosuspend(host->dev);
2006
2007         return 0;
2008
2009 err_slot_name:
2010         mmc_remove_host(mmc);
2011         free_irq(mmc_slot(host).card_detect_irq, host);
2012 err_irq_cd:
2013         if (host->use_reg)
2014                 omap_hsmmc_reg_put(host);
2015 err_reg:
2016         if (host->pdata->cleanup)
2017                 host->pdata->cleanup(&pdev->dev);
2018 err_irq_cd_init:
2019         free_irq(host->irq, host);
2020 err_irq:
2021         pm_runtime_mark_last_busy(host->dev);
2022         pm_runtime_put_autosuspend(host->dev);
2023         pm_runtime_disable(host->dev);
2024         clk_put(host->fclk);
2025         if (host->got_dbclk) {
2026                 clk_disable(host->dbclk);
2027                 clk_put(host->dbclk);
2028         }
2029 err1:
2030         iounmap(host->base);
2031         platform_set_drvdata(pdev, NULL);
2032         mmc_free_host(mmc);
2033 err_alloc:
2034         omap_hsmmc_gpio_free(pdata);
2035 err:
2036         release_mem_region(res->start, resource_size(res));
2037         return ret;
2038 }
2039
2040 static int omap_hsmmc_remove(struct platform_device *pdev)
2041 {
2042         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2043         struct resource *res;
2044
2045         if (host) {
2046                 pm_runtime_get_sync(host->dev);
2047                 mmc_remove_host(host->mmc);
2048                 if (host->use_reg)
2049                         omap_hsmmc_reg_put(host);
2050                 if (host->pdata->cleanup)
2051                         host->pdata->cleanup(&pdev->dev);
2052                 free_irq(host->irq, host);
2053                 if (mmc_slot(host).card_detect_irq)
2054                         free_irq(mmc_slot(host).card_detect_irq, host);
2055
2056                 pm_runtime_put_sync(host->dev);
2057                 pm_runtime_disable(host->dev);
2058                 clk_put(host->fclk);
2059                 if (host->got_dbclk) {
2060                         clk_disable(host->dbclk);
2061                         clk_put(host->dbclk);
2062                 }
2063
2064                 mmc_free_host(host->mmc);
2065                 iounmap(host->base);
2066                 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2067         }
2068
2069         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2070         if (res)
2071                 release_mem_region(res->start, resource_size(res));
2072         platform_set_drvdata(pdev, NULL);
2073
2074         return 0;
2075 }
2076
2077 #ifdef CONFIG_PM
2078 static int omap_hsmmc_suspend(struct device *dev)
2079 {
2080         int ret = 0;
2081         struct platform_device *pdev = to_platform_device(dev);
2082         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2083
2084         if (host && host->suspended)
2085                 return 0;
2086
2087         if (host) {
2088                 pm_runtime_get_sync(host->dev);
2089                 host->suspended = 1;
2090                 if (host->pdata->suspend) {
2091                         ret = host->pdata->suspend(&pdev->dev,
2092                                                         host->slot_id);
2093                         if (ret) {
2094                                 dev_dbg(mmc_dev(host->mmc),
2095                                         "Unable to handle MMC board"
2096                                         " level suspend\n");
2097                                 host->suspended = 0;
2098                                 return ret;
2099                         }
2100                 }
2101                 ret = mmc_suspend_host(host->mmc);
2102
2103                 if (ret) {
2104                         host->suspended = 0;
2105                         if (host->pdata->resume) {
2106                                 ret = host->pdata->resume(&pdev->dev,
2107                                                           host->slot_id);
2108                                 if (ret)
2109                                         dev_dbg(mmc_dev(host->mmc),
2110                                                 "Unmask interrupt failed\n");
2111                         }
2112                         goto err;
2113                 }
2114
2115                 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2116                         omap_hsmmc_disable_irq(host);
2117                         OMAP_HSMMC_WRITE(host->base, HCTL,
2118                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2119                 }
2120                 if (host->got_dbclk)
2121                         clk_disable(host->dbclk);
2122
2123         }
2124 err:
2125         pm_runtime_put_sync(host->dev);
2126         return ret;
2127 }
2128
2129 /* Routine to resume the MMC device */
2130 static int omap_hsmmc_resume(struct device *dev)
2131 {
2132         int ret = 0;
2133         struct platform_device *pdev = to_platform_device(dev);
2134         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2135
2136         if (host && !host->suspended)
2137                 return 0;
2138
2139         if (host) {
2140                 pm_runtime_get_sync(host->dev);
2141
2142                 if (host->got_dbclk)
2143                         clk_enable(host->dbclk);
2144
2145                 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2146                         omap_hsmmc_conf_bus_power(host);
2147
2148                 if (host->pdata->resume) {
2149                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
2150                         if (ret)
2151                                 dev_dbg(mmc_dev(host->mmc),
2152                                         "Unmask interrupt failed\n");
2153                 }
2154
2155                 omap_hsmmc_protect_card(host);
2156
2157                 /* Notify the core to resume the host */
2158                 ret = mmc_resume_host(host->mmc);
2159                 if (ret == 0)
2160                         host->suspended = 0;
2161
2162                 pm_runtime_mark_last_busy(host->dev);
2163                 pm_runtime_put_autosuspend(host->dev);
2164         }
2165
2166         return ret;
2167
2168 }
2169
2170 #else
2171 #define omap_hsmmc_suspend      NULL
2172 #define omap_hsmmc_resume               NULL
2173 #endif
2174
2175 static int omap_hsmmc_runtime_suspend(struct device *dev)
2176 {
2177         struct omap_hsmmc_host *host;
2178
2179         host = platform_get_drvdata(to_platform_device(dev));
2180         omap_hsmmc_context_save(host);
2181         dev_dbg(mmc_dev(host->mmc), "disabled\n");
2182
2183         return 0;
2184 }
2185
2186 static int omap_hsmmc_runtime_resume(struct device *dev)
2187 {
2188         struct omap_hsmmc_host *host;
2189
2190         host = platform_get_drvdata(to_platform_device(dev));
2191         omap_hsmmc_context_restore(host);
2192         dev_dbg(mmc_dev(host->mmc), "enabled\n");
2193
2194         return 0;
2195 }
2196
2197 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2198         .suspend        = omap_hsmmc_suspend,
2199         .resume         = omap_hsmmc_resume,
2200         .runtime_suspend = omap_hsmmc_runtime_suspend,
2201         .runtime_resume = omap_hsmmc_runtime_resume,
2202 };
2203
2204 static struct platform_driver omap_hsmmc_driver = {
2205         .remove         = omap_hsmmc_remove,
2206         .driver         = {
2207                 .name = DRIVER_NAME,
2208                 .owner = THIS_MODULE,
2209                 .pm = &omap_hsmmc_dev_pm_ops,
2210                 .of_match_table = of_match_ptr(omap_mmc_of_match),
2211         },
2212 };
2213
2214 static int __init omap_hsmmc_init(void)
2215 {
2216         /* Register the MMC driver */
2217         return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2218 }
2219
2220 static void __exit omap_hsmmc_cleanup(void)
2221 {
2222         /* Unregister MMC driver */
2223         platform_driver_unregister(&omap_hsmmc_driver);
2224 }
2225
2226 module_init(omap_hsmmc_init);
2227 module_exit(omap_hsmmc_cleanup);
2228
2229 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2230 MODULE_LICENSE("GPL");
2231 MODULE_ALIAS("platform:" DRIVER_NAME);
2232 MODULE_AUTHOR("Texas Instruments Inc");