2 * drivers/i2c/busses/i2c-tegra.c
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/err.h>
23 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/i2c-tegra.h>
30 #include <asm/unaligned.h>
34 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
35 #define BYTES_PER_FIFO_WORD 4
37 #define I2C_CNFG 0x000
38 #define I2C_CNFG_PACKET_MODE_EN (1<<10)
39 #define I2C_CNFG_NEW_MASTER_FSM (1<<11)
40 #define I2C_SL_CNFG 0x020
41 #define I2C_SL_CNFG_NEWSL (1<<2)
42 #define I2C_SL_ADDR1 0x02c
43 #define I2C_TX_FIFO 0x050
44 #define I2C_RX_FIFO 0x054
45 #define I2C_PACKET_TRANSFER_STATUS 0x058
46 #define I2C_FIFO_CONTROL 0x05c
47 #define I2C_FIFO_CONTROL_TX_FLUSH (1<<1)
48 #define I2C_FIFO_CONTROL_RX_FLUSH (1<<0)
49 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
50 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
51 #define I2C_FIFO_STATUS 0x060
52 #define I2C_FIFO_STATUS_TX_MASK 0xF0
53 #define I2C_FIFO_STATUS_TX_SHIFT 4
54 #define I2C_FIFO_STATUS_RX_MASK 0x0F
55 #define I2C_FIFO_STATUS_RX_SHIFT 0
56 #define I2C_INT_MASK 0x064
57 #define I2C_INT_STATUS 0x068
58 #define I2C_INT_PACKET_XFER_COMPLETE (1<<7)
59 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6)
60 #define I2C_INT_TX_FIFO_OVERFLOW (1<<5)
61 #define I2C_INT_RX_FIFO_UNDERFLOW (1<<4)
62 #define I2C_INT_NO_ACK (1<<3)
63 #define I2C_INT_ARBITRATION_LOST (1<<2)
64 #define I2C_INT_TX_FIFO_DATA_REQ (1<<1)
65 #define I2C_INT_RX_FIFO_DATA_REQ (1<<0)
66 #define I2C_CLK_DIVISOR 0x06c
68 #define DVC_CTRL_REG1 0x000
69 #define DVC_CTRL_REG1_INTR_EN (1<<10)
70 #define DVC_CTRL_REG2 0x004
71 #define DVC_CTRL_REG3 0x008
72 #define DVC_CTRL_REG3_SW_PROG (1<<26)
73 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30)
74 #define DVC_STATUS 0x00c
75 #define DVC_STATUS_I2C_DONE_INTR (1<<30)
77 #define I2C_ERR_NONE 0x00
78 #define I2C_ERR_NO_ACK 0x01
79 #define I2C_ERR_ARBITRATION_LOST 0x02
81 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
82 #define PACKET_HEADER0_PACKET_ID_SHIFT 16
83 #define PACKET_HEADER0_CONT_ID_SHIFT 12
84 #define PACKET_HEADER0_PROTOCOL_I2C (1<<4)
86 #define I2C_HEADER_HIGHSPEED_MODE (1<<22)
87 #define I2C_HEADER_CONT_ON_NAK (1<<21)
88 #define I2C_HEADER_SEND_START_BYTE (1<<20)
89 #define I2C_HEADER_READ (1<<19)
90 #define I2C_HEADER_10BIT_ADDR (1<<18)
91 #define I2C_HEADER_IE_ENABLE (1<<17)
92 #define I2C_HEADER_REPEAT_START (1<<16)
93 #define I2C_HEADER_MASTER_ADDR_SHIFT 12
94 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
97 * struct tegra_i2c_dev - per device i2c context
98 * @dev: device reference for power management
99 * @adapter: core i2c layer adapter information
100 * @clk: clock reference for i2c controller
101 * @i2c_clk: clock reference for i2c bus
102 * @iomem: memory resource for registers
103 * @base: ioremapped registers cookie
104 * @cont_id: i2c controller id, used for for packet header
105 * @irq: irq number of transfer complete interrupt
106 * @is_dvc: identifies the DVC i2c controller, has a different register layout
107 * @msg_complete: transfer completion notifier
108 * @msg_err: error code for completed message
109 * @msg_buf: pointer to current message data
110 * @msg_buf_remaining: size of unsent data in the message buffer
111 * @msg_read: identifies read transfers
112 * @bus_clk_rate: current i2c bus clock rate
113 * @is_suspended: prevents i2c controller accesses after suspend is called
115 struct tegra_i2c_dev {
117 struct i2c_adapter adapter;
120 struct resource *iomem;
125 struct completion msg_complete;
128 size_t msg_buf_remaining;
130 unsigned long bus_clk_rate;
134 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
136 writel(val, i2c_dev->base + reg);
139 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
141 return readl(i2c_dev->base + reg);
145 * i2c_writel and i2c_readl will offset the register if necessary to talk
146 * to the I2C block inside the DVC block
148 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
152 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
156 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
159 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
162 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
164 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
167 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
168 unsigned long reg, int len)
170 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
173 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
174 unsigned long reg, int len)
176 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
179 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
181 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
183 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
186 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
188 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
190 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
193 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
195 unsigned long timeout = jiffies + HZ;
196 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
197 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
198 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
200 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
201 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
202 if (time_after(jiffies, timeout)) {
203 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
211 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
215 u8 *buf = i2c_dev->msg_buf;
216 size_t buf_remaining = i2c_dev->msg_buf_remaining;
217 int words_to_transfer;
219 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
220 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
221 I2C_FIFO_STATUS_RX_SHIFT;
223 /* Rounds down to not include partial word at the end of buf */
224 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
225 if (words_to_transfer > rx_fifo_avail)
226 words_to_transfer = rx_fifo_avail;
228 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
230 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
231 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
232 rx_fifo_avail -= words_to_transfer;
235 * If there is a partial word at the end of buf, handle it manually to
236 * prevent overwriting past the end of buf
238 if (rx_fifo_avail > 0 && buf_remaining > 0) {
239 BUG_ON(buf_remaining > 3);
240 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
241 memcpy(buf, &val, buf_remaining);
246 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
247 i2c_dev->msg_buf_remaining = buf_remaining;
248 i2c_dev->msg_buf = buf;
252 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
256 u8 *buf = i2c_dev->msg_buf;
257 size_t buf_remaining = i2c_dev->msg_buf_remaining;
258 int words_to_transfer;
260 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
261 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
262 I2C_FIFO_STATUS_TX_SHIFT;
264 /* Rounds down to not include partial word at the end of buf */
265 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
266 if (words_to_transfer > tx_fifo_avail)
267 words_to_transfer = tx_fifo_avail;
269 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
271 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
272 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
273 tx_fifo_avail -= words_to_transfer;
276 * If there is a partial word at the end of buf, handle it manually to
277 * prevent reading past the end of buf, which could cross a page
278 * boundary and fault.
280 if (tx_fifo_avail > 0 && buf_remaining > 0) {
281 BUG_ON(buf_remaining > 3);
282 memcpy(&val, buf, buf_remaining);
283 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
288 BUG_ON(tx_fifo_avail > 0 && buf_remaining > 0);
289 i2c_dev->msg_buf_remaining = buf_remaining;
290 i2c_dev->msg_buf = buf;
295 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
296 * block. This block is identical to the rest of the I2C blocks, except that
297 * it only supports master mode, it has registers moved around, and it needs
298 * some extra init to get it into I2C mode. The register moves are handled
299 * by i2c_readl and i2c_writel
301 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
304 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
305 val |= DVC_CTRL_REG3_SW_PROG;
306 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
307 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
309 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
310 val |= DVC_CTRL_REG1_INTR_EN;
311 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
314 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
319 clk_enable(i2c_dev->clk);
321 tegra_periph_reset_assert(i2c_dev->clk);
323 tegra_periph_reset_deassert(i2c_dev->clk);
326 tegra_dvc_init(i2c_dev);
328 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN;
329 i2c_writel(i2c_dev, val, I2C_CNFG);
330 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
331 clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8);
333 if (!i2c_dev->is_dvc) {
334 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
335 i2c_writel(i2c_dev, sl_cfg | I2C_SL_CNFG_NEWSL, I2C_SL_CNFG);
338 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
339 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
340 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
342 if (tegra_i2c_flush_fifos(i2c_dev))
345 clk_disable(i2c_dev->clk);
349 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
352 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
353 struct tegra_i2c_dev *i2c_dev = dev_id;
355 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
358 dev_warn(i2c_dev->dev, "interrupt with no status\n");
362 if (unlikely(status & status_err)) {
363 if (status & I2C_INT_NO_ACK)
364 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
365 if (status & I2C_INT_ARBITRATION_LOST)
366 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
367 complete(&i2c_dev->msg_complete);
371 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
372 if (i2c_dev->msg_buf_remaining)
373 tegra_i2c_empty_rx_fifo(i2c_dev);
378 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
379 if (i2c_dev->msg_buf_remaining)
380 tegra_i2c_fill_tx_fifo(i2c_dev);
382 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
385 if ((status & I2C_INT_PACKET_XFER_COMPLETE) &&
386 !i2c_dev->msg_buf_remaining)
387 complete(&i2c_dev->msg_complete);
389 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
391 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
394 /* An error occurred, mask all interrupts */
395 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
396 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
397 I2C_INT_RX_FIFO_DATA_REQ);
398 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
402 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
403 struct i2c_msg *msg, int stop)
409 tegra_i2c_flush_fifos(i2c_dev);
410 i2c_writel(i2c_dev, 0xFF, I2C_INT_STATUS);
415 i2c_dev->msg_buf = msg->buf;
416 i2c_dev->msg_buf_remaining = msg->len;
417 i2c_dev->msg_err = I2C_ERR_NONE;
418 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
419 INIT_COMPLETION(i2c_dev->msg_complete);
421 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
422 PACKET_HEADER0_PROTOCOL_I2C |
423 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
424 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
425 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
427 packet_header = msg->len - 1;
428 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
430 packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
431 packet_header |= I2C_HEADER_IE_ENABLE;
432 if (msg->flags & I2C_M_TEN)
433 packet_header |= I2C_HEADER_10BIT_ADDR;
434 if (msg->flags & I2C_M_IGNORE_NAK)
435 packet_header |= I2C_HEADER_CONT_ON_NAK;
436 if (msg->flags & I2C_M_NOSTART)
437 packet_header |= I2C_HEADER_REPEAT_START;
438 if (msg->flags & I2C_M_RD)
439 packet_header |= I2C_HEADER_READ;
440 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
442 if (!(msg->flags & I2C_M_RD))
443 tegra_i2c_fill_tx_fifo(i2c_dev);
445 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
446 if (msg->flags & I2C_M_RD)
447 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
448 else if (i2c_dev->msg_buf_remaining)
449 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
450 tegra_i2c_unmask_irq(i2c_dev, int_mask);
451 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
452 i2c_readl(i2c_dev, I2C_INT_MASK));
454 ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
455 tegra_i2c_mask_irq(i2c_dev, int_mask);
457 if (WARN_ON(ret == 0)) {
458 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
460 tegra_i2c_init(i2c_dev);
464 dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
465 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
467 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
470 tegra_i2c_init(i2c_dev);
471 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
472 if (msg->flags & I2C_M_IGNORE_NAK)
480 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
483 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
487 if (i2c_dev->is_suspended)
490 clk_enable(i2c_dev->clk);
491 for (i = 0; i < num; i++) {
492 int stop = (i == (num - 1)) ? 1 : 0;
493 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], stop);
497 clk_disable(i2c_dev->clk);
501 static u32 tegra_i2c_func(struct i2c_adapter *adap)
506 static const struct i2c_algorithm tegra_i2c_algo = {
507 .master_xfer = tegra_i2c_xfer,
508 .functionality = tegra_i2c_func,
511 static int tegra_i2c_probe(struct platform_device *pdev)
513 struct tegra_i2c_dev *i2c_dev;
514 struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
515 struct resource *res;
516 struct resource *iomem;
523 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
525 dev_err(&pdev->dev, "no mem resource\n");
528 iomem = request_mem_region(res->start, resource_size(res), pdev->name);
530 dev_err(&pdev->dev, "I2C region already claimed\n");
534 base = ioremap(iomem->start, resource_size(iomem));
536 dev_err(&pdev->dev, "Cannot ioremap I2C region\n");
540 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
542 dev_err(&pdev->dev, "no irq resource\n");
548 clk = clk_get(&pdev->dev, NULL);
550 dev_err(&pdev->dev, "missing controller clock");
552 goto err_release_region;
555 i2c_clk = clk_get(&pdev->dev, "i2c");
556 if (IS_ERR(i2c_clk)) {
557 dev_err(&pdev->dev, "missing bus clock");
558 ret = PTR_ERR(i2c_clk);
562 i2c_dev = kzalloc(sizeof(struct tegra_i2c_dev), GFP_KERNEL);
565 goto err_i2c_clk_put;
568 i2c_dev->base = base;
570 i2c_dev->i2c_clk = i2c_clk;
571 i2c_dev->iomem = iomem;
572 i2c_dev->adapter.algo = &tegra_i2c_algo;
574 i2c_dev->cont_id = pdev->id;
575 i2c_dev->dev = &pdev->dev;
576 i2c_dev->bus_clk_rate = pdata ? pdata->bus_clk_rate : 100000;
580 init_completion(&i2c_dev->msg_complete);
582 platform_set_drvdata(pdev, i2c_dev);
584 ret = tegra_i2c_init(i2c_dev);
586 dev_err(&pdev->dev, "Failed to initialize i2c controller");
590 ret = request_irq(i2c_dev->irq, tegra_i2c_isr, 0, pdev->name, i2c_dev);
592 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
596 clk_enable(i2c_dev->i2c_clk);
598 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
599 i2c_dev->adapter.owner = THIS_MODULE;
600 i2c_dev->adapter.class = I2C_CLASS_HWMON;
601 strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
602 sizeof(i2c_dev->adapter.name));
603 i2c_dev->adapter.algo = &tegra_i2c_algo;
604 i2c_dev->adapter.dev.parent = &pdev->dev;
605 i2c_dev->adapter.nr = pdev->id;
607 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
609 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
615 free_irq(i2c_dev->irq, i2c_dev);
623 release_mem_region(iomem->start, resource_size(iomem));
629 static int tegra_i2c_remove(struct platform_device *pdev)
631 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
632 i2c_del_adapter(&i2c_dev->adapter);
633 free_irq(i2c_dev->irq, i2c_dev);
634 clk_put(i2c_dev->i2c_clk);
635 clk_put(i2c_dev->clk);
636 release_mem_region(i2c_dev->iomem->start,
637 resource_size(i2c_dev->iomem));
638 iounmap(i2c_dev->base);
644 static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state)
646 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
648 i2c_lock_adapter(&i2c_dev->adapter);
649 i2c_dev->is_suspended = true;
650 i2c_unlock_adapter(&i2c_dev->adapter);
655 static int tegra_i2c_resume(struct platform_device *pdev)
657 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
660 i2c_lock_adapter(&i2c_dev->adapter);
662 ret = tegra_i2c_init(i2c_dev);
665 i2c_unlock_adapter(&i2c_dev->adapter);
669 i2c_dev->is_suspended = false;
671 i2c_unlock_adapter(&i2c_dev->adapter);
677 static struct platform_driver tegra_i2c_driver = {
678 .probe = tegra_i2c_probe,
679 .remove = tegra_i2c_remove,
681 .suspend = tegra_i2c_suspend,
682 .resume = tegra_i2c_resume,
686 .owner = THIS_MODULE,
690 static int __init tegra_i2c_init_driver(void)
692 return platform_driver_register(&tegra_i2c_driver);
695 static void __exit tegra_i2c_exit_driver(void)
697 platform_driver_unregister(&tegra_i2c_driver);
700 subsys_initcall(tegra_i2c_init_driver);
701 module_exit(tegra_i2c_exit_driver);
703 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
704 MODULE_AUTHOR("Colin Cross");
705 MODULE_LICENSE("GPL v2");