sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM1811_JACKDET_MODE_NONE  0x0000
  42 #define WM1811_JACKDET_MODE_JACK  0x0100
  43 #define WM1811_JACKDET_MODE_MIC   0x0080
  44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
  45
  46 #define WM8994_NUM_DRC 3
  47 #define WM8994_NUM_EQ  3
  48
  49 static int wm8994_drc_base[] = {
  50         WM8994_AIF1_DRC1_1,
  51         WM8994_AIF1_DRC2_1,
  52         WM8994_AIF2_DRC_1,
  53 };
  54
  55 static int wm8994_retune_mobile_base[] = {
  56         WM8994_AIF1_DAC1_EQ_GAINS_1,
  57         WM8994_AIF1_DAC2_EQ_GAINS_1,
  58         WM8994_AIF2_EQ_GAINS_1,
  59 };
  60
  61 static void wm8958_default_micdet(u16 status, void *data);
  62
  63 static const struct wm8958_micd_rate micdet_rates[] = {
  64         { 32768,       true,  1, 4 },
  65         { 32768,       false, 1, 1 },
  66         { 44100 * 256, true,  7, 10 },
  67         { 44100 * 256, false, 7, 10 },
  68 };
  69
  70 static const struct wm8958_micd_rate jackdet_rates[] = {
  71         { 32768,       true,  0, 1 },
  72         { 32768,       false, 0, 1 },
  73         { 44100 * 256, true,  7, 10 },
  74         { 44100 * 256, false, 7, 10 },
  75 };
  76
  77 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
  78 {
  79         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  80         int best, i, sysclk, val;
  81         bool idle;
  82         const struct wm8958_micd_rate *rates;
  83         int num_rates;
  84
  85         if (wm8994->jack_cb != wm8958_default_micdet)
  86                 return;
  87
  88         idle = !wm8994->jack_mic;
  89
  90         sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
  91         if (sysclk & WM8994_SYSCLK_SRC)
  92                 sysclk = wm8994->aifclk[1];
  93         else
  94                 sysclk = wm8994->aifclk[0];
  95
  96         if (wm8994->pdata && wm8994->pdata->micd_rates) {
  97                 rates = wm8994->pdata->micd_rates;
  98                 num_rates = wm8994->pdata->num_micd_rates;
  99         } else if (wm8994->jackdet) {
 100                 rates = jackdet_rates;
 101                 num_rates = ARRAY_SIZE(jackdet_rates);
 102         } else {
 103                 rates = micdet_rates;
 104                 num_rates = ARRAY_SIZE(micdet_rates);
 105         }
 106
 107         best = 0;
 108         for (i = 0; i < num_rates; i++) {
 109                 if (rates[i].idle != idle)
 110                         continue;
 111                 if (abs(rates[i].sysclk - sysclk) <
 112                     abs(rates[best].sysclk - sysclk))
 113                         best = i;
 114                 else if (rates[best].idle != idle)
 115                         best = i;
 116         }
 117
 118         val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
 119                 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
 120
 121         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
 122                             WM8958_MICD_BIAS_STARTTIME_MASK |
 123                             WM8958_MICD_RATE_MASK, val);
 124 }
 125
 126 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 127 {
 128         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 129         int rate;
 130         int reg1 = 0;
 131         int offset;
 132
 133         if (aif)
 134                 offset = 4;
 135         else
 136                 offset = 0;
 137
 138         switch (wm8994->sysclk[aif]) {
 139         case WM8994_SYSCLK_MCLK1:
 140                 rate = wm8994->mclk[0];
 141                 break;
 142
 143         case WM8994_SYSCLK_MCLK2:
 144                 reg1 |= 0x8;
 145                 rate = wm8994->mclk[1];
 146                 break;
 147
 148         case WM8994_SYSCLK_FLL1:
 149                 reg1 |= 0x10;
 150                 rate = wm8994->fll[0].out;
 151                 break;
 152
 153         case WM8994_SYSCLK_FLL2:
 154                 reg1 |= 0x18;
 155                 rate = wm8994->fll[1].out;
 156                 break;
 157
 158         default:
 159                 return -EINVAL;
 160         }
 161
 162         if (rate >= 13500000) {
 163                 rate /= 2;
 164                 reg1 |= WM8994_AIF1CLK_DIV;
 165
 166                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 167                         aif + 1, rate);
 168         }
 169
 170         wm8994->aifclk[aif] = rate;
 171
 172         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 173                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 174                             reg1);
 175
 176         return 0;
 177 }
 178
 179 static int configure_clock(struct snd_soc_codec *codec)
 180 {
 181         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 182         int change, new;
 183
 184         /* Bring up the AIF clocks first */
 185         configure_aif_clock(codec, 0);
 186         configure_aif_clock(codec, 1);
 187
 188         /* Then switch CLK_SYS over to the higher of them; a change
 189          * can only happen as a result of a clocking change which can
 190          * only be made outside of DAPM so we can safely redo the
 191          * clocking.
 192          */
 193
 194         /* If they're equal it doesn't matter which is used */
 195         if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
 196                 wm8958_micd_set_rate(codec);
 197                 return 0;
 198         }
 199
 200         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 201                 new = WM8994_SYSCLK_SRC;
 202         else
 203                 new = 0;
 204
 205         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 206                                      WM8994_SYSCLK_SRC, new);
 207         if (change)
 208                 snd_soc_dapm_sync(&codec->dapm);
 209
 210         wm8958_micd_set_rate(codec);
 211
 212         return 0;
 213 }
 214
 215 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 216                          struct snd_soc_dapm_widget *sink)
 217 {
 218         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 219         const char *clk;
 220
 221         /* Check what we're currently using for CLK_SYS */
 222         if (reg & WM8994_SYSCLK_SRC)
 223                 clk = "AIF2CLK";
 224         else
 225                 clk = "AIF1CLK";
 226
 227         return strcmp(source->name, clk) == 0;
 228 }
 229
 230 static const char *sidetone_hpf_text[] = {
 231         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 232 };
 233
 234 static const struct soc_enum sidetone_hpf =
 235         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 236
 237 static const char *adc_hpf_text[] = {
 238         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 239 };
 240
 241 static const struct soc_enum aif1adc1_hpf =
 242         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 243
 244 static const struct soc_enum aif1adc2_hpf =
 245         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 246
 247 static const struct soc_enum aif2adc_hpf =
 248         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 249
 250 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 251 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 252 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 253 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 254 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 255 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
 256 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
 257
 258 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 259 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 260         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 261         .put = wm8994_put_drc_sw, \
 262         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 263
 264 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 265                              struct snd_ctl_elem_value *ucontrol)
 266 {
 267         struct soc_mixer_control *mc =
 268                 (struct soc_mixer_control *)kcontrol->private_value;
 269         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 270         int mask, ret;
 271
 272         /* Can't enable both ADC and DAC paths simultaneously */
 273         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 274                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 275                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 276         else
 277                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 278
 279         ret = snd_soc_read(codec, mc->reg);
 280         if (ret < 0)
 281                 return ret;
 282         if (ret & mask)
 283                 return -EINVAL;
 284
 285         return snd_soc_put_volsw(kcontrol, ucontrol);
 286 }
 287
 288 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 289 {
 290         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 291         struct wm8994_pdata *pdata = wm8994->pdata;
 292         int base = wm8994_drc_base[drc];
 293         int cfg = wm8994->drc_cfg[drc];
 294         int save, i;
 295
 296         /* Save any enables; the configuration should clear them. */
 297         save = snd_soc_read(codec, base);
 298         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 299                 WM8994_AIF1ADC1R_DRC_ENA;
 300
 301         for (i = 0; i < WM8994_DRC_REGS; i++)
 302                 snd_soc_update_bits(codec, base + i, 0xffff,
 303                                     pdata->drc_cfgs[cfg].regs[i]);
 304
 305         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 306                              WM8994_AIF1ADC1L_DRC_ENA |
 307                              WM8994_AIF1ADC1R_DRC_ENA, save);
 308 }
 309
 310 /* Icky as hell but saves code duplication */
 311 static int wm8994_get_drc(const char *name)
 312 {
 313         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 314                 return 0;
 315         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 316                 return 1;
 317         if (strcmp(name, "AIF2DRC Mode") == 0)
 318                 return 2;
 319         return -EINVAL;
 320 }
 321
 322 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 323                                struct snd_ctl_elem_value *ucontrol)
 324 {
 325         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 326         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 327         struct wm8994_pdata *pdata = wm8994->pdata;
 328         int drc = wm8994_get_drc(kcontrol->id.name);
 329         int value = ucontrol->value.integer.value[0];
 330
 331         if (drc < 0)
 332                 return drc;
 333
 334         if (value >= pdata->num_drc_cfgs)
 335                 return -EINVAL;
 336
 337         wm8994->drc_cfg[drc] = value;
 338
 339         wm8994_set_drc(codec, drc);
 340
 341         return 0;
 342 }
 343
 344 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 345                                struct snd_ctl_elem_value *ucontrol)
 346 {
 347         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 348         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 349         int drc = wm8994_get_drc(kcontrol->id.name);
 350
 351         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 352
 353         return 0;
 354 }
 355
 356 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 357 {
 358         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 359         struct wm8994_pdata *pdata = wm8994->pdata;
 360         int base = wm8994_retune_mobile_base[block];
 361         int iface, best, best_val, save, i, cfg;
 362
 363         if (!pdata || !wm8994->num_retune_mobile_texts)
 364                 return;
 365
 366         switch (block) {
 367         case 0:
 368         case 1:
 369                 iface = 0;
 370                 break;
 371         case 2:
 372                 iface = 1;
 373                 break;
 374         default:
 375                 return;
 376         }
 377
 378         /* Find the version of the currently selected configuration
 379          * with the nearest sample rate. */
 380         cfg = wm8994->retune_mobile_cfg[block];
 381         best = 0;
 382         best_val = INT_MAX;
 383         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 384                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 385                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 386                     abs(pdata->retune_mobile_cfgs[i].rate
 387                         - wm8994->dac_rates[iface]) < best_val) {
 388                         best = i;
 389                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 390                                        - wm8994->dac_rates[iface]);
 391                 }
 392         }
 393
 394         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 395                 block,
 396                 pdata->retune_mobile_cfgs[best].name,
 397                 pdata->retune_mobile_cfgs[best].rate,
 398                 wm8994->dac_rates[iface]);
 399
 400         /* The EQ will be disabled while reconfiguring it, remember the
 401          * current configuration.
 402          */
 403         save = snd_soc_read(codec, base);
 404         save &= WM8994_AIF1DAC1_EQ_ENA;
 405
 406         for (i = 0; i < WM8994_EQ_REGS; i++)
 407                 snd_soc_update_bits(codec, base + i, 0xffff,
 408                                 pdata->retune_mobile_cfgs[best].regs[i]);
 409
 410         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 411 }
 412
 413 /* Icky as hell but saves code duplication */
 414 static int wm8994_get_retune_mobile_block(const char *name)
 415 {
 416         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 417                 return 0;
 418         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 419                 return 1;
 420         if (strcmp(name, "AIF2 EQ Mode") == 0)
 421                 return 2;
 422         return -EINVAL;
 423 }
 424
 425 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 426                                          struct snd_ctl_elem_value *ucontrol)
 427 {
 428         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 429         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 430         struct wm8994_pdata *pdata = wm8994->pdata;
 431         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 432         int value = ucontrol->value.integer.value[0];
 433
 434         if (block < 0)
 435                 return block;
 436
 437         if (value >= pdata->num_retune_mobile_cfgs)
 438                 return -EINVAL;
 439
 440         wm8994->retune_mobile_cfg[block] = value;
 441
 442         wm8994_set_retune_mobile(codec, block);
 443
 444         return 0;
 445 }
 446
 447 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 448                                          struct snd_ctl_elem_value *ucontrol)
 449 {
 450         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 451         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 452         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 453
 454         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 455
 456         return 0;
 457 }
 458
 459 static const char *aif_chan_src_text[] = {
 460         "Left", "Right"
 461 };
 462
 463 static const struct soc_enum aif1adcl_src =
 464         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 465
 466 static const struct soc_enum aif1adcr_src =
 467         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 468
 469 static const struct soc_enum aif2adcl_src =
 470         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 471
 472 static const struct soc_enum aif2adcr_src =
 473         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 474
 475 static const struct soc_enum aif1dacl_src =
 476         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 477
 478 static const struct soc_enum aif1dacr_src =
 479         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 480
 481 static const struct soc_enum aif2dacl_src =
 482         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 483
 484 static const struct soc_enum aif2dacr_src =
 485         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 486
 487 static const char *osr_text[] = {
 488         "Low Power", "High Performance",
 489 };
 490
 491 static const struct soc_enum dac_osr =
 492         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 493
 494 static const struct soc_enum adc_osr =
 495         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 496
 497 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 498 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 499                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 500                  1, 119, 0, digital_tlv),
 501 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 502                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 503                  1, 119, 0, digital_tlv),
 504 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 505                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 506                  1, 119, 0, digital_tlv),
 507
 508 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 509 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 510 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 511 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 512
 513 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 514 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 515 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 516 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 517
 518 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 519                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 520 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 521                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 522 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 523                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 524
 525 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 526 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 527
 528 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 529 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 530 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 531
 532 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 533 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 534 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 535
 536 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 537 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 538 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 539
 540 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 541 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 542 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 543
 544 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 545                5, 12, 0, st_tlv),
 546 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 547                0, 12, 0, st_tlv),
 548 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 549                5, 12, 0, st_tlv),
 550 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 551                0, 12, 0, st_tlv),
 552 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 553 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 554
 555 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 556 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 557
 558 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 559 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 560
 561 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 562 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 563
 564 SOC_ENUM("ADC OSR", adc_osr),
 565 SOC_ENUM("DAC OSR", dac_osr),
 566
 567 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 568                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 569 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 570              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 571
 572 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 573                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 574 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 575              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 576
 577 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 578                6, 1, 1, wm_hubs_spkmix_tlv),
 579 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 580                2, 1, 1, wm_hubs_spkmix_tlv),
 581
 582 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 583                6, 1, 1, wm_hubs_spkmix_tlv),
 584 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 585                2, 1, 1, wm_hubs_spkmix_tlv),
 586
 587 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 588                10, 15, 0, wm8994_3d_tlv),
 589 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 590            8, 1, 0),
 591 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 592                10, 15, 0, wm8994_3d_tlv),
 593 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 594            8, 1, 0),
 595 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 596                10, 15, 0, wm8994_3d_tlv),
 597 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 598            8, 1, 0),
 599 };
 600
 601 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 602 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 603                eq_tlv),
 604 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 605                eq_tlv),
 606 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 607                eq_tlv),
 608 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 609                eq_tlv),
 610 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 611                eq_tlv),
 612
 613 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 614                eq_tlv),
 615 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 616                eq_tlv),
 617 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 618                eq_tlv),
 619 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 620                eq_tlv),
 621 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 622                eq_tlv),
 623
 624 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 625                eq_tlv),
 626 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 627                eq_tlv),
 628 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 629                eq_tlv),
 630 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 631                eq_tlv),
 632 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 633                eq_tlv),
 634 };
 635
 636 static const char *wm8958_ng_text[] = {
 637         "30ms", "125ms", "250ms", "500ms",
 638 };
 639
 640 static const struct soc_enum wm8958_aif1dac1_ng_hold =
 641         SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
 642                         WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
 643
 644 static const struct soc_enum wm8958_aif1dac2_ng_hold =
 645         SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
 646                         WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
 647
 648 static const struct soc_enum wm8958_aif2dac_ng_hold =
 649         SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
 650                         WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
 651
 652 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 653 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 654
 655 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
 656            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
 657 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
 658 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
 659                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
 660                7, 1, ng_tlv),
 661
 662 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
 663            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
 664 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
 665 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
 666                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
 667                7, 1, ng_tlv),
 668
 669 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
 670            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
 671 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
 672 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
 673                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
 674                7, 1, ng_tlv),
 675 };
 676
 677 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
 678 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
 679                mixin_boost_tlv),
 680 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
 681                mixin_boost_tlv),
 682 };
 683
 684 /* We run all mode setting through a function to enforce audio mode */
 685 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
 686 {
 687         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 688
 689         if (wm8994->active_refcount)
 690                 mode = WM1811_JACKDET_MODE_AUDIO;
 691
 692         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 693                             WM1811_JACKDET_MODE_MASK, mode);
 694
 695         if (mode == WM1811_JACKDET_MODE_MIC)
 696                 msleep(2);
 697 }
 698
 699 static void active_reference(struct snd_soc_codec *codec)
 700 {
 701         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 702
 703         mutex_lock(&wm8994->accdet_lock);
 704
 705         wm8994->active_refcount++;
 706
 707         dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
 708                 wm8994->active_refcount);
 709
 710         if (wm8994->active_refcount == 1) {
 711                 /* If we're using jack detection go into audio mode */
 712                 if (wm8994->jackdet && wm8994->jack_cb) {
 713                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 714                                             WM1811_JACKDET_MODE_MASK,
 715                                             WM1811_JACKDET_MODE_AUDIO);
 716                         msleep(2);
 717                 }
 718         }
 719
 720         mutex_unlock(&wm8994->accdet_lock);
 721 }
 722
 723 static void active_dereference(struct snd_soc_codec *codec)
 724 {
 725         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 726         u16 mode;
 727
 728         mutex_lock(&wm8994->accdet_lock);
 729
 730         wm8994->active_refcount--;
 731
 732         dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
 733                 wm8994->active_refcount);
 734
 735         if (wm8994->active_refcount == 0) {
 736                 /* Go into appropriate detection only mode */
 737                 if (wm8994->jackdet && wm8994->jack_cb) {
 738                         if (wm8994->jack_mic || wm8994->mic_detecting)
 739                                 mode = WM1811_JACKDET_MODE_MIC;
 740                         else
 741                                 mode = WM1811_JACKDET_MODE_JACK;
 742
 743                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 744                                             WM1811_JACKDET_MODE_MASK,
 745                                             mode);
 746                 }
 747         }
 748
 749         mutex_unlock(&wm8994->accdet_lock);
 750 }
 751
 752 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 753                          struct snd_kcontrol *kcontrol, int event)
 754 {
 755         struct snd_soc_codec *codec = w->codec;
 756
 757         switch (event) {
 758         case SND_SOC_DAPM_PRE_PMU:
 759                 return configure_clock(codec);
 760
 761         case SND_SOC_DAPM_POST_PMD:
 762                 configure_clock(codec);
 763                 break;
 764         }
 765
 766         return 0;
 767 }
 768
 769 static void vmid_reference(struct snd_soc_codec *codec)
 770 {
 771         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 772
 773         pm_runtime_get_sync(codec->dev);
 774
 775         wm8994->vmid_refcount++;
 776
 777         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
 778                 wm8994->vmid_refcount);
 779
 780         if (wm8994->vmid_refcount == 1) {
 781                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 782                                     WM8994_LINEOUT_VMID_BUF_ENA |
 783                                     WM8994_LINEOUT1_DISCH |
 784                                     WM8994_LINEOUT2_DISCH,
 785                                     WM8994_LINEOUT_VMID_BUF_ENA);
 786
 787                 wm_hubs_vmid_ena(codec);
 788
 789                 /* Startup bias, VMID ramp & buffer */
 790                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 791                                     WM8994_BIAS_SRC |
 792                                     WM8994_VMID_DISCH |
 793                                     WM8994_STARTUP_BIAS_ENA |
 794                                     WM8994_VMID_BUF_ENA |
 795                                     WM8994_VMID_RAMP_MASK,
 796                                     WM8994_BIAS_SRC |
 797                                     WM8994_STARTUP_BIAS_ENA |
 798                                     WM8994_VMID_BUF_ENA |
 799                                     (0x2 << WM8994_VMID_RAMP_SHIFT));
 800
 801                 /* Main bias enable, VMID=2x40k */
 802                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 803                                     WM8994_BIAS_ENA |
 804                                     WM8994_VMID_SEL_MASK,
 805                                     WM8994_BIAS_ENA | 0x2);
 806
 807                 msleep(50);
 808
 809                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 810                                     WM8994_VMID_RAMP_MASK | WM8994_BIAS_SRC,
 811                                     0);
 812         }
 813 }
 814
 815 static void vmid_dereference(struct snd_soc_codec *codec)
 816 {
 817         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 818
 819         wm8994->vmid_refcount--;
 820
 821         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
 822                 wm8994->vmid_refcount);
 823
 824         if (wm8994->vmid_refcount == 0) {
 825                 /* Switch over to startup biases */
 826                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 827                                     WM8994_BIAS_SRC |
 828                                     WM8994_STARTUP_BIAS_ENA |
 829                                     WM8994_VMID_BUF_ENA |
 830                                     WM8994_VMID_RAMP_MASK,
 831                                     WM8994_BIAS_SRC |
 832                                     WM8994_STARTUP_BIAS_ENA |
 833                                     WM8994_VMID_BUF_ENA |
 834                                     (1 << WM8994_VMID_RAMP_SHIFT));
 835
 836                 /* Disable main biases */
 837                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 838                                     WM8994_BIAS_ENA |
 839                                     WM8994_VMID_SEL_MASK, 0);
 840
 841                 /* Discharge VMID */
 842                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 843                                     WM8994_VMID_DISCH, WM8994_VMID_DISCH);
 844
 845                 /* Discharge line */
 846                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 847                                     WM8994_LINEOUT1_DISCH |
 848                                     WM8994_LINEOUT2_DISCH,
 849                                     WM8994_LINEOUT1_DISCH |
 850                                     WM8994_LINEOUT2_DISCH);
 851
 852                 msleep(5);
 853
 854                 /* Switch off startup biases */
 855                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 856                                     WM8994_BIAS_SRC |
 857                                     WM8994_STARTUP_BIAS_ENA |
 858                                     WM8994_VMID_BUF_ENA |
 859                                     WM8994_VMID_RAMP_MASK, 0);
 860         }
 861
 862         pm_runtime_put(codec->dev);
 863 }
 864
 865 static int vmid_event(struct snd_soc_dapm_widget *w,
 866                       struct snd_kcontrol *kcontrol, int event)
 867 {
 868         struct snd_soc_codec *codec = w->codec;
 869
 870         switch (event) {
 871         case SND_SOC_DAPM_PRE_PMU:
 872                 vmid_reference(codec);
 873                 break;
 874
 875         case SND_SOC_DAPM_POST_PMD:
 876                 vmid_dereference(codec);
 877                 break;
 878         }
 879
 880         return 0;
 881 }
 882
 883 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 884 {
 885         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 886         int enable = 1;
 887         int source = 0;  /* GCC flow analysis can't track enable */
 888         int reg, reg_r;
 889
 890         /* Only support direct DAC->headphone paths */
 891         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 892         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 893                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 894                 enable = 0;
 895         }
 896
 897         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 898         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 899                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 900                 enable = 0;
 901         }
 902
 903         /* We also need the same setting for L/R and only one path */
 904         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 905         switch (reg) {
 906         case WM8994_AIF2DACL_TO_DAC1L:
 907                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 908                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 909                 break;
 910         case WM8994_AIF1DAC2L_TO_DAC1L:
 911                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 912                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 913                 break;
 914         case WM8994_AIF1DAC1L_TO_DAC1L:
 915                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 916                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 917                 break;
 918         default:
 919                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 920                 enable = 0;
 921                 break;
 922         }
 923
 924         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 925         if (reg_r != reg) {
 926                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 927                 enable = 0;
 928         }
 929
 930         if (enable) {
 931                 dev_dbg(codec->dev, "Class W enabled\n");
 932                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 933                                     WM8994_CP_DYN_PWR |
 934                                     WM8994_CP_DYN_SRC_SEL_MASK,
 935                                     source | WM8994_CP_DYN_PWR);
 936                 wm8994->hubs.class_w = true;
 937
 938         } else {
 939                 dev_dbg(codec->dev, "Class W disabled\n");
 940                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 941                                     WM8994_CP_DYN_PWR, 0);
 942                 wm8994->hubs.class_w = false;
 943         }
 944 }
 945
 946 static int late_enable_ev(struct snd_soc_dapm_widget *w,
 947                           struct snd_kcontrol *kcontrol, int event)
 948 {
 949         struct snd_soc_codec *codec = w->codec;
 950         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 951
 952         switch (event) {
 953         case SND_SOC_DAPM_PRE_PMU:
 954                 if (wm8994->aif1clk_enable) {
 955                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 956                                             WM8994_AIF1CLK_ENA_MASK,
 957                                             WM8994_AIF1CLK_ENA);
 958                         wm8994->aif1clk_enable = 0;
 959                 }
 960                 if (wm8994->aif2clk_enable) {
 961                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 962                                             WM8994_AIF2CLK_ENA_MASK,
 963                                             WM8994_AIF2CLK_ENA);
 964                         wm8994->aif2clk_enable = 0;
 965                 }
 966                 break;
 967         }
 968
 969         /* We may also have postponed startup of DSP, handle that. */
 970         wm8958_aif_ev(w, kcontrol, event);
 971
 972         return 0;
 973 }
 974
 975 static int late_disable_ev(struct snd_soc_dapm_widget *w,
 976                            struct snd_kcontrol *kcontrol, int event)
 977 {
 978         struct snd_soc_codec *codec = w->codec;
 979         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 980
 981         switch (event) {
 982         case SND_SOC_DAPM_POST_PMD:
 983                 if (wm8994->aif1clk_disable) {
 984                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 985                                             WM8994_AIF1CLK_ENA_MASK, 0);
 986                         wm8994->aif1clk_disable = 0;
 987                 }
 988                 if (wm8994->aif2clk_disable) {
 989                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 990                                             WM8994_AIF2CLK_ENA_MASK, 0);
 991                         wm8994->aif2clk_disable = 0;
 992                 }
 993                 break;
 994         }
 995
 996         return 0;
 997 }
 998
 999 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1000                       struct snd_kcontrol *kcontrol, int event)
1001 {
1002         struct snd_soc_codec *codec = w->codec;
1003         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1004
1005         switch (event) {
1006         case SND_SOC_DAPM_PRE_PMU:
1007                 wm8994->aif1clk_enable = 1;
1008                 break;
1009         case SND_SOC_DAPM_POST_PMD:
1010                 wm8994->aif1clk_disable = 1;
1011                 break;
1012         }
1013
1014         return 0;
1015 }
1016
1017 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1018                       struct snd_kcontrol *kcontrol, int event)
1019 {
1020         struct snd_soc_codec *codec = w->codec;
1021         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1022
1023         switch (event) {
1024         case SND_SOC_DAPM_PRE_PMU:
1025                 wm8994->aif2clk_enable = 1;
1026                 break;
1027         case SND_SOC_DAPM_POST_PMD:
1028                 wm8994->aif2clk_disable = 1;
1029                 break;
1030         }
1031
1032         return 0;
1033 }
1034
1035 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1036                       struct snd_kcontrol *kcontrol, int event)
1037 {
1038         late_enable_ev(w, kcontrol, event);
1039         return 0;
1040 }
1041
1042 static int micbias_ev(struct snd_soc_dapm_widget *w,
1043                       struct snd_kcontrol *kcontrol, int event)
1044 {
1045         late_enable_ev(w, kcontrol, event);
1046         return 0;
1047 }
1048
1049 static int dac_ev(struct snd_soc_dapm_widget *w,
1050                   struct snd_kcontrol *kcontrol, int event)
1051 {
1052         struct snd_soc_codec *codec = w->codec;
1053         unsigned int mask = 1 << w->shift;
1054
1055         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1056                             mask, mask);
1057         return 0;
1058 }
1059
1060 static const char *hp_mux_text[] = {
1061         "Mixer",
1062         "DAC",
1063 };
1064
1065 #define WM8994_HP_ENUM(xname, xenum) \
1066 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1067         .info = snd_soc_info_enum_double, \
1068         .get = snd_soc_dapm_get_enum_double, \
1069         .put = wm8994_put_hp_enum, \
1070         .private_value = (unsigned long)&xenum }
1071
1072 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1073                               struct snd_ctl_elem_value *ucontrol)
1074 {
1075         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1076         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1077         struct snd_soc_codec *codec = w->codec;
1078         int ret;
1079
1080         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1081
1082         wm8994_update_class_w(codec);
1083
1084         return ret;
1085 }
1086
1087 static const struct soc_enum hpl_enum =
1088         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1089
1090 static const struct snd_kcontrol_new hpl_mux =
1091         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1092
1093 static const struct soc_enum hpr_enum =
1094         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1095
1096 static const struct snd_kcontrol_new hpr_mux =
1097         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1098
1099 static const char *adc_mux_text[] = {
1100         "ADC",
1101         "DMIC",
1102 };
1103
1104 static const struct soc_enum adc_enum =
1105         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1106
1107 static const struct snd_kcontrol_new adcl_mux =
1108         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1109
1110 static const struct snd_kcontrol_new adcr_mux =
1111         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1112
1113 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1114 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1115 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1116 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1117 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1118 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1119 };
1120
1121 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1122 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1123 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1124 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1125 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1126 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1127 };
1128
1129 /* Debugging; dump chip status after DAPM transitions */
1130 static int post_ev(struct snd_soc_dapm_widget *w,
1131             struct snd_kcontrol *kcontrol, int event)
1132 {
1133         struct snd_soc_codec *codec = w->codec;
1134         dev_dbg(codec->dev, "SRC status: %x\n",
1135                 snd_soc_read(codec,
1136                              WM8994_RATE_STATUS));
1137         return 0;
1138 }
1139
1140 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1141 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1142                 1, 1, 0),
1143 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1144                 0, 1, 0),
1145 };
1146
1147 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1148 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1149                 1, 1, 0),
1150 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1151                 0, 1, 0),
1152 };
1153
1154 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1155 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1156                 1, 1, 0),
1157 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1158                 0, 1, 0),
1159 };
1160
1161 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1162 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1163                 1, 1, 0),
1164 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1165                 0, 1, 0),
1166 };
1167
1168 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1169 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1170                 5, 1, 0),
1171 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1172                 4, 1, 0),
1173 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1174                 2, 1, 0),
1175 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1176                 1, 1, 0),
1177 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1178                 0, 1, 0),
1179 };
1180
1181 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1182 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1183                 5, 1, 0),
1184 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1185                 4, 1, 0),
1186 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1187                 2, 1, 0),
1188 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1189                 1, 1, 0),
1190 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1191                 0, 1, 0),
1192 };
1193
1194 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1195 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1196         .info = snd_soc_info_volsw, \
1197         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1198         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1199
1200 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1201                               struct snd_ctl_elem_value *ucontrol)
1202 {
1203         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1204         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1205         struct snd_soc_codec *codec = w->codec;
1206         int ret;
1207
1208         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1209
1210         wm8994_update_class_w(codec);
1211
1212         return ret;
1213 }
1214
1215 static const struct snd_kcontrol_new dac1l_mix[] = {
1216 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1217                       5, 1, 0),
1218 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1219                       4, 1, 0),
1220 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1221                       2, 1, 0),
1222 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1223                       1, 1, 0),
1224 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1225                       0, 1, 0),
1226 };
1227
1228 static const struct snd_kcontrol_new dac1r_mix[] = {
1229 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1230                       5, 1, 0),
1231 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1232                       4, 1, 0),
1233 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1234                       2, 1, 0),
1235 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1236                       1, 1, 0),
1237 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1238                       0, 1, 0),
1239 };
1240
1241 static const char *sidetone_text[] = {
1242         "ADC/DMIC1", "DMIC2",
1243 };
1244
1245 static const struct soc_enum sidetone1_enum =
1246         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1247
1248 static const struct snd_kcontrol_new sidetone1_mux =
1249         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1250
1251 static const struct soc_enum sidetone2_enum =
1252         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1253
1254 static const struct snd_kcontrol_new sidetone2_mux =
1255         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1256
1257 static const char *aif1dac_text[] = {
1258         "AIF1DACDAT", "AIF3DACDAT",
1259 };
1260
1261 static const struct soc_enum aif1dac_enum =
1262         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1263
1264 static const struct snd_kcontrol_new aif1dac_mux =
1265         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1266
1267 static const char *aif2dac_text[] = {
1268         "AIF2DACDAT", "AIF3DACDAT",
1269 };
1270
1271 static const struct soc_enum aif2dac_enum =
1272         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1273
1274 static const struct snd_kcontrol_new aif2dac_mux =
1275         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1276
1277 static const char *aif2adc_text[] = {
1278         "AIF2ADCDAT", "AIF3DACDAT",
1279 };
1280
1281 static const struct soc_enum aif2adc_enum =
1282         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1283
1284 static const struct snd_kcontrol_new aif2adc_mux =
1285         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1286
1287 static const char *aif3adc_text[] = {
1288         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1289 };
1290
1291 static const struct soc_enum wm8994_aif3adc_enum =
1292         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1293
1294 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1295         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1296
1297 static const struct soc_enum wm8958_aif3adc_enum =
1298         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1299
1300 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1301         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1302
1303 static const char *mono_pcm_out_text[] = {
1304         "None", "AIF2ADCL", "AIF2ADCR",
1305 };
1306
1307 static const struct soc_enum mono_pcm_out_enum =
1308         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1309
1310 static const struct snd_kcontrol_new mono_pcm_out_mux =
1311         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1312
1313 static const char *aif2dac_src_text[] = {
1314         "AIF2", "AIF3",
1315 };
1316
1317 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1318 static const struct soc_enum aif2dacl_src_enum =
1319         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1320
1321 static const struct snd_kcontrol_new aif2dacl_src_mux =
1322         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1323
1324 static const struct soc_enum aif2dacr_src_enum =
1325         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1326
1327 static const struct snd_kcontrol_new aif2dacr_src_mux =
1328         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1329
1330 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1331 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1332         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1333 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1334         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1335
1336 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1337         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1338 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1339         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1340 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1341         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1342 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1343         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1344 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1345         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1346
1347 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1348                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1349                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1350 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1351                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1352                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1353 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1354                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1355 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1356                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1357
1358 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1359 };
1360
1361 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1362 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1363 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1364 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1365 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1366                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1367 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1368                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1369 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1370 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1371 };
1372
1373 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1374 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1375         dac_ev, SND_SOC_DAPM_PRE_PMU),
1376 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1377         dac_ev, SND_SOC_DAPM_PRE_PMU),
1378 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1379         dac_ev, SND_SOC_DAPM_PRE_PMU),
1380 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1381         dac_ev, SND_SOC_DAPM_PRE_PMU),
1382 };
1383
1384 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1385 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1386 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1387 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1388 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1389 };
1390
1391 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1392 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1393                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1394 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1395                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1396 };
1397
1398 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1399 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1400 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1401 };
1402
1403 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1404 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1405 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1406 SND_SOC_DAPM_INPUT("Clock"),
1407
1408 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1409                       SND_SOC_DAPM_PRE_PMU),
1410 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1411                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1412
1413 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1414                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1415
1416 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1417 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1418 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1419
1420 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1421                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1422 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1423                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1424 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1425                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1426                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1427 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1428                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1429                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1430
1431 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1432                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1433 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1434                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1435 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1436                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1437                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1438 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1439                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1440                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1441
1442 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1443                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1444 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1445                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1446
1447 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1448                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1449 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1450                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1451
1452 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1453                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1454 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1455                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1456
1457 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1458 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1459
1460 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1461                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1462 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1463                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1464
1465 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1466                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1467 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1468                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1469 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1470                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1471                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1472 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1473                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1474                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1475
1476 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1477 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1478 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1479 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT",  NULL, 0, SND_SOC_NOPM, 0, 0),
1480
1481 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1482 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1483 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1484
1485 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1486 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1487
1488 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1489
1490 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1491 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1492 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1493 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1494
1495 /* Power is done with the muxes since the ADC power also controls the
1496  * downsampling chain, the chip will automatically manage the analogue
1497  * specific portions.
1498  */
1499 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1500 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1501
1502 SND_SOC_DAPM_POST("Debug log", post_ev),
1503 };
1504
1505 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1506 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1507 };
1508
1509 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1510 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1511 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1512 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1513 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1514 };
1515
1516 static const struct snd_soc_dapm_route intercon[] = {
1517         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1518         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1519
1520         { "DSP1CLK", NULL, "CLK_SYS" },
1521         { "DSP2CLK", NULL, "CLK_SYS" },
1522         { "DSPINTCLK", NULL, "CLK_SYS" },
1523
1524         { "AIF1ADC1L", NULL, "AIF1CLK" },
1525         { "AIF1ADC1L", NULL, "DSP1CLK" },
1526         { "AIF1ADC1R", NULL, "AIF1CLK" },
1527         { "AIF1ADC1R", NULL, "DSP1CLK" },
1528         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1529
1530         { "AIF1DAC1L", NULL, "AIF1CLK" },
1531         { "AIF1DAC1L", NULL, "DSP1CLK" },
1532         { "AIF1DAC1R", NULL, "AIF1CLK" },
1533         { "AIF1DAC1R", NULL, "DSP1CLK" },
1534         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1535
1536         { "AIF1ADC2L", NULL, "AIF1CLK" },
1537         { "AIF1ADC2L", NULL, "DSP1CLK" },
1538         { "AIF1ADC2R", NULL, "AIF1CLK" },
1539         { "AIF1ADC2R", NULL, "DSP1CLK" },
1540         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1541
1542         { "AIF1DAC2L", NULL, "AIF1CLK" },
1543         { "AIF1DAC2L", NULL, "DSP1CLK" },
1544         { "AIF1DAC2R", NULL, "AIF1CLK" },
1545         { "AIF1DAC2R", NULL, "DSP1CLK" },
1546         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1547
1548         { "AIF2ADCL", NULL, "AIF2CLK" },
1549         { "AIF2ADCL", NULL, "DSP2CLK" },
1550         { "AIF2ADCR", NULL, "AIF2CLK" },
1551         { "AIF2ADCR", NULL, "DSP2CLK" },
1552         { "AIF2ADCR", NULL, "DSPINTCLK" },
1553
1554         { "AIF2DACL", NULL, "AIF2CLK" },
1555         { "AIF2DACL", NULL, "DSP2CLK" },
1556         { "AIF2DACR", NULL, "AIF2CLK" },
1557         { "AIF2DACR", NULL, "DSP2CLK" },
1558         { "AIF2DACR", NULL, "DSPINTCLK" },
1559
1560         { "DMIC1L", NULL, "DMIC1DAT" },
1561         { "DMIC1L", NULL, "CLK_SYS" },
1562         { "DMIC1R", NULL, "DMIC1DAT" },
1563         { "DMIC1R", NULL, "CLK_SYS" },
1564         { "DMIC2L", NULL, "DMIC2DAT" },
1565         { "DMIC2L", NULL, "CLK_SYS" },
1566         { "DMIC2R", NULL, "DMIC2DAT" },
1567         { "DMIC2R", NULL, "CLK_SYS" },
1568
1569         { "ADCL", NULL, "AIF1CLK" },
1570         { "ADCL", NULL, "DSP1CLK" },
1571         { "ADCL", NULL, "DSPINTCLK" },
1572
1573         { "ADCR", NULL, "AIF1CLK" },
1574         { "ADCR", NULL, "DSP1CLK" },
1575         { "ADCR", NULL, "DSPINTCLK" },
1576
1577         { "ADCL Mux", "ADC", "ADCL" },
1578         { "ADCL Mux", "DMIC", "DMIC1L" },
1579         { "ADCR Mux", "ADC", "ADCR" },
1580         { "ADCR Mux", "DMIC", "DMIC1R" },
1581
1582         { "DAC1L", NULL, "AIF1CLK" },
1583         { "DAC1L", NULL, "DSP1CLK" },
1584         { "DAC1L", NULL, "DSPINTCLK" },
1585
1586         { "DAC1R", NULL, "AIF1CLK" },
1587         { "DAC1R", NULL, "DSP1CLK" },
1588         { "DAC1R", NULL, "DSPINTCLK" },
1589
1590         { "DAC2L", NULL, "AIF2CLK" },
1591         { "DAC2L", NULL, "DSP2CLK" },
1592         { "DAC2L", NULL, "DSPINTCLK" },
1593
1594         { "DAC2R", NULL, "AIF2DACR" },
1595         { "DAC2R", NULL, "AIF2CLK" },
1596         { "DAC2R", NULL, "DSP2CLK" },
1597         { "DAC2R", NULL, "DSPINTCLK" },
1598
1599         { "TOCLK", NULL, "CLK_SYS" },
1600
1601         { "AIF1DACDAT", NULL, "AIF1 Playback" },
1602         { "AIF2DACDAT", NULL, "AIF2 Playback" },
1603         { "AIF3DACDAT", NULL, "AIF3 Playback" },
1604
1605         { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1606         { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1607         { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1608
1609         /* AIF1 outputs */
1610         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1611         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1612         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1613
1614         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1615         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1616         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1617
1618         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1619         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1620         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1621
1622         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1623         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1624         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1625
1626         /* Pin level routing for AIF3 */
1627         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1628         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1629         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1630         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1631
1632         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1633         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1634         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1635         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1636         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1637         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1638         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1639
1640         /* DAC1 inputs */
1641         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1642         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1643         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1644         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1645         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1646
1647         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1648         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1649         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1650         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1651         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1652
1653         /* DAC2/AIF2 outputs  */
1654         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1655         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1656         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1657         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1658         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1659         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1660
1661         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1662         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1663         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1664         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1665         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1666         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1667
1668         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1669         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1670         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1671         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1672
1673         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1674
1675         /* AIF3 output */
1676         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1677         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1678         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1679         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1680         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1681         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1682         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1683         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1684
1685         /* Sidetone */
1686         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1687         { "Left Sidetone", "DMIC2", "DMIC2L" },
1688         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1689         { "Right Sidetone", "DMIC2", "DMIC2R" },
1690
1691         /* Output stages */
1692         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1693         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1694
1695         { "SPKL", "DAC1 Switch", "DAC1L" },
1696         { "SPKL", "DAC2 Switch", "DAC2L" },
1697
1698         { "SPKR", "DAC1 Switch", "DAC1R" },
1699         { "SPKR", "DAC2 Switch", "DAC2R" },
1700
1701         { "Left Headphone Mux", "DAC", "DAC1L" },
1702         { "Right Headphone Mux", "DAC", "DAC1R" },
1703 };
1704
1705 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1706         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1707         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1708         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1709         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1710         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1711         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1712         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1713         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1714 };
1715
1716 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1717         { "DAC1L", NULL, "DAC1L Mixer" },
1718         { "DAC1R", NULL, "DAC1R Mixer" },
1719         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1720         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1721 };
1722
1723 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1724         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1725         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1726         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1727         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1728         { "MICBIAS1", NULL, "CLK_SYS" },
1729         { "MICBIAS1", NULL, "MICBIAS Supply" },
1730         { "MICBIAS2", NULL, "CLK_SYS" },
1731         { "MICBIAS2", NULL, "MICBIAS Supply" },
1732 };
1733
1734 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1735         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1736         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1737         { "MICBIAS1", NULL, "VMID" },
1738         { "MICBIAS2", NULL, "VMID" },
1739 };
1740
1741 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1742         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1743         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1744
1745         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1746         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1747         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1748         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1749
1750         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1751         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1752
1753         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1754 };
1755
1756 /* The size in bits of the FLL divide multiplied by 10
1757  * to allow rounding later */
1758 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1759
1760 struct fll_div {
1761         u16 outdiv;
1762         u16 n;
1763         u16 k;
1764         u16 clk_ref_div;
1765         u16 fll_fratio;
1766 };
1767
1768 static int wm8994_get_fll_config(struct fll_div *fll,
1769                                  int freq_in, int freq_out)
1770 {
1771         u64 Kpart;
1772         unsigned int K, Ndiv, Nmod;
1773
1774         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1775
1776         /* Scale the input frequency down to <= 13.5MHz */
1777         fll->clk_ref_div = 0;
1778         while (freq_in > 13500000) {
1779                 fll->clk_ref_div++;
1780                 freq_in /= 2;
1781
1782                 if (fll->clk_ref_div > 3)
1783                         return -EINVAL;
1784         }
1785         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1786
1787         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1788         fll->outdiv = 3;
1789         while (freq_out * (fll->outdiv + 1) < 90000000) {
1790                 fll->outdiv++;
1791                 if (fll->outdiv > 63)
1792                         return -EINVAL;
1793         }
1794         freq_out *= fll->outdiv + 1;
1795         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1796
1797         if (freq_in > 1000000) {
1798                 fll->fll_fratio = 0;
1799         } else if (freq_in > 256000) {
1800                 fll->fll_fratio = 1;
1801                 freq_in *= 2;
1802         } else if (freq_in > 128000) {
1803                 fll->fll_fratio = 2;
1804                 freq_in *= 4;
1805         } else if (freq_in > 64000) {
1806                 fll->fll_fratio = 3;
1807                 freq_in *= 8;
1808         } else {
1809                 fll->fll_fratio = 4;
1810                 freq_in *= 16;
1811         }
1812         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1813
1814         /* Now, calculate N.K */
1815         Ndiv = freq_out / freq_in;
1816
1817         fll->n = Ndiv;
1818         Nmod = freq_out % freq_in;
1819         pr_debug("Nmod=%d\n", Nmod);
1820
1821         /* Calculate fractional part - scale up so we can round. */
1822         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1823
1824         do_div(Kpart, freq_in);
1825
1826         K = Kpart & 0xFFFFFFFF;
1827
1828         if ((K % 10) >= 5)
1829                 K += 5;
1830
1831         /* Move down to proper range now rounding is done */
1832         fll->k = K / 10;
1833
1834         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1835
1836         return 0;
1837 }
1838
1839 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1840                           unsigned int freq_in, unsigned int freq_out)
1841 {
1842         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1843         struct wm8994 *control = wm8994->wm8994;
1844         int reg_offset, ret;
1845         struct fll_div fll;
1846         u16 reg, aif1, aif2;
1847         unsigned long timeout;
1848         bool was_enabled;
1849
1850         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1851                 & WM8994_AIF1CLK_ENA;
1852
1853         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1854                 & WM8994_AIF2CLK_ENA;
1855
1856         switch (id) {
1857         case WM8994_FLL1:
1858                 reg_offset = 0;
1859                 id = 0;
1860                 break;
1861         case WM8994_FLL2:
1862                 reg_offset = 0x20;
1863                 id = 1;
1864                 break;
1865         default:
1866                 return -EINVAL;
1867         }
1868
1869         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1870         was_enabled = reg & WM8994_FLL1_ENA;
1871
1872         switch (src) {
1873         case 0:
1874                 /* Allow no source specification when stopping */
1875                 if (freq_out)
1876                         return -EINVAL;
1877                 src = wm8994->fll[id].src;
1878                 break;
1879         case WM8994_FLL_SRC_MCLK1:
1880         case WM8994_FLL_SRC_MCLK2:
1881         case WM8994_FLL_SRC_LRCLK:
1882         case WM8994_FLL_SRC_BCLK:
1883                 break;
1884         default:
1885                 return -EINVAL;
1886         }
1887
1888         /* Are we changing anything? */
1889         if (wm8994->fll[id].src == src &&
1890             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1891                 return 0;
1892
1893         /* If we're stopping the FLL redo the old config - no
1894          * registers will actually be written but we avoid GCC flow
1895          * analysis bugs spewing warnings.
1896          */
1897         if (freq_out)
1898                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1899         else
1900                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1901                                             wm8994->fll[id].out);
1902         if (ret < 0)
1903                 return ret;
1904
1905         /* Gate the AIF clocks while we reclock */
1906         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1907                             WM8994_AIF1CLK_ENA, 0);
1908         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1909                             WM8994_AIF2CLK_ENA, 0);
1910
1911         /* We always need to disable the FLL while reconfiguring */
1912         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1913                             WM8994_FLL1_ENA, 0);
1914
1915         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1916                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1917         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1918                             WM8994_FLL1_OUTDIV_MASK |
1919                             WM8994_FLL1_FRATIO_MASK, reg);
1920
1921         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1922
1923         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1924                             WM8994_FLL1_N_MASK,
1925                                     fll.n << WM8994_FLL1_N_SHIFT);
1926
1927         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1928                             WM8994_FLL1_REFCLK_DIV_MASK |
1929                             WM8994_FLL1_REFCLK_SRC_MASK,
1930                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1931                             (src - 1));
1932
1933         /* Clear any pending completion from a previous failure */
1934         try_wait_for_completion(&wm8994->fll_locked[id]);
1935
1936         /* Enable (with fractional mode if required) */
1937         if (freq_out) {
1938                 /* Enable VMID if we need it */
1939                 if (!was_enabled) {
1940                         active_reference(codec);
1941
1942                         switch (control->type) {
1943                         case WM8994:
1944                                 vmid_reference(codec);
1945                                 break;
1946                         case WM8958:
1947                                 if (wm8994->revision < 1)
1948                                         vmid_reference(codec);
1949                                 break;
1950                         default:
1951                                 break;
1952                         }
1953                 }
1954
1955                 if (fll.k)
1956                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1957                 else
1958                         reg = WM8994_FLL1_ENA;
1959                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1960                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1961                                     reg);
1962
1963                 if (wm8994->fll_locked_irq) {
1964                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1965                                                               msecs_to_jiffies(10));
1966                         if (timeout == 0)
1967                                 dev_warn(codec->dev,
1968                                          "Timed out waiting for FLL lock\n");
1969                 } else {
1970                         msleep(5);
1971                 }
1972         } else {
1973                 if (was_enabled) {
1974                         switch (control->type) {
1975                         case WM8994:
1976                                 vmid_dereference(codec);
1977                                 break;
1978                         case WM8958:
1979                                 if (wm8994->revision < 1)
1980                                         vmid_dereference(codec);
1981                                 break;
1982                         default:
1983                                 break;
1984                         }
1985
1986                         active_dereference(codec);
1987                 }
1988         }
1989
1990         wm8994->fll[id].in = freq_in;
1991         wm8994->fll[id].out = freq_out;
1992         wm8994->fll[id].src = src;
1993
1994         /* Enable any gated AIF clocks */
1995         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1996                             WM8994_AIF1CLK_ENA, aif1);
1997         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1998                             WM8994_AIF2CLK_ENA, aif2);
1999
2000         configure_clock(codec);
2001
2002         return 0;
2003 }
2004
2005 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2006 {
2007         struct completion *completion = data;
2008
2009         complete(completion);
2010
2011         return IRQ_HANDLED;
2012 }
2013
2014 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2015
2016 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2017                           unsigned int freq_in, unsigned int freq_out)
2018 {
2019         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2020 }
2021
2022 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2023                 int clk_id, unsigned int freq, int dir)
2024 {
2025         struct snd_soc_codec *codec = dai->codec;
2026         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2027         int i;
2028
2029         switch (dai->id) {
2030         case 1:
2031         case 2:
2032                 break;
2033
2034         default:
2035                 /* AIF3 shares clocking with AIF1/2 */
2036                 return -EINVAL;
2037         }
2038
2039         switch (clk_id) {
2040         case WM8994_SYSCLK_MCLK1:
2041                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2042                 wm8994->mclk[0] = freq;
2043                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2044                         dai->id, freq);
2045                 break;
2046
2047         case WM8994_SYSCLK_MCLK2:
2048                 /* TODO: Set GPIO AF */
2049                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2050                 wm8994->mclk[1] = freq;
2051                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2052                         dai->id, freq);
2053                 break;
2054
2055         case WM8994_SYSCLK_FLL1:
2056                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2057                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2058                 break;
2059
2060         case WM8994_SYSCLK_FLL2:
2061                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2062                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2063                 break;
2064
2065         case WM8994_SYSCLK_OPCLK:
2066                 /* Special case - a division (times 10) is given and
2067                  * no effect on main clocking.
2068                  */
2069                 if (freq) {
2070                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2071                                 if (opclk_divs[i] == freq)
2072                                         break;
2073                         if (i == ARRAY_SIZE(opclk_divs))
2074                                 return -EINVAL;
2075                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2076                                             WM8994_OPCLK_DIV_MASK, i);
2077                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2078                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2079                 } else {
2080                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2081                                             WM8994_OPCLK_ENA, 0);
2082                 }
2083
2084         default:
2085                 return -EINVAL;
2086         }
2087
2088         configure_clock(codec);
2089
2090         return 0;
2091 }
2092
2093 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2094                                  enum snd_soc_bias_level level)
2095 {
2096         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2097         struct wm8994 *control = wm8994->wm8994;
2098
2099         wm_hubs_set_bias_level(codec, level);
2100
2101         switch (level) {
2102         case SND_SOC_BIAS_ON:
2103                 break;
2104
2105         case SND_SOC_BIAS_PREPARE:
2106                 /* MICBIAS into regulating mode */
2107                 switch (control->type) {
2108                 case WM8958:
2109                 case WM1811:
2110                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2111                                             WM8958_MICB1_MODE, 0);
2112                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2113                                             WM8958_MICB2_MODE, 0);
2114                         break;
2115                 default:
2116                         break;
2117                 }
2118
2119                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2120                         active_reference(codec);
2121                 break;
2122
2123         case SND_SOC_BIAS_STANDBY:
2124                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2125                         switch (control->type) {
2126                         case WM8994:
2127                                 if (wm8994->revision < 4) {
2128                                         /* Tweak DC servo and DSP
2129                                          * configuration for improved
2130                                          * performance. */
2131                                         snd_soc_write(codec, 0x102, 0x3);
2132                                         snd_soc_write(codec, 0x56, 0x3);
2133                                         snd_soc_write(codec, 0x817, 0);
2134                                         snd_soc_write(codec, 0x102, 0);
2135                                 }
2136                                 break;
2137
2138                         case WM8958:
2139                                 if (wm8994->revision == 0) {
2140                                         /* Optimise performance for rev A */
2141                                         snd_soc_write(codec, 0x102, 0x3);
2142                                         snd_soc_write(codec, 0xcb, 0x81);
2143                                         snd_soc_write(codec, 0x817, 0);
2144                                         snd_soc_write(codec, 0x102, 0);
2145
2146                                         snd_soc_update_bits(codec,
2147                                                             WM8958_CHARGE_PUMP_2,
2148                                                             WM8958_CP_DISCH,
2149                                                             WM8958_CP_DISCH);
2150                                 }
2151                                 break;
2152
2153                         case WM1811:
2154                                 if (wm8994->revision < 2) {
2155                                         snd_soc_write(codec, 0x102, 0x3);
2156                                         snd_soc_write(codec, 0x5d, 0x7e);
2157                                         snd_soc_write(codec, 0x5e, 0x0);
2158                                         snd_soc_write(codec, 0x102, 0x0);
2159                                 }
2160                                 break;
2161                         }
2162
2163                         /* Discharge LINEOUT1 & 2 */
2164                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2165                                             WM8994_LINEOUT1_DISCH |
2166                                             WM8994_LINEOUT2_DISCH,
2167                                             WM8994_LINEOUT1_DISCH |
2168                                             WM8994_LINEOUT2_DISCH);
2169                 }
2170
2171                 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2172                         active_dereference(codec);
2173
2174                 /* MICBIAS into bypass mode on newer devices */
2175                 switch (control->type) {
2176                 case WM8958:
2177                 case WM1811:
2178                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2179                                             WM8958_MICB1_MODE,
2180                                             WM8958_MICB1_MODE);
2181                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2182                                             WM8958_MICB2_MODE,
2183                                             WM8958_MICB2_MODE);
2184                         break;
2185                 default:
2186                         break;
2187                 }
2188                 break;
2189
2190         case SND_SOC_BIAS_OFF:
2191                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2192                         wm8994->cur_fw = NULL;
2193                 break;
2194         }
2195
2196         codec->dapm.bias_level = level;
2197
2198         return 0;
2199 }
2200
2201 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2202 {
2203         struct snd_soc_codec *codec = dai->codec;
2204         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2205         struct wm8994 *control = wm8994->wm8994;
2206         int ms_reg;
2207         int aif1_reg;
2208         int ms = 0;
2209         int aif1 = 0;
2210
2211         switch (dai->id) {
2212         case 1:
2213                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2214                 aif1_reg = WM8994_AIF1_CONTROL_1;
2215                 break;
2216         case 2:
2217                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2218                 aif1_reg = WM8994_AIF2_CONTROL_1;
2219                 break;
2220         default:
2221                 return -EINVAL;
2222         }
2223
2224         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2225         case SND_SOC_DAIFMT_CBS_CFS:
2226                 break;
2227         case SND_SOC_DAIFMT_CBM_CFM:
2228                 ms = WM8994_AIF1_MSTR;
2229                 break;
2230         default:
2231                 return -EINVAL;
2232         }
2233
2234         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2235         case SND_SOC_DAIFMT_DSP_B:
2236                 aif1 |= WM8994_AIF1_LRCLK_INV;
2237         case SND_SOC_DAIFMT_DSP_A:
2238                 aif1 |= 0x18;
2239                 break;
2240         case SND_SOC_DAIFMT_I2S:
2241                 aif1 |= 0x10;
2242                 break;
2243         case SND_SOC_DAIFMT_RIGHT_J:
2244                 break;
2245         case SND_SOC_DAIFMT_LEFT_J:
2246                 aif1 |= 0x8;
2247                 break;
2248         default:
2249                 return -EINVAL;
2250         }
2251
2252         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2253         case SND_SOC_DAIFMT_DSP_A:
2254         case SND_SOC_DAIFMT_DSP_B:
2255                 /* frame inversion not valid for DSP modes */
2256                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2257                 case SND_SOC_DAIFMT_NB_NF:
2258                         break;
2259                 case SND_SOC_DAIFMT_IB_NF:
2260                         aif1 |= WM8994_AIF1_BCLK_INV;
2261                         break;
2262                 default:
2263                         return -EINVAL;
2264                 }
2265                 break;
2266
2267         case SND_SOC_DAIFMT_I2S:
2268         case SND_SOC_DAIFMT_RIGHT_J:
2269         case SND_SOC_DAIFMT_LEFT_J:
2270                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2271                 case SND_SOC_DAIFMT_NB_NF:
2272                         break;
2273                 case SND_SOC_DAIFMT_IB_IF:
2274                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2275                         break;
2276                 case SND_SOC_DAIFMT_IB_NF:
2277                         aif1 |= WM8994_AIF1_BCLK_INV;
2278                         break;
2279                 case SND_SOC_DAIFMT_NB_IF:
2280                         aif1 |= WM8994_AIF1_LRCLK_INV;
2281                         break;
2282                 default:
2283                         return -EINVAL;
2284                 }
2285                 break;
2286         default:
2287                 return -EINVAL;
2288         }
2289
2290         /* The AIF2 format configuration needs to be mirrored to AIF3
2291          * on WM8958 if it's in use so just do it all the time. */
2292         switch (control->type) {
2293         case WM1811:
2294         case WM8958:
2295                 if (dai->id == 2)
2296                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2297                                             WM8994_AIF1_LRCLK_INV |
2298                                             WM8958_AIF3_FMT_MASK, aif1);
2299                 break;
2300
2301         default:
2302                 break;
2303         }
2304
2305         snd_soc_update_bits(codec, aif1_reg,
2306                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2307                             WM8994_AIF1_FMT_MASK,
2308                             aif1);
2309         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2310                             ms);
2311
2312         return 0;
2313 }
2314
2315 static struct {
2316         int val, rate;
2317 } srs[] = {
2318         { 0,   8000 },
2319         { 1,  11025 },
2320         { 2,  12000 },
2321         { 3,  16000 },
2322         { 4,  22050 },
2323         { 5,  24000 },
2324         { 6,  32000 },
2325         { 7,  44100 },
2326         { 8,  48000 },
2327         { 9,  88200 },
2328         { 10, 96000 },
2329 };
2330
2331 static int fs_ratios[] = {
2332         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2333 };
2334
2335 static int bclk_divs[] = {
2336         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2337         640, 880, 960, 1280, 1760, 1920
2338 };
2339
2340 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2341                             struct snd_pcm_hw_params *params,
2342                             struct snd_soc_dai *dai)
2343 {
2344         struct snd_soc_codec *codec = dai->codec;
2345         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2346         int aif1_reg;
2347         int aif2_reg;
2348         int bclk_reg;
2349         int lrclk_reg;
2350         int rate_reg;
2351         int aif1 = 0;
2352         int aif2 = 0;
2353         int bclk = 0;
2354         int lrclk = 0;
2355         int rate_val = 0;
2356         int id = dai->id - 1;
2357
2358         int i, cur_val, best_val, bclk_rate, best;
2359
2360         switch (dai->id) {
2361         case 1:
2362                 aif1_reg = WM8994_AIF1_CONTROL_1;
2363                 aif2_reg = WM8994_AIF1_CONTROL_2;
2364                 bclk_reg = WM8994_AIF1_BCLK;
2365                 rate_reg = WM8994_AIF1_RATE;
2366                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2367                     wm8994->lrclk_shared[0]) {
2368                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2369                 } else {
2370                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2371                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2372                 }
2373                 break;
2374         case 2:
2375                 aif1_reg = WM8994_AIF2_CONTROL_1;
2376                 aif2_reg = WM8994_AIF2_CONTROL_2;
2377                 bclk_reg = WM8994_AIF2_BCLK;
2378                 rate_reg = WM8994_AIF2_RATE;
2379                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2380                     wm8994->lrclk_shared[1]) {
2381                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2382                 } else {
2383                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2384                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2385                 }
2386                 break;
2387         default:
2388                 return -EINVAL;
2389         }
2390
2391         bclk_rate = params_rate(params) * 2;
2392         switch (params_format(params)) {
2393         case SNDRV_PCM_FORMAT_S16_LE:
2394                 bclk_rate *= 16;
2395                 break;
2396         case SNDRV_PCM_FORMAT_S20_3LE:
2397                 bclk_rate *= 20;
2398                 aif1 |= 0x20;
2399                 break;
2400         case SNDRV_PCM_FORMAT_S24_LE:
2401                 bclk_rate *= 24;
2402                 aif1 |= 0x40;
2403                 break;
2404         case SNDRV_PCM_FORMAT_S32_LE:
2405                 bclk_rate *= 32;
2406                 aif1 |= 0x60;
2407                 break;
2408         default:
2409                 return -EINVAL;
2410         }
2411
2412         /* Try to find an appropriate sample rate; look for an exact match. */
2413         for (i = 0; i < ARRAY_SIZE(srs); i++)
2414                 if (srs[i].rate == params_rate(params))
2415                         break;
2416         if (i == ARRAY_SIZE(srs))
2417                 return -EINVAL;
2418         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2419
2420         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2421         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2422                 dai->id, wm8994->aifclk[id], bclk_rate);
2423
2424         if (params_channels(params) == 1 &&
2425             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2426                 aif2 |= WM8994_AIF1_MONO;
2427
2428         if (wm8994->aifclk[id] == 0) {
2429                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2430                 return -EINVAL;
2431         }
2432
2433         /* AIFCLK/fs ratio; look for a close match in either direction */
2434         best = 0;
2435         best_val = abs((fs_ratios[0] * params_rate(params))
2436                        - wm8994->aifclk[id]);
2437         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2438                 cur_val = abs((fs_ratios[i] * params_rate(params))
2439                               - wm8994->aifclk[id]);
2440                 if (cur_val >= best_val)
2441                         continue;
2442                 best = i;
2443                 best_val = cur_val;
2444         }
2445         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2446                 dai->id, fs_ratios[best]);
2447         rate_val |= best;
2448
2449         /* We may not get quite the right frequency if using
2450          * approximate clocks so look for the closest match that is
2451          * higher than the target (we need to ensure that there enough
2452          * BCLKs to clock out the samples).
2453          */
2454         best = 0;
2455         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2456                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2457                 if (cur_val < 0) /* BCLK table is sorted */
2458                         break;
2459                 best = i;
2460         }
2461         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2462         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2463                 bclk_divs[best], bclk_rate);
2464         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2465
2466         lrclk = bclk_rate / params_rate(params);
2467         if (!lrclk) {
2468                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2469                         bclk_rate);
2470                 return -EINVAL;
2471         }
2472         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2473                 lrclk, bclk_rate / lrclk);
2474
2475         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2476         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2477         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2478         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2479                             lrclk);
2480         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2481                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2482
2483         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2484                 switch (dai->id) {
2485                 case 1:
2486                         wm8994->dac_rates[0] = params_rate(params);
2487                         wm8994_set_retune_mobile(codec, 0);
2488                         wm8994_set_retune_mobile(codec, 1);
2489                         break;
2490                 case 2:
2491                         wm8994->dac_rates[1] = params_rate(params);
2492                         wm8994_set_retune_mobile(codec, 2);
2493                         break;
2494                 }
2495         }
2496
2497         return 0;
2498 }
2499
2500 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2501                                  struct snd_pcm_hw_params *params,
2502                                  struct snd_soc_dai *dai)
2503 {
2504         struct snd_soc_codec *codec = dai->codec;
2505         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2506         struct wm8994 *control = wm8994->wm8994;
2507         int aif1_reg;
2508         int aif1 = 0;
2509
2510         switch (dai->id) {
2511         case 3:
2512                 switch (control->type) {
2513                 case WM1811:
2514                 case WM8958:
2515                         aif1_reg = WM8958_AIF3_CONTROL_1;
2516                         break;
2517                 default:
2518                         return 0;
2519                 }
2520         default:
2521                 return 0;
2522         }
2523
2524         switch (params_format(params)) {
2525         case SNDRV_PCM_FORMAT_S16_LE:
2526                 break;
2527         case SNDRV_PCM_FORMAT_S20_3LE:
2528                 aif1 |= 0x20;
2529                 break;
2530         case SNDRV_PCM_FORMAT_S24_LE:
2531                 aif1 |= 0x40;
2532                 break;
2533         case SNDRV_PCM_FORMAT_S32_LE:
2534                 aif1 |= 0x60;
2535                 break;
2536         default:
2537                 return -EINVAL;
2538         }
2539
2540         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2541 }
2542
2543 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2544                                 struct snd_soc_dai *dai)
2545 {
2546         struct snd_soc_codec *codec = dai->codec;
2547         int rate_reg = 0;
2548
2549         switch (dai->id) {
2550         case 1:
2551                 rate_reg = WM8994_AIF1_RATE;
2552                 break;
2553         case 2:
2554                 rate_reg = WM8994_AIF2_RATE;
2555                 break;
2556         default:
2557                 break;
2558         }
2559
2560         /* If the DAI is idle then configure the divider tree for the
2561          * lowest output rate to save a little power if the clock is
2562          * still active (eg, because it is system clock).
2563          */
2564         if (rate_reg && !dai->playback_active && !dai->capture_active)
2565                 snd_soc_update_bits(codec, rate_reg,
2566                                     WM8994_AIF1_SR_MASK |
2567                                     WM8994_AIF1CLK_RATE_MASK, 0x9);
2568 }
2569
2570 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2571 {
2572         struct snd_soc_codec *codec = codec_dai->codec;
2573         int mute_reg;
2574         int reg;
2575
2576         switch (codec_dai->id) {
2577         case 1:
2578                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2579                 break;
2580         case 2:
2581                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2582                 break;
2583         default:
2584                 return -EINVAL;
2585         }
2586
2587         if (mute)
2588                 reg = WM8994_AIF1DAC1_MUTE;
2589         else
2590                 reg = 0;
2591
2592         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2593
2594         return 0;
2595 }
2596
2597 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2598 {
2599         struct snd_soc_codec *codec = codec_dai->codec;
2600         int reg, val, mask;
2601
2602         switch (codec_dai->id) {
2603         case 1:
2604                 reg = WM8994_AIF1_MASTER_SLAVE;
2605                 mask = WM8994_AIF1_TRI;
2606                 break;
2607         case 2:
2608                 reg = WM8994_AIF2_MASTER_SLAVE;
2609                 mask = WM8994_AIF2_TRI;
2610                 break;
2611         case 3:
2612                 reg = WM8994_POWER_MANAGEMENT_6;
2613                 mask = WM8994_AIF3_TRI;
2614                 break;
2615         default:
2616                 return -EINVAL;
2617         }
2618
2619         if (tristate)
2620                 val = mask;
2621         else
2622                 val = 0;
2623
2624         return snd_soc_update_bits(codec, reg, mask, val);
2625 }
2626
2627 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2628 {
2629         struct snd_soc_codec *codec = dai->codec;
2630
2631         /* Disable the pulls on the AIF if we're using it to save power. */
2632         snd_soc_update_bits(codec, WM8994_GPIO_3,
2633                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2634         snd_soc_update_bits(codec, WM8994_GPIO_4,
2635                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2636         snd_soc_update_bits(codec, WM8994_GPIO_5,
2637                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2638
2639         return 0;
2640 }
2641
2642 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2643
2644 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2645                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2646
2647 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2648         .set_sysclk     = wm8994_set_dai_sysclk,
2649         .set_fmt        = wm8994_set_dai_fmt,
2650         .hw_params      = wm8994_hw_params,
2651         .shutdown       = wm8994_aif_shutdown,
2652         .digital_mute   = wm8994_aif_mute,
2653         .set_pll        = wm8994_set_fll,
2654         .set_tristate   = wm8994_set_tristate,
2655 };
2656
2657 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2658         .set_sysclk     = wm8994_set_dai_sysclk,
2659         .set_fmt        = wm8994_set_dai_fmt,
2660         .hw_params      = wm8994_hw_params,
2661         .shutdown       = wm8994_aif_shutdown,
2662         .digital_mute   = wm8994_aif_mute,
2663         .set_pll        = wm8994_set_fll,
2664         .set_tristate   = wm8994_set_tristate,
2665 };
2666
2667 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2668         .hw_params      = wm8994_aif3_hw_params,
2669         .set_tristate   = wm8994_set_tristate,
2670 };
2671
2672 static struct snd_soc_dai_driver wm8994_dai[] = {
2673         {
2674                 .name = "wm8994-aif1",
2675                 .id = 1,
2676                 .playback = {
2677                         .stream_name = "AIF1 Playback",
2678                         .channels_min = 1,
2679                         .channels_max = 2,
2680                         .rates = WM8994_RATES,
2681                         .formats = WM8994_FORMATS,
2682                         .sig_bits = 24,
2683                 },
2684                 .capture = {
2685                         .stream_name = "AIF1 Capture",
2686                         .channels_min = 1,
2687                         .channels_max = 2,
2688                         .rates = WM8994_RATES,
2689                         .formats = WM8994_FORMATS,
2690                         .sig_bits = 24,
2691                  },
2692                 .ops = &wm8994_aif1_dai_ops,
2693         },
2694         {
2695                 .name = "wm8994-aif2",
2696                 .id = 2,
2697                 .playback = {
2698                         .stream_name = "AIF2 Playback",
2699                         .channels_min = 1,
2700                         .channels_max = 2,
2701                         .rates = WM8994_RATES,
2702                         .formats = WM8994_FORMATS,
2703                         .sig_bits = 24,
2704                 },
2705                 .capture = {
2706                         .stream_name = "AIF2 Capture",
2707                         .channels_min = 1,
2708                         .channels_max = 2,
2709                         .rates = WM8994_RATES,
2710                         .formats = WM8994_FORMATS,
2711                         .sig_bits = 24,
2712                 },
2713                 .probe = wm8994_aif2_probe,
2714                 .ops = &wm8994_aif2_dai_ops,
2715         },
2716         {
2717                 .name = "wm8994-aif3",
2718                 .id = 3,
2719                 .playback = {
2720                         .stream_name = "AIF3 Playback",
2721                         .channels_min = 1,
2722                         .channels_max = 2,
2723                         .rates = WM8994_RATES,
2724                         .formats = WM8994_FORMATS,
2725                         .sig_bits = 24,
2726                 },
2727                 .capture = {
2728                         .stream_name = "AIF3 Capture",
2729                         .channels_min = 1,
2730                         .channels_max = 2,
2731                         .rates = WM8994_RATES,
2732                         .formats = WM8994_FORMATS,
2733                         .sig_bits = 24,
2734                  },
2735                 .ops = &wm8994_aif3_dai_ops,
2736         }
2737 };
2738
2739 #ifdef CONFIG_PM
2740 static int wm8994_suspend(struct snd_soc_codec *codec)
2741 {
2742         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2743         struct wm8994 *control = wm8994->wm8994;
2744         int i, ret;
2745
2746         switch (control->type) {
2747         case WM8994:
2748                 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2749                 break;
2750         case WM1811:
2751                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2752                                     WM1811_JACKDET_MODE_MASK, 0);
2753                 /* Fall through */
2754         case WM8958:
2755                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2756                                     WM8958_MICD_ENA, 0);
2757                 break;
2758         }
2759
2760         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2761                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2762                        sizeof(struct wm8994_fll_config));
2763                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2764                 if (ret < 0)
2765                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2766                                  i + 1, ret);
2767         }
2768
2769         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2770
2771         return 0;
2772 }
2773
2774 static int wm8994_resume(struct snd_soc_codec *codec)
2775 {
2776         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2777         struct wm8994 *control = wm8994->wm8994;
2778         int i, ret;
2779         unsigned int val, mask;
2780
2781         if (wm8994->revision < 4) {
2782                 /* force a HW read */
2783                 ret = regmap_read(control->regmap,
2784                                   WM8994_POWER_MANAGEMENT_5, &val);
2785
2786                 /* modify the cache only */
2787                 codec->cache_only = 1;
2788                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2789                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2790                 val &= mask;
2791                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2792                                     mask, val);
2793                 codec->cache_only = 0;
2794         }
2795
2796         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2797                 if (!wm8994->fll_suspend[i].out)
2798                         continue;
2799
2800                 ret = _wm8994_set_fll(codec, i + 1,
2801                                      wm8994->fll_suspend[i].src,
2802                                      wm8994->fll_suspend[i].in,
2803                                      wm8994->fll_suspend[i].out);
2804                 if (ret < 0)
2805                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2806                                  i + 1, ret);
2807         }
2808
2809         switch (control->type) {
2810         case WM8994:
2811                 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2812                         snd_soc_update_bits(codec, WM8994_MICBIAS,
2813                                             WM8994_MICD_ENA, WM8994_MICD_ENA);
2814                 break;
2815         case WM1811:
2816                 if (wm8994->jackdet && wm8994->jack_cb) {
2817                         /* Restart from idle */
2818                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2819                                             WM1811_JACKDET_MODE_MASK,
2820                                             WM1811_JACKDET_MODE_JACK);
2821                         break;
2822                 }
2823         case WM8958:
2824                 if (wm8994->jack_cb)
2825                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2826                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
2827                 break;
2828         }
2829
2830         return 0;
2831 }
2832 #else
2833 #define wm8994_suspend NULL
2834 #define wm8994_resume NULL
2835 #endif
2836
2837 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2838 {
2839         struct snd_soc_codec *codec = wm8994->codec;
2840         struct wm8994_pdata *pdata = wm8994->pdata;
2841         struct snd_kcontrol_new controls[] = {
2842                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2843                              wm8994->retune_mobile_enum,
2844                              wm8994_get_retune_mobile_enum,
2845                              wm8994_put_retune_mobile_enum),
2846                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2847                              wm8994->retune_mobile_enum,
2848                              wm8994_get_retune_mobile_enum,
2849                              wm8994_put_retune_mobile_enum),
2850                 SOC_ENUM_EXT("AIF2 EQ Mode",
2851                              wm8994->retune_mobile_enum,
2852                              wm8994_get_retune_mobile_enum,
2853                              wm8994_put_retune_mobile_enum),
2854         };
2855         int ret, i, j;
2856         const char **t;
2857
2858         /* We need an array of texts for the enum API but the number
2859          * of texts is likely to be less than the number of
2860          * configurations due to the sample rate dependency of the
2861          * configurations. */
2862         wm8994->num_retune_mobile_texts = 0;
2863         wm8994->retune_mobile_texts = NULL;
2864         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2865                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2866                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2867                                    wm8994->retune_mobile_texts[j]) == 0)
2868                                 break;
2869                 }
2870
2871                 if (j != wm8994->num_retune_mobile_texts)
2872                         continue;
2873
2874                 /* Expand the array... */
2875                 t = krealloc(wm8994->retune_mobile_texts,
2876                              sizeof(char *) *
2877                              (wm8994->num_retune_mobile_texts + 1),
2878                              GFP_KERNEL);
2879                 if (t == NULL)
2880                         continue;
2881
2882                 /* ...store the new entry... */
2883                 t[wm8994->num_retune_mobile_texts] =
2884                         pdata->retune_mobile_cfgs[i].name;
2885
2886                 /* ...and remember the new version. */
2887                 wm8994->num_retune_mobile_texts++;
2888                 wm8994->retune_mobile_texts = t;
2889         }
2890
2891         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2892                 wm8994->num_retune_mobile_texts);
2893
2894         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2895         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2896
2897         ret = snd_soc_add_codec_controls(wm8994->codec, controls,
2898                                    ARRAY_SIZE(controls));
2899         if (ret != 0)
2900                 dev_err(wm8994->codec->dev,
2901                         "Failed to add ReTune Mobile controls: %d\n", ret);
2902 }
2903
2904 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2905 {
2906         struct snd_soc_codec *codec = wm8994->codec;
2907         struct wm8994_pdata *pdata = wm8994->pdata;
2908         int ret, i;
2909
2910         if (!pdata)
2911                 return;
2912
2913         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2914                                       pdata->lineout2_diff,
2915                                       pdata->lineout1fb,
2916                                       pdata->lineout2fb,
2917                                       pdata->jd_scthr,
2918                                       pdata->jd_thr,
2919                                       pdata->micbias1_lvl,
2920                                       pdata->micbias2_lvl);
2921
2922         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2923
2924         if (pdata->num_drc_cfgs) {
2925                 struct snd_kcontrol_new controls[] = {
2926                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2927                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2928                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2929                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2930                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2931                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2932                 };
2933
2934                 /* We need an array of texts for the enum API */
2935                 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
2936                             sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
2937                 if (!wm8994->drc_texts) {
2938                         dev_err(wm8994->codec->dev,
2939                                 "Failed to allocate %d DRC config texts\n",
2940                                 pdata->num_drc_cfgs);
2941                         return;
2942                 }
2943
2944                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2945                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2946
2947                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2948                 wm8994->drc_enum.texts = wm8994->drc_texts;
2949
2950                 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
2951                                            ARRAY_SIZE(controls));
2952                 if (ret != 0)
2953                         dev_err(wm8994->codec->dev,
2954                                 "Failed to add DRC mode controls: %d\n", ret);
2955
2956                 for (i = 0; i < WM8994_NUM_DRC; i++)
2957                         wm8994_set_drc(codec, i);
2958         }
2959
2960         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2961                 pdata->num_retune_mobile_cfgs);
2962
2963         if (pdata->num_retune_mobile_cfgs)
2964                 wm8994_handle_retune_mobile_pdata(wm8994);
2965         else
2966                 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
2967                                      ARRAY_SIZE(wm8994_eq_controls));
2968
2969         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2970                 if (pdata->micbias[i]) {
2971                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
2972                                 pdata->micbias[i] & 0xffff);
2973                 }
2974         }
2975 }
2976
2977 /**
2978  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2979  *
2980  * @codec:   WM8994 codec
2981  * @jack:    jack to report detection events on
2982  * @micbias: microphone bias to detect on
2983  *
2984  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2985  * being used to bring out signals to the processor then only platform
2986  * data configuration is needed for WM8994 and processor GPIOs should
2987  * be configured using snd_soc_jack_add_gpios() instead.
2988  *
2989  * Configuration of detection levels is available via the micbias1_lvl
2990  * and micbias2_lvl platform data members.
2991  */
2992 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2993                       int micbias)
2994 {
2995         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2996         struct wm8994_micdet *micdet;
2997         struct wm8994 *control = wm8994->wm8994;
2998         int reg, ret;
2999
3000         if (control->type != WM8994) {
3001                 dev_warn(codec->dev, "Not a WM8994\n");
3002                 return -EINVAL;
3003         }
3004
3005         switch (micbias) {
3006         case 1:
3007                 micdet = &wm8994->micdet[0];
3008                 if (jack)
3009                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3010                                                             "MICBIAS1");
3011                 else
3012                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3013                                                        "MICBIAS1");
3014                 break;
3015         case 2:
3016                 micdet = &wm8994->micdet[1];
3017                 if (jack)
3018                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3019                                                             "MICBIAS1");
3020                 else
3021                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3022                                                        "MICBIAS1");
3023                 break;
3024         default:
3025                 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3026                 return -EINVAL;
3027         }
3028
3029         if (ret != 0)
3030                 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3031                          micbias, ret);
3032
3033         dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3034                 micbias, jack);
3035
3036         /* Store the configuration */
3037         micdet->jack = jack;
3038         micdet->detecting = true;
3039
3040         /* If either of the jacks is set up then enable detection */
3041         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3042                 reg = WM8994_MICD_ENA;
3043         else
3044                 reg = 0;
3045
3046         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3047
3048         snd_soc_dapm_sync(&codec->dapm);
3049
3050         return 0;
3051 }
3052 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3053
3054 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3055 {
3056         struct wm8994_priv *priv = data;
3057         struct snd_soc_codec *codec = priv->codec;
3058         int reg;
3059         int report;
3060
3061 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3062         trace_snd_soc_jack_irq(dev_name(codec->dev));
3063 #endif
3064
3065         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3066         if (reg < 0) {
3067                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3068                         reg);
3069                 return IRQ_HANDLED;
3070         }
3071
3072         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3073
3074         report = 0;
3075         if (reg & WM8994_MIC1_DET_STS) {
3076                 if (priv->micdet[0].detecting)
3077                         report = SND_JACK_HEADSET;
3078         }
3079         if (reg & WM8994_MIC1_SHRT_STS) {
3080                 if (priv->micdet[0].detecting)
3081                         report = SND_JACK_HEADPHONE;
3082                 else
3083                         report |= SND_JACK_BTN_0;
3084         }
3085         if (report)
3086                 priv->micdet[0].detecting = false;
3087         else
3088                 priv->micdet[0].detecting = true;
3089
3090         snd_soc_jack_report(priv->micdet[0].jack, report,
3091                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3092
3093         report = 0;
3094         if (reg & WM8994_MIC2_DET_STS) {
3095                 if (priv->micdet[1].detecting)
3096                         report = SND_JACK_HEADSET;
3097         }
3098         if (reg & WM8994_MIC2_SHRT_STS) {
3099                 if (priv->micdet[1].detecting)
3100                         report = SND_JACK_HEADPHONE;
3101                 else
3102                         report |= SND_JACK_BTN_0;
3103         }
3104         if (report)
3105                 priv->micdet[1].detecting = false;
3106         else
3107                 priv->micdet[1].detecting = true;
3108
3109         snd_soc_jack_report(priv->micdet[1].jack, report,
3110                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3111
3112         return IRQ_HANDLED;
3113 }
3114
3115 /* Default microphone detection handler for WM8958 - the user can
3116  * override this if they wish.
3117  */
3118 static void wm8958_default_micdet(u16 status, void *data)
3119 {
3120         struct snd_soc_codec *codec = data;
3121         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3122         int report;
3123
3124         dev_dbg(codec->dev, "MICDET %x\n", status);
3125
3126         /* Either nothing present or just starting detection */
3127         if (!(status & WM8958_MICD_STS)) {
3128                 if (!wm8994->jackdet) {
3129                         /* If nothing present then clear our statuses */
3130                         dev_dbg(codec->dev, "Detected open circuit\n");
3131                         wm8994->jack_mic = false;
3132                         wm8994->mic_detecting = true;
3133
3134                         wm8958_micd_set_rate(codec);
3135
3136                         snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3137                                             wm8994->btn_mask |
3138                                              SND_JACK_HEADSET);
3139                 }
3140                 return;
3141         }
3142
3143         /* If the measurement is showing a high impedence we've got a
3144          * microphone.
3145          */
3146         if (wm8994->mic_detecting && (status & 0x600)) {
3147                 dev_dbg(codec->dev, "Detected microphone\n");
3148
3149                 wm8994->mic_detecting = false;
3150                 wm8994->jack_mic = true;
3151
3152                 wm8958_micd_set_rate(codec);
3153
3154                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3155                                     SND_JACK_HEADSET);
3156         }
3157
3158
3159         if (wm8994->mic_detecting && status & 0xfc) {
3160                 dev_dbg(codec->dev, "Detected headphone\n");
3161                 wm8994->mic_detecting = false;
3162
3163                 wm8958_micd_set_rate(codec);
3164
3165                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3166                                     SND_JACK_HEADSET);
3167
3168                 /* If we have jackdet that will detect removal */
3169                 if (wm8994->jackdet) {
3170                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3171                                             WM8958_MICD_ENA, 0);
3172
3173                         if (wm8994->pdata->jd_ext_cap) {
3174                                 mutex_lock(&codec->mutex);
3175                                 snd_soc_dapm_disable_pin(&codec->dapm,
3176                                                          "MICBIAS2");
3177                                 snd_soc_dapm_sync(&codec->dapm);
3178                                 mutex_unlock(&codec->mutex);
3179                         }
3180
3181                         wm1811_jackdet_set_mode(codec,
3182                                                 WM1811_JACKDET_MODE_JACK);
3183                 }
3184         }
3185
3186         /* Report short circuit as a button */
3187         if (wm8994->jack_mic) {
3188                 report = 0;
3189                 if (status & 0x4)
3190                         report |= SND_JACK_BTN_0;
3191
3192                 if (status & 0x8)
3193                         report |= SND_JACK_BTN_1;
3194
3195                 if (status & 0x10)
3196                         report |= SND_JACK_BTN_2;
3197
3198                 if (status & 0x20)
3199                         report |= SND_JACK_BTN_3;
3200
3201                 if (status & 0x40)
3202                         report |= SND_JACK_BTN_4;
3203
3204                 if (status & 0x80)
3205                         report |= SND_JACK_BTN_5;
3206
3207                 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3208                                     wm8994->btn_mask);
3209         }
3210 }
3211
3212 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3213 {
3214         struct wm8994_priv *wm8994 = data;
3215         struct snd_soc_codec *codec = wm8994->codec;
3216         int reg;
3217
3218         mutex_lock(&wm8994->accdet_lock);
3219
3220         reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3221         if (reg < 0) {
3222                 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3223                 mutex_unlock(&wm8994->accdet_lock);
3224                 return IRQ_NONE;
3225         }
3226
3227         dev_dbg(codec->dev, "JACKDET %x\n", reg);
3228
3229         if (reg & WM1811_JACKDET_LVL) {
3230                 dev_dbg(codec->dev, "Jack detected\n");
3231
3232                 snd_soc_jack_report(wm8994->micdet[0].jack,
3233                                     SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3234
3235                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3236                                     WM8958_MICB2_DISCH, 0);
3237
3238                 /*
3239                  * Start off measument of microphone impedence to find
3240                  * out what's actually there.
3241                  */
3242                 wm8994->mic_detecting = true;
3243                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3244
3245                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3246                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3247
3248                 /* If required for an external cap force MICBIAS on */
3249                 if (wm8994->pdata->jd_ext_cap) {
3250                         mutex_lock(&codec->mutex);
3251                         snd_soc_dapm_force_enable_pin(&codec->dapm,
3252                                                       "MICBIAS2");
3253                         snd_soc_dapm_sync(&codec->dapm);
3254                         mutex_unlock(&codec->mutex);
3255                 }
3256         } else {
3257                 dev_dbg(codec->dev, "Jack not detected\n");
3258
3259                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3260                                     WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3261
3262                 if (wm8994->pdata->jd_ext_cap) {
3263                         mutex_lock(&codec->mutex);
3264                         snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3265                         snd_soc_dapm_sync(&codec->dapm);
3266                         mutex_unlock(&codec->mutex);
3267                 }
3268
3269                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3270                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3271                                     wm8994->btn_mask);
3272
3273                 wm8994->mic_detecting = false;
3274                 wm8994->jack_mic = false;
3275                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3276                                     WM8958_MICD_ENA, 0);
3277                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3278         }
3279
3280         mutex_unlock(&wm8994->accdet_lock);
3281
3282         return IRQ_HANDLED;
3283 }
3284
3285 /**
3286  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3287  *
3288  * @codec:   WM8958 codec
3289  * @jack:    jack to report detection events on
3290  *
3291  * Enable microphone detection functionality for the WM8958.  By
3292  * default simple detection which supports the detection of up to 6
3293  * buttons plus video and microphone functionality is supported.
3294  *
3295  * The WM8958 has an advanced jack detection facility which is able to
3296  * support complex accessory detection, especially when used in
3297  * conjunction with external circuitry.  In order to provide maximum
3298  * flexiblity a callback is provided which allows a completely custom
3299  * detection algorithm.
3300  */
3301 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3302                       wm8958_micdet_cb cb, void *cb_data)
3303 {
3304         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3305         struct wm8994 *control = wm8994->wm8994;
3306         u16 micd_lvl_sel;
3307
3308         switch (control->type) {
3309         case WM1811:
3310         case WM8958:
3311                 break;
3312         default:
3313                 return -EINVAL;
3314         }
3315
3316         if (jack) {
3317                 if (!cb) {
3318                         dev_dbg(codec->dev, "Using default micdet callback\n");
3319                         cb = wm8958_default_micdet;
3320                         cb_data = codec;
3321                 }
3322
3323                 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3324
3325                 wm8994->micdet[0].jack = jack;
3326                 wm8994->jack_cb = cb;
3327                 wm8994->jack_cb_data = cb_data;
3328
3329                 wm8994->mic_detecting = true;
3330                 wm8994->jack_mic = false;
3331
3332                 wm8958_micd_set_rate(codec);
3333
3334                 /* Detect microphones and short circuits by default */
3335                 if (wm8994->pdata->micd_lvl_sel)
3336                         micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3337                 else
3338                         micd_lvl_sel = 0x41;
3339
3340                 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3341                         SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3342                         SND_JACK_BTN_4 | SND_JACK_BTN_5;
3343
3344                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3345                                     WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3346
3347                 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3348
3349                 /*
3350                  * If we can use jack detection start off with that,
3351                  * otherwise jump straight to microphone detection.
3352                  */
3353                 if (wm8994->jackdet) {
3354                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
3355                                             WM8958_MICB2_DISCH,
3356                                             WM8958_MICB2_DISCH);
3357                         snd_soc_update_bits(codec, WM8994_LDO_1,
3358                                             WM8994_LDO1_DISCH, 0);
3359                         wm1811_jackdet_set_mode(codec,
3360                                                 WM1811_JACKDET_MODE_JACK);
3361                 } else {
3362                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3363                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
3364                 }
3365
3366         } else {
3367                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3368                                     WM8958_MICD_ENA, 0);
3369                 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3370         }
3371
3372         return 0;
3373 }
3374 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3375
3376 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3377 {
3378         struct wm8994_priv *wm8994 = data;
3379         struct snd_soc_codec *codec = wm8994->codec;
3380         int reg, count;
3381
3382         mutex_lock(&wm8994->accdet_lock);
3383
3384         /*
3385          * Jack detection may have detected a removal simulataneously
3386          * with an update of the MICDET status; if so it will have
3387          * stopped detection and we can ignore this interrupt.
3388          */
3389         if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) {
3390                 mutex_unlock(&wm8994->accdet_lock);
3391                 return IRQ_HANDLED;
3392         }
3393
3394         /* We may occasionally read a detection without an impedence
3395          * range being provided - if that happens loop again.
3396          */
3397         count = 10;
3398         do {
3399                 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3400                 if (reg < 0) {
3401                         mutex_unlock(&wm8994->accdet_lock);
3402                         dev_err(codec->dev,
3403                                 "Failed to read mic detect status: %d\n",
3404                                 reg);
3405                         return IRQ_NONE;
3406                 }
3407
3408                 if (!(reg & WM8958_MICD_VALID)) {
3409                         dev_dbg(codec->dev, "Mic detect data not valid\n");
3410                         goto out;
3411                 }
3412
3413                 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3414                         break;
3415
3416                 msleep(1);
3417         } while (count--);
3418
3419         if (count == 0)
3420                 dev_warn(codec->dev, "No impedence range reported for jack\n");
3421
3422 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3423         trace_snd_soc_jack_irq(dev_name(codec->dev));
3424 #endif
3425
3426         if (wm8994->jack_cb)
3427                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3428         else
3429                 dev_warn(codec->dev, "Accessory detection with no callback\n");
3430
3431 out:
3432         mutex_unlock(&wm8994->accdet_lock);
3433
3434         return IRQ_HANDLED;
3435 }
3436
3437 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3438 {
3439         struct snd_soc_codec *codec = data;
3440
3441         dev_err(codec->dev, "FIFO error\n");
3442
3443         return IRQ_HANDLED;
3444 }
3445
3446 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3447 {
3448         struct snd_soc_codec *codec = data;
3449
3450         dev_err(codec->dev, "Thermal warning\n");
3451
3452         return IRQ_HANDLED;
3453 }
3454
3455 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3456 {
3457         struct snd_soc_codec *codec = data;
3458
3459         dev_crit(codec->dev, "Thermal shutdown\n");
3460
3461         return IRQ_HANDLED;
3462 }
3463
3464 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3465 {
3466         struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3467         struct wm8994_priv *wm8994;
3468         struct snd_soc_dapm_context *dapm = &codec->dapm;
3469         unsigned int reg;
3470         int ret, i;
3471
3472         codec->control_data = control->regmap;
3473
3474         wm8994 = devm_kzalloc(codec->dev, sizeof(struct wm8994_priv),
3475                               GFP_KERNEL);
3476         if (wm8994 == NULL)
3477                 return -ENOMEM;
3478         snd_soc_codec_set_drvdata(codec, wm8994);
3479
3480         snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3481
3482         wm8994->wm8994 = dev_get_drvdata(codec->dev->parent);
3483         wm8994->pdata = dev_get_platdata(codec->dev->parent);
3484         wm8994->codec = codec;
3485
3486         mutex_init(&wm8994->accdet_lock);
3487
3488         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3489                 init_completion(&wm8994->fll_locked[i]);
3490
3491         if (wm8994->pdata && wm8994->pdata->micdet_irq)
3492                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3493         else if (wm8994->pdata && wm8994->pdata->irq_base)
3494                 wm8994->micdet_irq = wm8994->pdata->irq_base +
3495                                      WM8994_IRQ_MIC1_DET;
3496
3497         pm_runtime_enable(codec->dev);
3498         pm_runtime_idle(codec->dev);
3499
3500         /* By default use idle_bias_off, will override for WM8994 */
3501         codec->dapm.idle_bias_off = 1;
3502
3503         /* Set revision-specific configuration */
3504         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3505         switch (control->type) {
3506         case WM8994:
3507                 /* Single ended line outputs should have VMID on. */
3508                 if (!wm8994->pdata->lineout1_diff ||
3509                     !wm8994->pdata->lineout2_diff)
3510                         codec->dapm.idle_bias_off = 0;
3511
3512                 switch (wm8994->revision) {
3513                 case 2:
3514                 case 3:
3515                         wm8994->hubs.dcs_codes_l = -5;
3516                         wm8994->hubs.dcs_codes_r = -5;
3517                         wm8994->hubs.hp_startup_mode = 1;
3518                         wm8994->hubs.dcs_readback_mode = 1;
3519                         wm8994->hubs.series_startup = 1;
3520                         break;
3521                 default:
3522                         wm8994->hubs.dcs_readback_mode = 2;
3523                         break;
3524                 }
3525                 break;
3526
3527         case WM8958:
3528                 wm8994->hubs.dcs_readback_mode = 1;
3529                 wm8994->hubs.hp_startup_mode = 1;
3530                 break;
3531
3532         case WM1811:
3533                 wm8994->hubs.dcs_readback_mode = 2;
3534                 wm8994->hubs.no_series_update = 1;
3535                 wm8994->hubs.hp_startup_mode = 1;
3536
3537                 switch (wm8994->revision) {
3538                 case 0:
3539                 case 1:
3540                 case 2:
3541                 case 3:
3542                         wm8994->hubs.dcs_codes_l = -9;
3543                         wm8994->hubs.dcs_codes_r = -5;
3544                         break;
3545                 default:
3546                         break;
3547                 }
3548
3549                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3550                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3551                 break;
3552
3553         default:
3554                 break;
3555         }
3556
3557         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3558                            wm8994_fifo_error, "FIFO error", codec);
3559         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3560                            wm8994_temp_warn, "Thermal warning", codec);
3561         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3562                            wm8994_temp_shut, "Thermal shutdown", codec);
3563
3564         ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3565                                  wm_hubs_dcs_done, "DC servo done",
3566                                  &wm8994->hubs);
3567         if (ret == 0)
3568                 wm8994->hubs.dcs_done_irq = true;
3569
3570         switch (control->type) {
3571         case WM8994:
3572                 if (wm8994->micdet_irq) {
3573                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3574                                                    wm8994_mic_irq,
3575                                                    IRQF_TRIGGER_RISING,
3576                                                    "Mic1 detect",
3577                                                    wm8994);
3578                         if (ret != 0)
3579                                 dev_warn(codec->dev,
3580                                          "Failed to request Mic1 detect IRQ: %d\n",
3581                                          ret);
3582                 }
3583
3584                 ret = wm8994_request_irq(wm8994->wm8994,
3585                                          WM8994_IRQ_MIC1_SHRT,
3586                                          wm8994_mic_irq, "Mic 1 short",
3587                                          wm8994);
3588                 if (ret != 0)
3589                         dev_warn(codec->dev,
3590                                  "Failed to request Mic1 short IRQ: %d\n",
3591                                  ret);
3592
3593                 ret = wm8994_request_irq(wm8994->wm8994,
3594                                          WM8994_IRQ_MIC2_DET,
3595                                          wm8994_mic_irq, "Mic 2 detect",
3596                                          wm8994);
3597                 if (ret != 0)
3598                         dev_warn(codec->dev,
3599                                  "Failed to request Mic2 detect IRQ: %d\n",
3600                                  ret);
3601
3602                 ret = wm8994_request_irq(wm8994->wm8994,
3603                                          WM8994_IRQ_MIC2_SHRT,
3604                                          wm8994_mic_irq, "Mic 2 short",
3605                                          wm8994);
3606                 if (ret != 0)
3607                         dev_warn(codec->dev,
3608                                  "Failed to request Mic2 short IRQ: %d\n",
3609                                  ret);
3610                 break;
3611
3612         case WM8958:
3613         case WM1811:
3614                 if (wm8994->micdet_irq) {
3615                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3616                                                    wm8958_mic_irq,
3617                                                    IRQF_TRIGGER_RISING,
3618                                                    "Mic detect",
3619                                                    wm8994);
3620                         if (ret != 0)
3621                                 dev_warn(codec->dev,
3622                                          "Failed to request Mic detect IRQ: %d\n",
3623                                          ret);
3624                 }
3625         }
3626
3627         switch (control->type) {
3628         case WM1811:
3629                 if (wm8994->revision > 1) {
3630                         ret = wm8994_request_irq(wm8994->wm8994,
3631                                                  WM8994_IRQ_GPIO(6),
3632                                                  wm1811_jackdet_irq, "JACKDET",
3633                                                  wm8994);
3634                         if (ret == 0)
3635                                 wm8994->jackdet = true;
3636                 }
3637                 break;
3638         default:
3639                 break;
3640         }
3641
3642         wm8994->fll_locked_irq = true;
3643         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3644                 ret = wm8994_request_irq(wm8994->wm8994,
3645                                          WM8994_IRQ_FLL1_LOCK + i,
3646                                          wm8994_fll_locked_irq, "FLL lock",
3647                                          &wm8994->fll_locked[i]);
3648                 if (ret != 0)
3649                         wm8994->fll_locked_irq = false;
3650         }
3651
3652         /* Make sure we can read from the GPIOs if they're inputs */
3653         pm_runtime_get_sync(codec->dev);
3654
3655         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3656          * configured on init - if a system wants to do this dynamically
3657          * at runtime we can deal with that then.
3658          */
3659         ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3660         if (ret < 0) {
3661                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3662                 goto err_irq;
3663         }
3664         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3665                 wm8994->lrclk_shared[0] = 1;
3666                 wm8994_dai[0].symmetric_rates = 1;
3667         } else {
3668                 wm8994->lrclk_shared[0] = 0;
3669         }
3670
3671         ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
3672         if (ret < 0) {
3673                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3674                 goto err_irq;
3675         }
3676         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3677                 wm8994->lrclk_shared[1] = 1;
3678                 wm8994_dai[1].symmetric_rates = 1;
3679         } else {
3680                 wm8994->lrclk_shared[1] = 0;
3681         }
3682
3683         pm_runtime_put(codec->dev);
3684
3685         /* Latch volume updates (right only; we always do left then right). */
3686         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3687                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3688         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3689                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3690         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3691                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3692         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3693                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3694         snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3695                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3696         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3697                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3698         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3699                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3700         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3701                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3702         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3703                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3704         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3705                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3706         snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3707                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3708         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3709                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3710         snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3711                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3712         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3713                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3714         snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3715                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3716         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3717                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3718
3719         /* Set the low bit of the 3D stereo depth so TLV matches */
3720         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3721                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3722                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3723         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3724                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3725                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3726         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3727                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3728                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3729
3730         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3731          * use this; it only affects behaviour on idle TDM clock
3732          * cycles. */
3733         switch (control->type) {
3734         case WM8994:
3735         case WM8958:
3736                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3737                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3738                 break;
3739         default:
3740                 break;
3741         }
3742
3743         /* Put MICBIAS into bypass mode by default on newer devices */
3744         switch (control->type) {
3745         case WM8958:
3746         case WM1811:
3747                 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3748                                     WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3749                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3750                                     WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3751                 break;
3752         default:
3753                 break;
3754         }
3755
3756         wm8994_update_class_w(codec);
3757
3758         wm8994_handle_pdata(wm8994);
3759
3760         wm_hubs_add_analogue_controls(codec);
3761         snd_soc_add_codec_controls(codec, wm8994_snd_controls,
3762                              ARRAY_SIZE(wm8994_snd_controls));
3763         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3764                                   ARRAY_SIZE(wm8994_dapm_widgets));
3765
3766         switch (control->type) {
3767         case WM8994:
3768                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3769                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3770                 if (wm8994->revision < 4) {
3771                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3772                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3773                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3774                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3775                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3776                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3777                 } else {
3778                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3779                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3780                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3781                                                   ARRAY_SIZE(wm8994_adc_widgets));
3782                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3783                                                   ARRAY_SIZE(wm8994_dac_widgets));
3784                 }
3785                 break;
3786         case WM8958:
3787                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
3788                                      ARRAY_SIZE(wm8958_snd_controls));
3789                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3790                                           ARRAY_SIZE(wm8958_dapm_widgets));
3791                 if (wm8994->revision < 1) {
3792                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3793                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3794                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3795                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3796                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3797                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3798                 } else {
3799                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3800                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3801                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3802                                                   ARRAY_SIZE(wm8994_adc_widgets));
3803                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3804                                                   ARRAY_SIZE(wm8994_dac_widgets));
3805                 }
3806                 break;
3807
3808         case WM1811:
3809                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
3810                                      ARRAY_SIZE(wm8958_snd_controls));
3811                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3812                                           ARRAY_SIZE(wm8958_dapm_widgets));
3813                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3814                                           ARRAY_SIZE(wm8994_lateclk_widgets));
3815                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3816                                           ARRAY_SIZE(wm8994_adc_widgets));
3817                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3818                                           ARRAY_SIZE(wm8994_dac_widgets));
3819                 break;
3820         }
3821
3822
3823         wm_hubs_add_analogue_routes(codec, 0, 0);
3824         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3825
3826         switch (control->type) {
3827         case WM8994:
3828                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3829                                         ARRAY_SIZE(wm8994_intercon));
3830
3831                 if (wm8994->revision < 4) {
3832                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3833                                                 ARRAY_SIZE(wm8994_revd_intercon));
3834                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3835                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3836                 } else {
3837                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3838                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3839                 }
3840                 break;
3841         case WM8958:
3842                 if (wm8994->revision < 1) {
3843                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3844                                                 ARRAY_SIZE(wm8994_revd_intercon));
3845                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3846                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3847                 } else {
3848                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3849                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3850                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3851                                                 ARRAY_SIZE(wm8958_intercon));
3852                 }
3853
3854                 wm8958_dsp2_init(codec);
3855                 break;
3856         case WM1811:
3857                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3858                                         ARRAY_SIZE(wm8994_lateclk_intercon));
3859                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3860                                         ARRAY_SIZE(wm8958_intercon));
3861                 break;
3862         }
3863
3864         return 0;
3865
3866 err_irq:
3867         if (wm8994->jackdet)
3868                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3869         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3870         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3871         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
3872         if (wm8994->micdet_irq)
3873                 free_irq(wm8994->micdet_irq, wm8994);
3874         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3875                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3876                                 &wm8994->fll_locked[i]);
3877         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3878                         &wm8994->hubs);
3879         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3880         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3881         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3882
3883         return ret;
3884 }
3885
3886 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3887 {
3888         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3889         struct wm8994 *control = wm8994->wm8994;
3890         int i;
3891
3892         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3893
3894         pm_runtime_disable(codec->dev);
3895
3896         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3897                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3898                                 &wm8994->fll_locked[i]);
3899
3900         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3901                         &wm8994->hubs);
3902         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3903         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3904         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3905
3906         if (wm8994->jackdet)
3907                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3908
3909         switch (control->type) {
3910         case WM8994:
3911                 if (wm8994->micdet_irq)
3912                         free_irq(wm8994->micdet_irq, wm8994);
3913                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3914                                 wm8994);
3915                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3916                                 wm8994);
3917                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3918                                 wm8994);
3919                 break;
3920
3921         case WM1811:
3922         case WM8958:
3923                 if (wm8994->micdet_irq)
3924                         free_irq(wm8994->micdet_irq, wm8994);
3925                 break;
3926         }
3927         if (wm8994->mbc)
3928                 release_firmware(wm8994->mbc);
3929         if (wm8994->mbc_vss)
3930                 release_firmware(wm8994->mbc_vss);
3931         if (wm8994->enh_eq)
3932                 release_firmware(wm8994->enh_eq);
3933         kfree(wm8994->retune_mobile_texts);
3934
3935         return 0;
3936 }
3937
3938 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3939         .probe =        wm8994_codec_probe,
3940         .remove =       wm8994_codec_remove,
3941         .suspend =      wm8994_suspend,
3942         .resume =       wm8994_resume,
3943         .set_bias_level = wm8994_set_bias_level,
3944 };
3945
3946 static int __devinit wm8994_probe(struct platform_device *pdev)
3947 {
3948         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3949                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
3950 }
3951
3952 static int __devexit wm8994_remove(struct platform_device *pdev)
3953 {
3954         snd_soc_unregister_codec(&pdev->dev);
3955         return 0;
3956 }
3957
3958 static struct platform_driver wm8994_codec_driver = {
3959         .driver = {
3960                    .name = "wm8994-codec",
3961                    .owner = THIS_MODULE,
3962                    },
3963         .probe = wm8994_probe,
3964         .remove = __devexit_p(wm8994_remove),
3965 };
3966
3967 module_platform_driver(wm8994_codec_driver);
3968
3969 MODULE_DESCRIPTION("ASoC WM8994 driver");
3970 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3971 MODULE_LICENSE("GPL");
3972 MODULE_ALIAS("platform:wm8994-codec");