2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
20 #include <linux/tty.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/init.h>
25 #include <linux/pci.h>
27 #include <video/tgafb.h>
33 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
34 static int tgafb_set_par(struct fb_info *);
35 static void tgafb_set_pll(struct tga_par *, int);
36 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
37 unsigned, struct fb_info *);
38 static int tgafb_blank(int, struct fb_info *);
39 static void tgafb_init_fix(struct fb_info *);
41 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
42 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
43 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
45 static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
47 static void tgafb_pci_unregister(struct pci_dev *);
50 static const char *mode_option = "640x480@60";
54 * Frame buffer operations
57 static struct fb_ops tgafb_ops = {
59 .fb_check_var = tgafb_check_var,
60 .fb_set_par = tgafb_set_par,
61 .fb_setcolreg = tgafb_setcolreg,
62 .fb_blank = tgafb_blank,
63 .fb_fillrect = tgafb_fillrect,
64 .fb_copyarea = tgafb_copyarea,
65 .fb_imageblit = tgafb_imageblit,
66 .fb_cursor = soft_cursor,
71 * PCI registration operations
74 static struct pci_device_id const tgafb_pci_table[] = {
75 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA, PCI_ANY_ID, PCI_ANY_ID,
79 static struct pci_driver tgafb_driver = {
81 .id_table = tgafb_pci_table,
82 .probe = tgafb_pci_register,
83 .remove = __devexit_p(tgafb_pci_unregister),
88 * tgafb_check_var - Optional function. Validates a var passed in.
89 * @var: frame buffer variable screen structure
90 * @info: frame buffer structure that represents a single frame buffer
93 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
95 struct tga_par *par = (struct tga_par *)info->par;
97 if (par->tga_type == TGA_TYPE_8PLANE) {
98 if (var->bits_per_pixel != 8)
101 if (var->bits_per_pixel != 32)
105 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
109 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
111 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
114 /* Some of the acceleration routines assume the line width is
115 a multiple of 64 bytes. */
116 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 64)
123 * tgafb_set_par - Optional function. Alters the hardware state.
124 * @info: frame buffer structure that represents a single frame buffer
127 tgafb_set_par(struct fb_info *info)
129 static unsigned int const deep_presets[4] = {
135 static unsigned int const rasterop_presets[4] = {
141 static unsigned int const mode_presets[4] = {
147 static unsigned int const base_addr_presets[4] = {
154 struct tga_par *par = (struct tga_par *) info->par;
155 u32 htimings, vtimings, pll_freq;
159 /* Encode video timings. */
160 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
161 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
162 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
163 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
164 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
165 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
166 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
167 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
168 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
170 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
171 htimings |= TGA_HORIZ_POLARITY;
172 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
173 vtimings |= TGA_VERT_POLARITY;
175 par->htimings = htimings;
176 par->vtimings = vtimings;
178 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
180 /* Store other useful values in par. */
181 par->xres = info->var.xres;
182 par->yres = info->var.yres;
183 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
184 par->bits_per_pixel = info->var.bits_per_pixel;
186 tga_type = par->tga_type;
188 /* First, disable video. */
189 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
191 /* Write the DEEP register. */
192 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
195 TGA_WRITE_REG(par, deep_presets[tga_type], TGA_DEEP_REG);
196 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
200 /* Write some more registers. */
201 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
202 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
203 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
205 /* Calculate & write the PLL. */
206 tgafb_set_pll(par, pll_freq);
208 /* Write some more registers. */
209 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
210 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
212 /* Init video timing regs. */
213 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
214 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
216 /* Initalise RAMDAC. */
217 if (tga_type == TGA_TYPE_8PLANE) {
219 /* Init BT485 RAMDAC registers. */
220 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
222 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
223 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
224 BT485_WRITE(par, 0x40, BT485_CMD_1);
225 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
226 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
228 /* Fill palette registers. */
229 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
230 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
232 for (i = 0; i < 16; i++) {
234 TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8),
236 TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8),
238 TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8),
241 for (i = 0; i < 240*3; i += 4) {
242 TGA_WRITE_REG(par, 0x55|(BT485_DATA_PAL<<8),
244 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
246 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
248 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
252 } else { /* 24-plane or 24plusZ */
254 /* Init BT463 registers. */
255 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
256 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
257 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
258 (par->sync_on_green ? 0x80 : 0x40));
260 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
261 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
262 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
263 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
265 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
266 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
267 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
268 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
270 /* Fill the palette. */
271 BT463_LOAD_ADDR(par, 0x0000);
272 TGA_WRITE_REG(par, BT463_PALETTE<<2, TGA_RAMDAC_REG);
274 for (i = 0; i < 16; i++) {
276 TGA_WRITE_REG(par, default_red[j]|(BT463_PALETTE<<10),
278 TGA_WRITE_REG(par, default_grn[j]|(BT463_PALETTE<<10),
280 TGA_WRITE_REG(par, default_blu[j]|(BT463_PALETTE<<10),
283 for (i = 0; i < 512*3; i += 4) {
284 TGA_WRITE_REG(par, 0x55|(BT463_PALETTE<<10),
286 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
288 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
290 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
294 /* Fill window type table after start of vertical retrace. */
295 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
297 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
299 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
301 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
303 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
304 TGA_WRITE_REG(par, BT463_REG_ACC<<2, TGA_RAMDAC_SETUP_REG);
306 for (i = 0; i < 16; i++) {
307 TGA_WRITE_REG(par, 0x00|(BT463_REG_ACC<<10),
309 TGA_WRITE_REG(par, 0x01|(BT463_REG_ACC<<10),
311 TGA_WRITE_REG(par, 0x80|(BT463_REG_ACC<<10),
317 /* Finally, enable video scan (and pray for the monitor... :-) */
318 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
323 #define DIFFCHECK(X) \
326 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
329 if (delta < min_diff) \
330 min_diff = delta, vm = m, va = a, vr = r; \
335 tgafb_set_pll(struct tga_par *par, int f)
337 int n, shift, base, min_diff, target;
338 int r,a,m,vm = 34, va = 1, vr = 30;
340 for (r = 0 ; r < 12 ; r++)
341 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
343 if (f > TGA_PLL_MAX_FREQ)
344 f = TGA_PLL_MAX_FREQ;
346 if (f >= TGA_PLL_MAX_FREQ / 2)
348 else if (f >= TGA_PLL_MAX_FREQ / 4)
353 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
354 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
356 for (r = 0 ; r < 10 ; r++)
357 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
360 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
361 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
363 else if (f <= 200000) {
364 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
365 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
368 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
369 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
372 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
373 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
374 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
375 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
376 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
377 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
379 target = (f << shift) / TGA_PLL_BASE_FREQ;
380 min_diff = TGA_PLL_MAX_FREQ;
387 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
388 m = ((n + 3) / 7) - 1;
390 DIFFCHECK((m + 1) * 7);
392 DIFFCHECK((m + 1) * 7);
403 for (r = 0; r < 8; r++)
404 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
405 for (r = 0; r < 8 ; r++)
406 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
407 for (r = 0; r < 7 ; r++)
408 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
409 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
414 * tgafb_setcolreg - Optional function. Sets a color register.
415 * @regno: boolean, 0 copy local, 1 get_user() function
416 * @red: frame buffer colormap structure
417 * @green: The green value which can be up to 16 bits wide
418 * @blue: The blue value which can be up to 16 bits wide.
419 * @transp: If supported the alpha value which can be up to 16 bits wide.
420 * @info: frame buffer info structure
423 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
424 unsigned transp, struct fb_info *info)
426 struct tga_par *par = (struct tga_par *) info->par;
434 if (par->tga_type == TGA_TYPE_8PLANE) {
435 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
436 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
437 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
438 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
439 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
440 } else if (regno < 16) {
441 u32 value = (red << 16) | (green << 8) | blue;
442 ((u32 *)info->pseudo_palette)[regno] = value;
450 * tgafb_blank - Optional function. Blanks the display.
451 * @blank_mode: the blank mode we want.
452 * @info: frame buffer structure that represents a single frame buffer
455 tgafb_blank(int blank, struct fb_info *info)
457 struct tga_par *par = (struct tga_par *) info->par;
458 u32 vhcr, vvcr, vvvr;
461 local_irq_save(flags);
463 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
464 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
465 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
466 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
469 case 0: /* Unblanking */
470 if (par->vesa_blanked) {
471 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
472 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
473 par->vesa_blanked = 0;
475 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
478 case 1: /* Normal blanking */
479 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
483 case 2: /* VESA blank (vsync off) */
484 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
485 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
486 par->vesa_blanked = 1;
489 case 3: /* VESA blank (hsync off) */
490 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
491 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
492 par->vesa_blanked = 1;
495 case 4: /* Poweroff */
496 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
497 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
498 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
499 par->vesa_blanked = 1;
503 local_irq_restore(flags);
513 * tgafb_imageblit - REQUIRED function. Can use generic routines if
514 * non acclerated hardware and packed pixel based.
515 * Copies a image from system memory to the screen.
517 * @info: frame buffer structure that represents a single frame buffer
518 * @image: structure defining the image.
521 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
523 static unsigned char const bitrev[256] = {
524 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
525 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
526 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
527 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
528 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
529 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
530 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
531 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
532 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
533 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
534 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
535 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
536 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
537 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
538 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
539 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
540 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
541 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
542 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
543 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
544 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
545 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
546 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
547 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
548 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
549 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
550 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
551 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
552 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
553 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
554 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
555 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff
558 struct tga_par *par = (struct tga_par *) info->par;
559 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
560 unsigned long rincr, line_length, shift, pos, is8bpp;
562 const unsigned char *data;
563 void *regs_base, *fb_base;
567 width = image->width;
568 height = image->height;
569 vxres = info->var.xres_virtual;
570 vyres = info->var.yres_virtual;
571 line_length = info->fix.line_length;
572 rincr = (width + 7) / 8;
574 /* Crop the image to the screen. */
575 if (dx > vxres || dy > vyres)
577 if (dx + width > vxres)
579 if (dy + height > vyres)
582 /* For copies that aren't pixel expansion, there's little we
583 can do better than the generic code. */
584 /* ??? There is a DMA write mode; I wonder if that could be
585 made to pull the data from the image buffer... */
586 if (image->depth > 1) {
587 cfb_imageblit(info, image);
591 regs_base = par->tga_regs_base;
592 fb_base = par->tga_fb_base;
593 is8bpp = info->var.bits_per_pixel == 8;
595 /* Expand the color values to fill 32-bits. */
596 /* ??? Would be nice to notice colour changes elsewhere, so
597 that we can do this only when necessary. */
598 fgcolor = image->fg_color;
599 bgcolor = image->bg_color;
601 fgcolor |= fgcolor << 8;
602 fgcolor |= fgcolor << 16;
603 bgcolor |= bgcolor << 8;
604 bgcolor |= bgcolor << 16;
607 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
609 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
611 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
612 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
614 /* Acquire proper alignment; set up the PIXELMASK register
615 so that we only write the proper character cell. */
616 pos = dy * line_length;
623 shift = (pos & 7) >> 2;
627 data = (const unsigned char *) image->data;
629 /* Enable opaque stipple mode. */
631 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
632 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
633 regs_base + TGA_MODE_REG);
635 if (width + shift <= 32) {
636 unsigned long bwidth;
638 /* Handle common case of imaging a single character, in
639 a font less than 32 pixels wide. */
641 pixelmask = (1 << width) - 1;
643 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
646 bwidth = (width + 7) / 8;
648 for (i = 0; i < height; ++i) {
651 /* The image data is bit big endian; we need
653 for (j = 0; j < bwidth; ++j)
654 mask |= bitrev[data[j]] << (j * 8);
656 __raw_writel(mask << shift, fb_base + pos);
662 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
663 } else if (shift == 0) {
664 unsigned long pos0 = pos;
665 const unsigned char *data0 = data;
666 unsigned long bincr = (is8bpp ? 8 : 8*4);
667 unsigned long bwidth;
669 /* Handle another common case in which accel_putcs
670 generates a large bitmap, which happens to be aligned.
671 Allow the tail to be misaligned. This case is
672 interesting because we've not got to hold partial
673 bytes across the words being written. */
677 bwidth = (width / 8) & -4;
678 for (i = 0; i < height; ++i) {
679 for (j = 0; j < bwidth; j += 4) {
681 mask |= bitrev[data[j+0]] << (0 * 8);
682 mask |= bitrev[data[j+1]] << (1 * 8);
683 mask |= bitrev[data[j+2]] << (2 * 8);
684 mask |= bitrev[data[j+3]] << (3 * 8);
685 __raw_writel(mask, fb_base + pos + j*bincr);
692 pixelmask = (1ul << (width & 31)) - 1;
694 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
697 pos = pos0 + bwidth*bincr;
698 data = data0 + bwidth;
699 bwidth = ((width & 31) + 7) / 8;
701 for (i = 0; i < height; ++i) {
703 for (j = 0; j < bwidth; ++j)
704 mask |= bitrev[data[j]] << (j * 8);
705 __raw_writel(mask, fb_base + pos);
710 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
713 unsigned long pos0 = pos;
714 const unsigned char *data0 = data;
715 unsigned long bincr = (is8bpp ? 8 : 8*4);
716 unsigned long bwidth;
718 /* Finally, handle the generic case of misaligned start.
719 Here we split the write into 16-bit spans. This allows
720 us to use only one pixel mask, instead of four as would
721 be required by writing 24-bit spans. */
723 pixelmask = 0xffff << shift;
724 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
727 bwidth = (width / 8) & -2;
728 for (i = 0; i < height; ++i) {
729 for (j = 0; j < bwidth; j += 2) {
731 mask |= bitrev[data[j+0]] << (0 * 8);
732 mask |= bitrev[data[j+1]] << (1 * 8);
734 __raw_writel(mask, fb_base + pos + j*bincr);
741 pixelmask = ((1ul << (width & 15)) - 1) << shift;
743 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
746 pos = pos0 + bwidth*bincr;
747 data = data0 + bwidth;
748 bwidth = (width & 15) > 8;
750 for (i = 0; i < height; ++i) {
751 u32 mask = bitrev[data[0]];
753 mask |= bitrev[data[1]] << 8;
755 __raw_writel(mask, fb_base + pos);
761 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
764 /* Disable opaque stipple mode. */
766 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
767 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
768 regs_base + TGA_MODE_REG);
772 * tgafb_fillrect - REQUIRED function. Can use generic routines if
773 * non acclerated hardware and packed pixel based.
774 * Draws a rectangle on the screen.
776 * @info: frame buffer structure that represents a single frame buffer
777 * @rect: structure defining the rectagle and operation.
780 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
782 struct tga_par *par = (struct tga_par *) info->par;
783 int is8bpp = info->var.bits_per_pixel == 8;
784 u32 dx, dy, width, height, vxres, vyres, color;
785 unsigned long pos, align, line_length, i, j;
786 void *regs_base, *fb_base;
791 height = rect->height;
792 vxres = info->var.xres_virtual;
793 vyres = info->var.yres_virtual;
794 line_length = info->fix.line_length;
795 regs_base = par->tga_regs_base;
796 fb_base = par->tga_fb_base;
798 /* Crop the rectangle to the screen. */
799 if (dx > vxres || dy > vyres || !width || !height)
801 if (dx + width > vxres)
803 if (dy + height > vyres)
806 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
808 /* ??? We could implement ROP_XOR with opaque fill mode
809 and a RasterOp setting of GXxor, but as far as I can
810 tell, this mode is not actually used in the kernel.
811 Thus I am ignoring it for now. */
812 if (rect->rop != ROP_COPY) {
813 cfb_fillrect(info, rect);
817 /* Expand the color value to fill 8 pixels. */
821 color |= color << 16;
822 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
823 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
826 color = ((u32 *)info->pseudo_palette)[color];
827 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
828 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
829 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
830 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
831 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
832 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
833 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
834 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
837 /* The DATA register holds the fill mask for block fill mode.
838 Since we're not stippling, this is all ones. */
839 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
841 /* Enable block fill mode. */
843 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
844 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
845 regs_base + TGA_MODE_REG);
848 /* We can fill 2k pixels per operation. Notice blocks that fit
849 the width of the screen so that we can take advantage of this
850 and fill more than one line per write. */
851 if (width == line_length)
852 width *= height, height = 1;
854 /* The write into the frame buffer must be aligned to 4 bytes,
855 but we are allowed to encode the offset within the word in
856 the data word written. */
857 align = (pos & 3) << 16;
863 data = (width - 1) | align;
865 for (i = 0; i < height; ++i) {
866 __raw_writel(data, fb_base + pos);
870 unsigned long Bpp = (is8bpp ? 1 : 4);
871 unsigned long nwidth = width & -2048;
874 fdata = (2048 - 1) | align;
875 ldata = ((width & 2047) - 1) | align;
877 for (i = 0; i < height; ++i) {
878 for (j = 0; j < nwidth; j += 2048)
879 __raw_writel(fdata, fb_base + pos + j*Bpp);
881 __raw_writel(ldata, fb_base + pos + j*Bpp);
887 /* Disable block fill mode. */
889 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
890 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
891 regs_base + TGA_MODE_REG);
895 * tgafb_copyarea - REQUIRED function. Can use generic routines if
896 * non acclerated hardware and packed pixel based.
897 * Copies on area of the screen to another area.
899 * @info: frame buffer structure that represents a single frame buffer
900 * @area: structure defining the source and destination.
903 /* Handle the special case of copying entire lines, e.g. during scrolling.
904 We can avoid a lot of needless computation in this case. In the 8bpp
905 case we need to use the COPY64 registers instead of mask writes into
906 the frame buffer to achieve maximum performance. */
909 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
910 u32 height, u32 width)
912 struct tga_par *par = (struct tga_par *) info->par;
913 void *tga_regs = par->tga_regs_base;
914 unsigned long dpos, spos, i, n64;
916 /* Set up the MODE and PIXELSHIFT registers. */
917 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
918 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
921 n64 = (height * width) / 64;
924 spos = (sy + height) * width;
925 dpos = (dy + height) * width;
927 for (i = 0; i < n64; ++i) {
930 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
932 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
939 for (i = 0; i < n64; ++i) {
940 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
942 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
949 /* Reset the MODE register to normal. */
950 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
954 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
955 u32 height, u32 width)
957 struct tga_par *par = (struct tga_par *) info->par;
958 void *tga_regs = par->tga_regs_base;
959 void *tga_fb = par->tga_fb_base;
961 unsigned long i, n16;
963 /* Set up the MODE and PIXELSHIFT registers. */
964 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
965 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
968 n16 = (height * width) / 16;
971 src = tga_fb + (sy + height) * width * 4;
972 dst = tga_fb + (dy + height) * width * 4;
974 for (i = 0; i < n16; ++i) {
977 __raw_writel(0xffff, src);
979 __raw_writel(0xffff, dst);
983 src = tga_fb + sy * width * 4;
984 dst = tga_fb + dy * width * 4;
986 for (i = 0; i < n16; ++i) {
987 __raw_writel(0xffff, src);
989 __raw_writel(0xffff, dst);
996 /* Reset the MODE register to normal. */
997 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1000 /* The general case of forward copy in 8bpp mode. */
1002 copyarea_foreward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1003 u32 height, u32 width, u32 line_length)
1005 struct tga_par *par = (struct tga_par *) info->par;
1006 unsigned long i, copied, left;
1007 unsigned long dpos, spos, dalign, salign, yincr;
1008 u32 smask_first, dmask_first, dmask_last;
1009 int pixel_shift, need_prime, need_second;
1010 unsigned long n64, n32, xincr_first;
1011 void *tga_regs, *tga_fb;
1013 yincr = line_length;
1020 /* Compute the offsets and alignments in the frame buffer.
1021 More than anything else, these control how we do copies. */
1022 dpos = dy * line_length + dx;
1023 spos = sy * line_length + sx;
1029 /* Compute the value for the PIXELSHIFT register. This controls
1030 both non-co-aligned source and destination and copy direction. */
1031 if (dalign >= salign)
1032 pixel_shift = dalign - salign;
1034 pixel_shift = 8 - (salign - dalign);
1036 /* Figure out if we need an additional priming step for the
1037 residue register. */
1038 need_prime = (salign > dalign);
1042 /* Begin by copying the leading unaligned destination. Copy enough
1043 to make the next destination address 32-byte aligned. */
1044 copied = 32 - (dalign + (dpos & 31));
1047 xincr_first = (copied + 7) & -8;
1048 smask_first = dmask_first = (1ul << copied) - 1;
1049 smask_first <<= salign;
1050 dmask_first <<= dalign + need_prime*8;
1051 if (need_prime && copied > 24)
1053 left = width - copied;
1055 /* Care for small copies. */
1056 if (copied > width) {
1058 t = (1ul << width) - 1;
1059 t <<= dalign + need_prime*8;
1064 /* Attempt to use 64-byte copies. This is only possible if the
1065 source and destination are co-aligned at 64 bytes. */
1066 n64 = need_second = 0;
1067 if ((dpos & 63) == (spos & 63)
1068 && (height == 1 || line_length % 64 == 0)) {
1069 /* We may need a 32-byte copy to ensure 64 byte alignment. */
1070 need_second = (dpos + xincr_first) & 63;
1071 if ((need_second & 32) != need_second)
1072 printk(KERN_ERR "tgafb: need_second wrong\n");
1073 if (left >= need_second + 64) {
1074 left -= need_second;
1081 /* Copy trailing full 32-byte sections. This will be the main
1082 loop if the 64 byte loop can't be used. */
1086 /* Copy the trailing unaligned destination. */
1087 dmask_last = (1ul << left) - 1;
1089 tga_regs = par->tga_regs_base;
1090 tga_fb = par->tga_fb_base;
1092 /* Set up the MODE and PIXELSHIFT registers. */
1093 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1094 __raw_writel(pixel_shift, tga_regs+TGA_PIXELSHIFT_REG);
1097 for (i = 0; i < height; ++i) {
1101 sfb = tga_fb + spos;
1102 dfb = tga_fb + dpos;
1104 __raw_writel(smask_first, sfb);
1106 __raw_writel(dmask_first, dfb);
1113 __raw_writel(0xffffffff, sfb);
1115 __raw_writel(0xffffffff, dfb);
1121 if (n64 && (((long)sfb | (long)dfb) & 63))
1123 "tgafb: misaligned copy64 (s:%p, d:%p)\n",
1126 for (j = 0; j < n64; ++j) {
1127 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1129 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1135 for (j = 0; j < n32; ++j) {
1136 __raw_writel(0xffffffff, sfb);
1138 __raw_writel(0xffffffff, dfb);
1145 __raw_writel(0xffffffff, sfb);
1147 __raw_writel(dmask_last, dfb);
1155 /* Reset the MODE register to normal. */
1156 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1159 /* The (almost) general case of backward copy in 8bpp mode. */
1161 copyarea_backward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1162 u32 height, u32 width, u32 line_length,
1163 const struct fb_copyarea *area)
1165 struct tga_par *par = (struct tga_par *) info->par;
1166 unsigned long i, left, yincr;
1167 unsigned long depos, sepos, dealign, sealign;
1168 u32 mask_first, mask_last;
1170 void *tga_regs, *tga_fb;
1172 yincr = line_length;
1179 /* Compute the offsets and alignments in the frame buffer.
1180 More than anything else, these control how we do copies. */
1181 depos = dy * line_length + dx + width;
1182 sepos = sy * line_length + sx + width;
1183 dealign = depos & 7;
1184 sealign = sepos & 7;
1186 /* ??? The documentation appears to be incorrect (or very
1187 misleading) wrt how pixel shifting works in backward copy
1188 mode, i.e. when PIXELSHIFT is negative. I give up for now.
1189 Do handle the common case of co-aligned backward copies,
1190 but frob everything else back on generic code. */
1191 if (dealign != sealign) {
1192 cfb_copyarea(info, area);
1196 /* We begin the copy with the trailing pixels of the
1197 unaligned destination. */
1198 mask_first = (1ul << dealign) - 1;
1199 left = width - dealign;
1201 /* Care for small copies. */
1202 if (dealign > width) {
1203 mask_first ^= (1ul << (dealign - width)) - 1;
1207 /* Next copy full words at a time. */
1211 /* Finally copy the unaligned head of the span. */
1212 mask_last = -1 << (32 - left);
1214 tga_regs = par->tga_regs_base;
1215 tga_fb = par->tga_fb_base;
1217 /* Set up the MODE and PIXELSHIFT registers. */
1218 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1219 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1222 for (i = 0; i < height; ++i) {
1226 sfb = tga_fb + sepos;
1227 dfb = tga_fb + depos;
1229 __raw_writel(mask_first, sfb);
1231 __raw_writel(mask_first, dfb);
1235 for (j = 0; j < n32; ++j) {
1238 __raw_writel(0xffffffff, sfb);
1240 __raw_writel(0xffffffff, dfb);
1247 __raw_writel(mask_last, sfb);
1249 __raw_writel(mask_last, dfb);
1257 /* Reset the MODE register to normal. */
1258 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1262 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1264 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1265 unsigned long line_length, bpp;
1269 width = area->width;
1270 height = area->height;
1273 vxres = info->var.xres_virtual;
1274 vyres = info->var.yres_virtual;
1275 line_length = info->fix.line_length;
1277 /* The top left corners must be in the virtual screen. */
1278 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1281 /* Clip the destination. */
1282 if (dx + width > vxres)
1284 if (dy + height > vyres)
1285 height = vyres - dy;
1287 /* The source must be completely inside the virtual screen. */
1288 if (sx + width > vxres || sy + height > vyres)
1291 bpp = info->var.bits_per_pixel;
1293 /* Detect copies of the entire line. */
1294 if (width * (bpp >> 3) == line_length) {
1296 copyarea_line_8bpp(info, dy, sy, height, width);
1298 copyarea_line_32bpp(info, dy, sy, height, width);
1301 /* ??? The documentation is unclear to me exactly how the pixelshift
1302 register works in 32bpp mode. Since I don't have hardware to test,
1303 give up for now and fall back on the generic routines. */
1305 cfb_copyarea(info, area);
1307 /* Detect overlapping source and destination that requires
1309 else if (dy == sy && dx > sx && dx < sx + width)
1310 copyarea_backward_8bpp(info, dx, dy, sx, sy, height,
1311 width, line_length, area);
1313 copyarea_foreward_8bpp(info, dx, dy, sx, sy, height,
1314 width, line_length);
1323 tgafb_init_fix(struct fb_info *info)
1325 struct tga_par *par = (struct tga_par *)info->par;
1326 u8 tga_type = par->tga_type;
1327 const char *tga_type_name;
1330 case TGA_TYPE_8PLANE:
1331 tga_type_name = "Digital ZLXp-E1";
1333 case TGA_TYPE_24PLANE:
1334 tga_type_name = "Digital ZLXp-E2";
1336 case TGA_TYPE_24PLUSZ:
1337 tga_type_name = "Digital ZLXp-E3";
1340 tga_type_name = "Unknown";
1344 strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1346 info->fix.type = FB_TYPE_PACKED_PIXELS;
1347 info->fix.type_aux = 0;
1348 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1349 ? FB_VISUAL_PSEUDOCOLOR
1350 : FB_VISUAL_TRUECOLOR);
1352 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
1353 info->fix.smem_start = (size_t) par->tga_fb_base;
1354 info->fix.smem_len = info->fix.line_length * par->yres;
1355 info->fix.mmio_start = (size_t) par->tga_regs_base;
1356 info->fix.mmio_len = 512;
1358 info->fix.xpanstep = 0;
1359 info->fix.ypanstep = 0;
1360 info->fix.ywrapstep = 0;
1362 info->fix.accel = FB_ACCEL_DEC_TGA;
1365 static __devinit int
1366 tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent)
1368 static unsigned int const fb_offset_presets[4] = {
1369 TGA_8PLANE_FB_OFFSET,
1370 TGA_24PLANE_FB_OFFSET,
1372 TGA_24PLUSZ_FB_OFFSET
1376 struct fb_info info;
1378 u32 pseudo_palette[16];
1382 unsigned long bar0_start, bar0_len;
1386 /* Enable device in PCI config. */
1387 if (pci_enable_device(pdev)) {
1388 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1392 /* Allocate the fb and par structures. */
1393 all = kmalloc(sizeof(*all), GFP_KERNEL);
1395 printk(KERN_ERR "tgafb: Cannot allocate memory\n");
1398 memset(all, 0, sizeof(*all));
1399 pci_set_drvdata(pdev, all);
1401 /* Request the mem regions. */
1402 bar0_start = pci_resource_start(pdev, 0);
1403 bar0_len = pci_resource_len(pdev, 0);
1405 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1406 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1410 /* Map the framebuffer. */
1411 mem_base = ioremap(bar0_start, bar0_len);
1413 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1417 /* Grab info about the card. */
1418 tga_type = (readl(mem_base) >> 12) & 0x0f;
1419 all->par.pdev = pdev;
1420 all->par.tga_mem_base = mem_base;
1421 all->par.tga_fb_base = mem_base + fb_offset_presets[tga_type];
1422 all->par.tga_regs_base = mem_base + TGA_REGS_OFFSET;
1423 all->par.tga_type = tga_type;
1424 pci_read_config_byte(pdev, PCI_REVISION_ID, &all->par.tga_chip_rev);
1426 /* Setup framebuffer. */
1427 all->info.flags = FBINFO_FLAG_DEFAULT;
1428 all->info.fbops = &tgafb_ops;
1429 all->info.screen_base = (char *) all->par.tga_fb_base;
1430 all->info.currcon = -1;
1431 all->info.par = &all->par;
1432 all->info.pseudo_palette = all->pseudo_palette;
1433 all->info.dev = &pdev->dev;
1435 /* This should give a reasonable default video mode. */
1437 ret = fb_find_mode(&all->info.var, &all->info, mode_option,
1439 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1440 if (ret == 0 || ret == 4) {
1441 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1446 if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
1447 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1452 tgafb_set_par(&all->info);
1453 tgafb_init_fix(&all->info);
1455 if (register_framebuffer(&all->info) < 0) {
1456 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1461 printk(KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1462 all->par.tga_chip_rev);
1463 printk(KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n",
1464 pdev->bus->number, PCI_SLOT(pdev->devfn),
1465 PCI_FUNC(pdev->devfn));
1466 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n",
1467 all->info.node, all->info.fix.id, bar0_start);
1472 release_mem_region(bar0_start, bar0_len);
1481 return pci_module_init(&tgafb_driver);
1486 tgafb_pci_unregister(struct pci_dev *pdev)
1488 struct fb_info *info = pci_get_drvdata(pdev);
1489 struct tga_par *par = info->par;
1493 unregister_framebuffer(info);
1494 iounmap(par->tga_mem_base);
1495 release_mem_region(pci_resource_start(pdev, 0),
1496 pci_resource_len(pdev, 0));
1503 pci_unregister_driver(&tgafb_driver);
1509 tgafb_setup(char *arg)
1514 while ((this_opt = strsep(&arg, ","))) {
1517 if (!strncmp(this_opt, "mode:", 5))
1518 mode_option = this_opt+5;
1521 "tgafb: unknown parameter %s\n",
1528 #endif /* !MODULE */
1535 module_init(tgafb_init);
1536 module_exit(tgafb_exit);
1539 MODULE_DESCRIPTION("framebuffer driver for TGA chipset");
1540 MODULE_LICENSE("GPL");