3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/errno.h>
23 #include <linux/sys.h>
24 #include <linux/threads.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/unistd.h>
33 #include <asm/ftrace.h>
34 #include <asm/ptrace.h>
37 #undef SHOW_SYSCALLS_TASK
40 * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
42 #if MSR_KERNEL >= 0x10000
43 #define LOAD_MSR_KERNEL(r, x) lis r,(x)@h; ori r,r,(x)@l
45 #define LOAD_MSR_KERNEL(r, x) li r,(x)
49 .globl mcheck_transfer_to_handler
50 mcheck_transfer_to_handler:
57 .globl debug_transfer_to_handler
58 debug_transfer_to_handler:
65 .globl crit_transfer_to_handler
66 crit_transfer_to_handler:
67 #ifdef CONFIG_PPC_BOOK3E_MMU
78 #ifdef CONFIG_PHYS_64BIT
81 #endif /* CONFIG_PHYS_64BIT */
82 #endif /* CONFIG_PPC_BOOK3E_MMU */
92 mfspr r8,SPRN_SPRG_THREAD
94 stw r0,SAVED_KSP_LIMIT(r11)
95 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
101 .globl crit_transfer_to_handler
102 crit_transfer_to_handler:
108 stw r0,crit_srr0@l(0)
110 stw r0,crit_srr1@l(0)
112 mfspr r8,SPRN_SPRG_THREAD
114 stw r0,saved_ksp_limit@l(0)
115 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
121 * This code finishes saving the registers to the exception frame
122 * and jumps to the appropriate handler for the exception, turning
123 * on address translation.
124 * Note that we rely on the caller having set cr0.eq iff the exception
125 * occurred in kernel mode (i.e. MSR:PR = 0).
127 .globl transfer_to_handler_full
128 transfer_to_handler_full:
132 .globl transfer_to_handler
142 mfspr r12,SPRN_SPRG_THREAD
144 tovirt(r2,r2) /* set r2 to current */
145 beq 2f /* if from user, fix up THREAD.regs */
146 addi r11,r1,STACK_FRAME_OVERHEAD
148 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
149 /* Check to see if the dbcr0 register is set up to debug. Use the
150 internal debug mode bit to do this. */
151 lwz r12,THREAD_DBCR0(r12)
152 andis. r12,r12,DBCR0_IDM@h
154 /* From user and task is ptraced - load up global dbcr0 */
155 li r12,-1 /* clear all pending debug events */
157 lis r11,global_dbcr0@ha
159 addi r11,r11,global_dbcr0@l
161 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
174 2: /* if from kernel, check interrupted DOZE/NAP mode and
175 * check for stack overflow
177 lwz r9,KSP_LIMIT(r12)
178 cmplw r1,r9 /* if r1 <= ksp_limit */
179 ble- stack_ovf /* then the kernel stack overflowed */
181 #if defined(CONFIG_6xx) || defined(CONFIG_E500)
182 rlwinm r9,r1,0,0,31-THREAD_SHIFT
183 tophys(r9,r9) /* check local flags */
184 lwz r12,TI_LOCAL_FLAGS(r9)
186 bt- 31-TLF_NAPPING,4f
187 bt- 31-TLF_SLEEPING,7f
188 #endif /* CONFIG_6xx || CONFIG_E500 */
189 .globl transfer_to_handler_cont
190 transfer_to_handler_cont:
193 lwz r11,0(r9) /* virtual address of handler */
194 lwz r9,4(r9) /* where to go when done */
195 #ifdef CONFIG_TRACE_IRQFLAGS
196 lis r12,reenable_mmu@h
197 ori r12,r12,reenable_mmu@l
202 reenable_mmu: /* re-enable mmu so we can */
206 andi. r10,r10,MSR_EE /* Did EE change? */
210 * The trace_hardirqs_off will use CALLER_ADDR0 and CALLER_ADDR1.
211 * If from user mode there is only one stack frame on the stack, and
212 * accessing CALLER_ADDR1 will cause oops. So we need create a dummy
213 * stack frame to make trace_hardirqs_off happy.
215 * This is handy because we also need to save a bunch of GPRs,
216 * r3 can be different from GPR3(r1) at this point, r9 and r11
217 * contains the old MSR and handler address respectively,
218 * r4 & r5 can contain page fault arguments that need to be passed
219 * along as well. r12, CCR, CTR, XER etc... are left clobbered as
220 * they aren't useful past this point (aren't syscall arguments),
221 * the rest is restored from the exception frame.
231 bl trace_hardirqs_off
234 bl trace_hardirqs_off
248 bctr /* jump to handler */
249 #else /* CONFIG_TRACE_IRQFLAGS */
254 RFI /* jump to handler, enable MMU */
255 #endif /* CONFIG_TRACE_IRQFLAGS */
257 #if defined (CONFIG_6xx) || defined(CONFIG_E500)
258 4: rlwinm r12,r12,0,~_TLF_NAPPING
259 stw r12,TI_LOCAL_FLAGS(r9)
260 b power_save_ppc32_restore
262 7: rlwinm r12,r12,0,~_TLF_SLEEPING
263 stw r12,TI_LOCAL_FLAGS(r9)
264 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
265 rlwinm r9,r9,0,~MSR_EE
266 lwz r12,_LINK(r11) /* and return to address in LR */
267 b fast_exception_return
271 * On kernel stack overflow, load up an initial stack pointer
272 * and call StackOverflow(regs), which should not return.
275 /* sometimes we use a statically-allocated stack, which is OK. */
279 ble 5b /* r1 <= &_end is OK */
281 addi r3,r1,STACK_FRAME_OVERHEAD
282 lis r1,init_thread_union@ha
283 addi r1,r1,init_thread_union@l
284 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
285 lis r9,StackOverflow@ha
286 addi r9,r9,StackOverflow@l
287 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
295 * Handle a system call.
297 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
298 .stabs "entry_32.S",N_SO,0,0,0f
305 lwz r11,_CCR(r1) /* Clear SO bit in CR */
310 #endif /* SHOW_SYSCALLS */
311 #ifdef CONFIG_TRACE_IRQFLAGS
312 /* Return from syscalls can (and generally will) hard enable
313 * interrupts. You aren't supposed to call a syscall with
314 * interrupts disabled in the first place. However, to ensure
315 * that we get it right vs. lockdep if it happens, we force
316 * that hard enable here with appropriate tracing if we see
317 * that we have been called with interrupts off
322 /* We came in with interrupts disabled, we enable them now */
335 #endif /* CONFIG_TRACE_IRQFLAGS */
336 rlwinm r10,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
337 lwz r11,TI_FLAGS(r10)
338 andi. r11,r11,_TIF_SYSCALL_T_OR_A
340 syscall_dotrace_cont:
341 cmplwi 0,r0,NR_syscalls
342 lis r10,sys_call_table@h
343 ori r10,r10,sys_call_table@l
346 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
348 addi r9,r1,STACK_FRAME_OVERHEAD
350 blrl /* Call handler */
351 .globl ret_from_syscall
354 bl do_show_syscall_exit
357 rlwinm r12,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
358 /* disable interrupts so current_thread_info()->flags can't change */
359 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
360 /* Note: We don't bother telling lockdep about it */
365 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
366 bne- syscall_exit_work
368 blt+ syscall_exit_cont
369 lwz r11,_CCR(r1) /* Load CR */
371 oris r11,r11,0x1000 /* Set SO bit in CR */
375 #ifdef CONFIG_TRACE_IRQFLAGS
376 /* If we are going to return from the syscall with interrupts
377 * off, we trace that here. It shouldn't happen though but we
378 * want to catch the bugger if it does right ?
383 bl trace_hardirqs_off
386 #endif /* CONFIG_TRACE_IRQFLAGS */
387 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
388 /* If the process has its own DBCR0 value, load it up. The internal
389 debug mode bit tells us that dbcr0 should be loaded. */
390 lwz r0,THREAD+THREAD_DBCR0(r2)
391 andis. r10,r0,DBCR0_IDM@h
395 BEGIN_MMU_FTR_SECTION
396 lis r4,icache_44x_need_flush@ha
397 lwz r5,icache_44x_need_flush@l(r4)
401 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x)
402 #endif /* CONFIG_44x */
405 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
406 stwcx. r0,0,r1 /* to clear the reservation */
422 stw r7,icache_44x_need_flush@l(r4)
424 #endif /* CONFIG_44x */
436 /* Traced system call support */
441 addi r3,r1,STACK_FRAME_OVERHEAD
442 bl do_syscall_trace_enter
444 * Restore argument registers possibly just changed.
445 * We use the return value of do_syscall_trace_enter
446 * for call number to look up in the table (r0).
456 b syscall_dotrace_cont
459 andi. r0,r9,_TIF_RESTOREALL
465 andi. r0,r9,_TIF_NOERROR
467 lwz r11,_CCR(r1) /* Load CR */
469 oris r11,r11,0x1000 /* Set SO bit in CR */
472 1: stw r6,RESULT(r1) /* Save result */
473 stw r3,GPR3(r1) /* Update return value */
474 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
477 /* Clear per-syscall TIF flags if any are set. */
479 li r11,_TIF_PERSYSCALL_MASK
480 addi r12,r12,TI_FLAGS
483 #ifdef CONFIG_IBM405_ERR77
488 subi r12,r12,TI_FLAGS
490 4: /* Anything which requires enabling interrupts? */
491 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
494 /* Re-enable interrupts. There is no need to trace that with
495 * lockdep as we are supposed to have IRQs on at this point
501 /* Save NVGPRS if they're not saved already */
509 addi r3,r1,STACK_FRAME_OVERHEAD
510 bl do_syscall_trace_leave
511 b ret_from_except_full
515 #ifdef SHOW_SYSCALLS_TASK
516 lis r11,show_syscalls_task@ha
517 lwz r11,show_syscalls_task@l(r11)
548 do_show_syscall_exit:
549 #ifdef SHOW_SYSCALLS_TASK
550 lis r11,show_syscalls_task@ha
551 lwz r11,show_syscalls_task@l(r11)
557 stw r3,RESULT(r1) /* Save result */
567 7: .string "syscall %d(%x, %x, %x, %x, %x, "
568 77: .string "%x), current=%p\n"
569 79: .string " -> %x\n"
572 #ifdef SHOW_SYSCALLS_TASK
574 .globl show_syscalls_task
579 #endif /* SHOW_SYSCALLS */
582 * The fork/clone functions need to copy the full register set into
583 * the child process. Therefore we need to save all the nonvolatile
584 * registers (r13 - r31) before calling the C code.
590 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
591 stw r0,_TRAP(r1) /* register set saved */
598 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
599 stw r0,_TRAP(r1) /* register set saved */
606 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
607 stw r0,_TRAP(r1) /* register set saved */
610 .globl ppc_swapcontext
614 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
615 stw r0,_TRAP(r1) /* register set saved */
619 * Top-level page fault handling.
620 * This is in assembler because if do_page_fault tells us that
621 * it is a bad kernel page fault, we want to save the non-volatile
622 * registers before calling bad_page_fault.
624 .globl handle_page_fault
627 addi r3,r1,STACK_FRAME_OVERHEAD
636 addi r3,r1,STACK_FRAME_OVERHEAD
639 b ret_from_except_full
642 * This routine switches between two different tasks. The process
643 * state of one is saved on its kernel stack. Then the state
644 * of the other is restored from its kernel stack. The memory
645 * management hardware is updated to the second process's state.
646 * Finally, we can return to the second process.
647 * On entry, r3 points to the THREAD for the current task, r4
648 * points to the THREAD for the new task.
650 * This routine is always called with interrupts disabled.
652 * Note: there are two ways to get to the "going out" portion
653 * of this code; either by coming in via the entry (_switch)
654 * or via "fork" which must set up an environment equivalent
655 * to the "_switch" path. If you change this , you'll have to
656 * change the fork code also.
658 * The code which creates the new task context is in 'copy_thread'
659 * in arch/ppc/kernel/process.c
662 stwu r1,-INT_FRAME_SIZE(r1)
664 stw r0,INT_FRAME_SIZE+4(r1)
665 /* r3-r12 are caller saved -- Cort */
667 stw r0,_NIP(r1) /* Return to switch caller */
669 li r0,MSR_FP /* Disable floating-point */
670 #ifdef CONFIG_ALTIVEC
672 oris r0,r0,MSR_VEC@h /* Disable altivec */
673 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
674 stw r12,THREAD+THREAD_VRSAVE(r2)
675 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
676 #endif /* CONFIG_ALTIVEC */
679 oris r0,r0,MSR_SPE@h /* Disable SPE */
680 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
681 stw r12,THREAD+THREAD_SPEFSCR(r2)
682 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
683 #endif /* CONFIG_SPE */
684 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
692 stw r1,KSP(r3) /* Set old stack pointer */
695 /* We need a sync somewhere here to make sure that if the
696 * previous task gets rescheduled on another CPU, it sees all
697 * stores it has performed on this one.
700 #endif /* CONFIG_SMP */
704 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
705 lwz r1,KSP(r4) /* Load new stack pointer */
707 /* save the old current 'last' for return value */
709 addi r2,r4,-THREAD /* Update current */
711 #ifdef CONFIG_ALTIVEC
713 lwz r0,THREAD+THREAD_VRSAVE(r2)
714 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
715 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
716 #endif /* CONFIG_ALTIVEC */
719 lwz r0,THREAD+THREAD_SPEFSCR(r2)
720 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
721 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
722 #endif /* CONFIG_SPE */
726 /* r3-r12 are destroyed -- Cort */
729 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
731 addi r1,r1,INT_FRAME_SIZE
734 .globl fast_exception_return
735 fast_exception_return:
736 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
737 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
738 beq 1f /* if not, we've got problems */
741 2: REST_4GPRS(3, r11)
756 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
757 /* check if the exception happened in a restartable section */
758 1: lis r3,exc_exit_restart_end@ha
759 addi r3,r3,exc_exit_restart_end@l
762 lis r4,exc_exit_restart@ha
763 addi r4,r4,exc_exit_restart@l
766 lis r3,fee_restarts@ha
768 lwz r5,fee_restarts@l(r3)
770 stw r5,fee_restarts@l(r3)
771 mr r12,r4 /* restart at exc_exit_restart */
780 /* aargh, a nonrecoverable interrupt, panic */
781 /* aargh, we don't know which trap this is */
782 /* but the 601 doesn't implement the RI bit, so assume it's OK */
786 END_FTR_SECTION_IFSET(CPU_FTR_601)
789 addi r3,r1,STACK_FRAME_OVERHEAD
791 ori r10,r10,MSR_KERNEL@l
792 bl transfer_to_handler_full
793 .long nonrecoverable_exception
794 .long ret_from_except
797 .globl ret_from_except_full
798 ret_from_except_full:
802 .globl ret_from_except
804 /* Hard-disable interrupts so that current_thread_info()->flags
805 * can't change between when we test it and when we return
806 * from the interrupt. */
807 /* Note: We don't bother telling lockdep about it */
808 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
809 SYNC /* Some chip revs have problems here... */
810 MTMSRD(r10) /* disable interrupts */
812 lwz r3,_MSR(r1) /* Returning to user mode? */
816 user_exc_return: /* r10 contains MSR_KERNEL here */
817 /* Check current_thread_info()->flags */
818 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
820 andi. r0,r9,_TIF_USER_WORK_MASK
824 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
825 /* Check whether this process has its own DBCR0 value. The internal
826 debug mode bit tells us that dbcr0 should be loaded. */
827 lwz r0,THREAD+THREAD_DBCR0(r2)
828 andis. r10,r0,DBCR0_IDM@h
832 #ifdef CONFIG_PREEMPT
835 /* N.B. the only way to get here is from the beq following ret_from_except. */
837 /* check current_thread_info->preempt_count */
838 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
839 lwz r0,TI_PREEMPT(r9)
840 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
843 andi. r0,r0,_TIF_NEED_RESCHED
845 andi. r0,r3,MSR_EE /* interrupts off? */
846 beq restore /* don't schedule if so */
847 #ifdef CONFIG_TRACE_IRQFLAGS
848 /* Lockdep thinks irqs are enabled, we need to call
849 * preempt_schedule_irq with IRQs off, so we inform lockdep
850 * now that we -did- turn them off already
852 bl trace_hardirqs_off
854 1: bl preempt_schedule_irq
855 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
857 andi. r0,r3,_TIF_NEED_RESCHED
859 #ifdef CONFIG_TRACE_IRQFLAGS
860 /* And now, to properly rebalance the above, we tell lockdep they
861 * are being turned back on, which will happen when we return
867 #endif /* CONFIG_PREEMPT */
869 /* interrupts are hard-disabled at this point */
872 BEGIN_MMU_FTR_SECTION
874 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
875 lis r4,icache_44x_need_flush@ha
876 lwz r5,icache_44x_need_flush@l(r4)
881 stw r6,icache_44x_need_flush@l(r4)
883 #endif /* CONFIG_44x */
886 #ifdef CONFIG_TRACE_IRQFLAGS
887 /* Lockdep doesn't know about the fact that IRQs are temporarily turned
888 * off in this assembly code while peeking at TI_FLAGS() and such. However
889 * we need to inform it if the exception turned interrupts off, and we
890 * are about to trun them back on.
892 * The problem here sadly is that we don't know whether the exceptions was
893 * one that turned interrupts off or not. So we always tell lockdep about
894 * turning them on here when we go back to wherever we came from with EE
895 * on, even if that may meen some redudant calls being tracked. Maybe later
896 * we could encode what the exception did somewhere or test the exception
897 * type in the pt_regs but that sounds overkill
902 * Since the ftrace irqsoff latency trace checks CALLER_ADDR1,
903 * which is the stack frame here, we need to force a stack frame
904 * in case we came from user space.
915 #endif /* CONFIG_TRACE_IRQFLAGS */
930 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
931 stwcx. r0,0,r1 /* to clear the reservation */
933 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
934 andi. r10,r9,MSR_RI /* check if this exception occurred */
935 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
943 * Once we put values in SRR0 and SRR1, we are in a state
944 * where exceptions are not recoverable, since taking an
945 * exception will trash SRR0 and SRR1. Therefore we clear the
946 * MSR:RI bit to indicate this. If we do take an exception,
947 * we can't return to the point of the exception but we
948 * can restart the exception exit path at the label
949 * exc_exit_restart below. -- paulus
951 LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI)
953 MTMSRD(r10) /* clear the RI bit */
954 .globl exc_exit_restart
962 .globl exc_exit_restart_end
963 exc_exit_restart_end:
967 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
969 * This is a bit different on 4xx/Book-E because it doesn't have
970 * the RI bit in the MSR.
971 * The TLB miss handler checks if we have interrupted
972 * the exception exit path and restarts it if so
973 * (well maybe one day it will... :).
980 .globl exc_exit_restart
989 .globl exc_exit_restart_end
990 exc_exit_restart_end:
993 b . /* prevent prefetch past rfi */
996 * Returning from a critical interrupt in user mode doesn't need
997 * to be any different from a normal exception. For a critical
998 * interrupt in the kernel, we just return (without checking for
999 * preemption) since the interrupt may have happened at some crucial
1000 * place (e.g. inside the TLB miss handler), and because we will be
1001 * running with r1 pointing into critical_stack, not the current
1002 * process's kernel stack (and therefore current_thread_info() will
1003 * give the wrong answer).
1004 * We have to restore various SPRs that may have been in use at the
1005 * time of the critical interrupt.
1009 #define PPC_40x_TURN_OFF_MSR_DR \
1010 /* avoid any possible TLB misses here by turning off MSR.DR, we \
1011 * assume the instructions here are mapped by a pinned TLB entry */ \
1017 #define PPC_40x_TURN_OFF_MSR_DR
1020 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
1023 andi. r3,r3,MSR_PR; \
1024 LOAD_MSR_KERNEL(r10,MSR_KERNEL); \
1025 bne user_exc_return; \
1028 REST_4GPRS(3, r1); \
1029 REST_2GPRS(7, r1); \
1032 mtspr SPRN_XER,r10; \
1034 PPC405_ERR77(0,r1); \
1035 stwcx. r0,0,r1; /* to clear the reservation */ \
1036 lwz r11,_LINK(r1); \
1040 PPC_40x_TURN_OFF_MSR_DR; \
1043 mtspr SPRN_DEAR,r9; \
1044 mtspr SPRN_ESR,r10; \
1047 mtspr exc_lvl_srr0,r11; \
1048 mtspr exc_lvl_srr1,r12; \
1050 lwz r12,GPR12(r1); \
1051 lwz r10,GPR10(r1); \
1052 lwz r11,GPR11(r1); \
1054 PPC405_ERR77_SYNC; \
1056 b .; /* prevent prefetch past exc_lvl_rfi */
1058 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
1059 lwz r9,_##exc_lvl_srr0(r1); \
1060 lwz r10,_##exc_lvl_srr1(r1); \
1061 mtspr SPRN_##exc_lvl_srr0,r9; \
1062 mtspr SPRN_##exc_lvl_srr1,r10;
1064 #if defined(CONFIG_PPC_BOOK3E_MMU)
1065 #ifdef CONFIG_PHYS_64BIT
1066 #define RESTORE_MAS7 \
1068 mtspr SPRN_MAS7,r11;
1070 #define RESTORE_MAS7
1071 #endif /* CONFIG_PHYS_64BIT */
1072 #define RESTORE_MMU_REGS \
1076 mtspr SPRN_MAS0,r9; \
1078 mtspr SPRN_MAS1,r10; \
1080 mtspr SPRN_MAS2,r11; \
1081 mtspr SPRN_MAS3,r9; \
1082 mtspr SPRN_MAS6,r10; \
1084 #elif defined(CONFIG_44x)
1085 #define RESTORE_MMU_REGS \
1087 mtspr SPRN_MMUCR,r9;
1089 #define RESTORE_MMU_REGS
1093 .globl ret_from_crit_exc
1095 mfspr r9,SPRN_SPRG_THREAD
1096 lis r10,saved_ksp_limit@ha;
1097 lwz r10,saved_ksp_limit@l(r10);
1099 stw r10,KSP_LIMIT(r9)
1100 lis r9,crit_srr0@ha;
1101 lwz r9,crit_srr0@l(r9);
1102 lis r10,crit_srr1@ha;
1103 lwz r10,crit_srr1@l(r10);
1105 mtspr SPRN_SRR1,r10;
1106 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1107 #endif /* CONFIG_40x */
1110 .globl ret_from_crit_exc
1112 mfspr r9,SPRN_SPRG_THREAD
1113 lwz r10,SAVED_KSP_LIMIT(r1)
1114 stw r10,KSP_LIMIT(r9)
1115 RESTORE_xSRR(SRR0,SRR1);
1117 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1119 .globl ret_from_debug_exc
1121 mfspr r9,SPRN_SPRG_THREAD
1122 lwz r10,SAVED_KSP_LIMIT(r1)
1123 stw r10,KSP_LIMIT(r9)
1124 lwz r9,THREAD_INFO-THREAD(r9)
1125 rlwinm r10,r1,0,0,(31-THREAD_SHIFT)
1126 lwz r10,TI_PREEMPT(r10)
1127 stw r10,TI_PREEMPT(r9)
1128 RESTORE_xSRR(SRR0,SRR1);
1129 RESTORE_xSRR(CSRR0,CSRR1);
1131 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
1133 .globl ret_from_mcheck_exc
1134 ret_from_mcheck_exc:
1135 mfspr r9,SPRN_SPRG_THREAD
1136 lwz r10,SAVED_KSP_LIMIT(r1)
1137 stw r10,KSP_LIMIT(r9)
1138 RESTORE_xSRR(SRR0,SRR1);
1139 RESTORE_xSRR(CSRR0,CSRR1);
1140 RESTORE_xSRR(DSRR0,DSRR1);
1142 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
1143 #endif /* CONFIG_BOOKE */
1146 * Load the DBCR0 value for a task that is being ptraced,
1147 * having first saved away the global DBCR0. Note that r0
1148 * has the dbcr0 value to set upon entry to this.
1151 mfmsr r10 /* first disable debug exceptions */
1152 rlwinm r10,r10,0,~MSR_DE
1155 mfspr r10,SPRN_DBCR0
1156 lis r11,global_dbcr0@ha
1157 addi r11,r11,global_dbcr0@l
1159 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
1170 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
1178 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
1180 do_work: /* r10 contains MSR_KERNEL here */
1181 andi. r0,r9,_TIF_NEED_RESCHED
1184 do_resched: /* r10 contains MSR_KERNEL here */
1185 /* Note: We don't need to inform lockdep that we are enabling
1186 * interrupts here. As far as it knows, they are already enabled
1190 MTMSRD(r10) /* hard-enable interrupts */
1193 /* Note: And we don't tell it we are disabling them again
1194 * neither. Those disable/enable cycles used to peek at
1195 * TI_FLAGS aren't advertised.
1197 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
1199 MTMSRD(r10) /* disable interrupts */
1200 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
1202 andi. r0,r9,_TIF_NEED_RESCHED
1204 andi. r0,r9,_TIF_USER_WORK_MASK
1206 do_user_signal: /* r10 contains MSR_KERNEL here */
1209 MTMSRD(r10) /* hard-enable interrupts */
1210 /* save r13-r31 in the exception frame, if not already done */
1217 2: addi r3,r1,STACK_FRAME_OVERHEAD
1224 * We come here when we are at the end of handling an exception
1225 * that occurred at a place where taking an exception will lose
1226 * state information, such as the contents of SRR0 and SRR1.
1229 lis r10,exc_exit_restart_end@ha
1230 addi r10,r10,exc_exit_restart_end@l
1233 lis r11,exc_exit_restart@ha
1234 addi r11,r11,exc_exit_restart@l
1237 lis r10,ee_restarts@ha
1238 lwz r12,ee_restarts@l(r10)
1240 stw r12,ee_restarts@l(r10)
1241 mr r12,r11 /* restart at exc_exit_restart */
1243 3: /* OK, we can't recover, kill this process */
1244 /* but the 601 doesn't implement the RI bit, so assume it's OK */
1247 END_FTR_SECTION_IFSET(CPU_FTR_601)
1254 4: addi r3,r1,STACK_FRAME_OVERHEAD
1255 bl nonrecoverable_exception
1256 /* shouldn't return */
1266 * PROM code for specific machines follows. Put it
1267 * here so it's easy to add arch-specific sections later.
1270 #ifdef CONFIG_PPC_RTAS
1272 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1273 * called with the MMU off.
1276 stwu r1,-INT_FRAME_SIZE(r1)
1278 stw r0,INT_FRAME_SIZE+4(r1)
1279 LOAD_REG_ADDR(r4, rtas)
1280 lis r6,1f@ha /* physical return address for rtas */
1284 lwz r8,RTASENTRY(r4)
1288 LOAD_MSR_KERNEL(r0,MSR_KERNEL)
1289 SYNC /* disable interrupts so SRR0/1 */
1290 MTMSRD(r0) /* don't get trashed */
1291 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1293 mtspr SPRN_SPRG_RTAS,r7
1298 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1299 lwz r9,8(r9) /* original msr value */
1301 addi r1,r1,INT_FRAME_SIZE
1303 mtspr SPRN_SPRG_RTAS,r0
1306 RFI /* return to caller */
1308 .globl machine_check_in_rtas
1309 machine_check_in_rtas:
1311 /* XXX load up BATs and panic */
1313 #endif /* CONFIG_PPC_RTAS */
1315 #ifdef CONFIG_FUNCTION_TRACER
1316 #ifdef CONFIG_DYNAMIC_FTRACE
1320 * It is required that _mcount on PPC32 must preserve the
1321 * link register. But we have r0 to play with. We use r0
1322 * to push the return address back to the caller of mcount
1323 * into the ctr register, restore the link register and
1324 * then jump back using the ctr register.
1332 _GLOBAL(ftrace_caller)
1334 /* r3 ends up with link register */
1335 subi r3, r3, MCOUNT_INSN_SIZE
1340 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1341 .globl ftrace_graph_call
1344 _GLOBAL(ftrace_graph_stub)
1346 MCOUNT_RESTORE_FRAME
1347 /* old link register ends up in ctr reg */
1355 subi r3, r3, MCOUNT_INSN_SIZE
1356 LOAD_REG_ADDR(r5, ftrace_trace_function)
1363 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1364 b ftrace_graph_caller
1366 MCOUNT_RESTORE_FRAME
1370 _GLOBAL(ftrace_stub)
1373 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1374 _GLOBAL(ftrace_graph_caller)
1375 /* load r4 with local address */
1377 subi r4, r4, MCOUNT_INSN_SIZE
1379 /* get the parent address */
1382 bl prepare_ftrace_return
1385 MCOUNT_RESTORE_FRAME
1386 /* old link register ends up in ctr reg */
1389 _GLOBAL(return_to_handler)
1390 /* need to save return values */
1397 bl ftrace_return_to_handler
1400 /* return value has real return address */
1408 /* Jump back to real return address */
1410 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1412 #endif /* CONFIG_MCOUNT */