1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
34 #include "radeon_drm.h"
35 #include "radeon_drv.h"
37 #define RADEON_FIFO_DEBUG 0
40 /* CP microcode (from ATI) */
41 static u32 R200_cp_microcode[][2] = {
42 { 0x21007000, 0000000000 },
43 { 0x20007000, 0000000000 },
44 { 0x000000ab, 0x00000004 },
45 { 0x000000af, 0x00000004 },
46 { 0x66544a49, 0000000000 },
47 { 0x49494174, 0000000000 },
48 { 0x54517d83, 0000000000 },
49 { 0x498d8b64, 0000000000 },
50 { 0x49494949, 0000000000 },
51 { 0x49da493c, 0000000000 },
52 { 0x49989898, 0000000000 },
53 { 0xd34949d5, 0000000000 },
54 { 0x9dc90e11, 0000000000 },
55 { 0xce9b9b9b, 0000000000 },
56 { 0x000f0000, 0x00000016 },
57 { 0x352e232c, 0000000000 },
58 { 0x00000013, 0x00000004 },
59 { 0x000f0000, 0x00000016 },
60 { 0x352e272c, 0000000000 },
61 { 0x000f0001, 0x00000016 },
62 { 0x3239362f, 0000000000 },
63 { 0x000077ef, 0x00000002 },
64 { 0x00061000, 0x00000002 },
65 { 0x00000020, 0x0000001a },
66 { 0x00004000, 0x0000001e },
67 { 0x00061000, 0x00000002 },
68 { 0x00000020, 0x0000001a },
69 { 0x00004000, 0x0000001e },
70 { 0x00061000, 0x00000002 },
71 { 0x00000020, 0x0000001a },
72 { 0x00004000, 0x0000001e },
73 { 0x00000016, 0x00000004 },
74 { 0x0003802a, 0x00000002 },
75 { 0x040067e0, 0x00000002 },
76 { 0x00000016, 0x00000004 },
77 { 0x000077e0, 0x00000002 },
78 { 0x00065000, 0x00000002 },
79 { 0x000037e1, 0x00000002 },
80 { 0x040067e1, 0x00000006 },
81 { 0x000077e0, 0x00000002 },
82 { 0x000077e1, 0x00000002 },
83 { 0x000077e1, 0x00000006 },
84 { 0xffffffff, 0000000000 },
85 { 0x10000000, 0000000000 },
86 { 0x0003802a, 0x00000002 },
87 { 0x040067e0, 0x00000006 },
88 { 0x00007675, 0x00000002 },
89 { 0x00007676, 0x00000002 },
90 { 0x00007677, 0x00000002 },
91 { 0x00007678, 0x00000006 },
92 { 0x0003802b, 0x00000002 },
93 { 0x04002676, 0x00000002 },
94 { 0x00007677, 0x00000002 },
95 { 0x00007678, 0x00000006 },
96 { 0x0000002e, 0x00000018 },
97 { 0x0000002e, 0x00000018 },
98 { 0000000000, 0x00000006 },
99 { 0x0000002f, 0x00000018 },
100 { 0x0000002f, 0x00000018 },
101 { 0000000000, 0x00000006 },
102 { 0x01605000, 0x00000002 },
103 { 0x00065000, 0x00000002 },
104 { 0x00098000, 0x00000002 },
105 { 0x00061000, 0x00000002 },
106 { 0x64c0603d, 0x00000004 },
107 { 0x00080000, 0x00000016 },
108 { 0000000000, 0000000000 },
109 { 0x0400251d, 0x00000002 },
110 { 0x00007580, 0x00000002 },
111 { 0x00067581, 0x00000002 },
112 { 0x04002580, 0x00000002 },
113 { 0x00067581, 0x00000002 },
114 { 0x00000046, 0x00000004 },
115 { 0x00005000, 0000000000 },
116 { 0x00061000, 0x00000002 },
117 { 0x0000750e, 0x00000002 },
118 { 0x00019000, 0x00000002 },
119 { 0x00011055, 0x00000014 },
120 { 0x00000055, 0x00000012 },
121 { 0x0400250f, 0x00000002 },
122 { 0x0000504a, 0x00000004 },
123 { 0x00007565, 0x00000002 },
124 { 0x00007566, 0x00000002 },
125 { 0x00000051, 0x00000004 },
126 { 0x01e655b4, 0x00000002 },
127 { 0x4401b0dc, 0x00000002 },
128 { 0x01c110dc, 0x00000002 },
129 { 0x2666705d, 0x00000018 },
130 { 0x040c2565, 0x00000002 },
131 { 0x0000005d, 0x00000018 },
132 { 0x04002564, 0x00000002 },
133 { 0x00007566, 0x00000002 },
134 { 0x00000054, 0x00000004 },
135 { 0x00401060, 0x00000008 },
136 { 0x00101000, 0x00000002 },
137 { 0x000d80ff, 0x00000002 },
138 { 0x00800063, 0x00000008 },
139 { 0x000f9000, 0x00000002 },
140 { 0x000e00ff, 0x00000002 },
141 { 0000000000, 0x00000006 },
142 { 0x00000080, 0x00000018 },
143 { 0x00000054, 0x00000004 },
144 { 0x00007576, 0x00000002 },
145 { 0x00065000, 0x00000002 },
146 { 0x00009000, 0x00000002 },
147 { 0x00041000, 0x00000002 },
148 { 0x0c00350e, 0x00000002 },
149 { 0x00049000, 0x00000002 },
150 { 0x00051000, 0x00000002 },
151 { 0x01e785f8, 0x00000002 },
152 { 0x00200000, 0x00000002 },
153 { 0x00600073, 0x0000000c },
154 { 0x00007563, 0x00000002 },
155 { 0x006075f0, 0x00000021 },
156 { 0x20007068, 0x00000004 },
157 { 0x00005068, 0x00000004 },
158 { 0x00007576, 0x00000002 },
159 { 0x00007577, 0x00000002 },
160 { 0x0000750e, 0x00000002 },
161 { 0x0000750f, 0x00000002 },
162 { 0x00a05000, 0x00000002 },
163 { 0x00600076, 0x0000000c },
164 { 0x006075f0, 0x00000021 },
165 { 0x000075f8, 0x00000002 },
166 { 0x00000076, 0x00000004 },
167 { 0x000a750e, 0x00000002 },
168 { 0x0020750f, 0x00000002 },
169 { 0x00600079, 0x00000004 },
170 { 0x00007570, 0x00000002 },
171 { 0x00007571, 0x00000002 },
172 { 0x00007572, 0x00000006 },
173 { 0x00005000, 0x00000002 },
174 { 0x00a05000, 0x00000002 },
175 { 0x00007568, 0x00000002 },
176 { 0x00061000, 0x00000002 },
177 { 0x00000084, 0x0000000c },
178 { 0x00058000, 0x00000002 },
179 { 0x0c607562, 0x00000002 },
180 { 0x00000086, 0x00000004 },
181 { 0x00600085, 0x00000004 },
182 { 0x400070dd, 0000000000 },
183 { 0x000380dd, 0x00000002 },
184 { 0x00000093, 0x0000001c },
185 { 0x00065095, 0x00000018 },
186 { 0x040025bb, 0x00000002 },
187 { 0x00061096, 0x00000018 },
188 { 0x040075bc, 0000000000 },
189 { 0x000075bb, 0x00000002 },
190 { 0x000075bc, 0000000000 },
191 { 0x00090000, 0x00000006 },
192 { 0x00090000, 0x00000002 },
193 { 0x000d8002, 0x00000006 },
194 { 0x00005000, 0x00000002 },
195 { 0x00007821, 0x00000002 },
196 { 0x00007800, 0000000000 },
197 { 0x00007821, 0x00000002 },
198 { 0x00007800, 0000000000 },
199 { 0x01665000, 0x00000002 },
200 { 0x000a0000, 0x00000002 },
201 { 0x000671cc, 0x00000002 },
202 { 0x0286f1cd, 0x00000002 },
203 { 0x000000a3, 0x00000010 },
204 { 0x21007000, 0000000000 },
205 { 0x000000aa, 0x0000001c },
206 { 0x00065000, 0x00000002 },
207 { 0x000a0000, 0x00000002 },
208 { 0x00061000, 0x00000002 },
209 { 0x000b0000, 0x00000002 },
210 { 0x38067000, 0x00000002 },
211 { 0x000a00a6, 0x00000004 },
212 { 0x20007000, 0000000000 },
213 { 0x01200000, 0x00000002 },
214 { 0x20077000, 0x00000002 },
215 { 0x01200000, 0x00000002 },
216 { 0x20007000, 0000000000 },
217 { 0x00061000, 0x00000002 },
218 { 0x0120751b, 0x00000002 },
219 { 0x8040750a, 0x00000002 },
220 { 0x8040750b, 0x00000002 },
221 { 0x00110000, 0x00000002 },
222 { 0x000380dd, 0x00000002 },
223 { 0x000000bd, 0x0000001c },
224 { 0x00061096, 0x00000018 },
225 { 0x844075bd, 0x00000002 },
226 { 0x00061095, 0x00000018 },
227 { 0x840075bb, 0x00000002 },
228 { 0x00061096, 0x00000018 },
229 { 0x844075bc, 0x00000002 },
230 { 0x000000c0, 0x00000004 },
231 { 0x804075bd, 0x00000002 },
232 { 0x800075bb, 0x00000002 },
233 { 0x804075bc, 0x00000002 },
234 { 0x00108000, 0x00000002 },
235 { 0x01400000, 0x00000002 },
236 { 0x006000c4, 0x0000000c },
237 { 0x20c07000, 0x00000020 },
238 { 0x000000c6, 0x00000012 },
239 { 0x00800000, 0x00000006 },
240 { 0x0080751d, 0x00000006 },
241 { 0x000025bb, 0x00000002 },
242 { 0x000040c0, 0x00000004 },
243 { 0x0000775c, 0x00000002 },
244 { 0x00a05000, 0x00000002 },
245 { 0x00661000, 0x00000002 },
246 { 0x0460275d, 0x00000020 },
247 { 0x00004000, 0000000000 },
248 { 0x00007999, 0x00000002 },
249 { 0x00a05000, 0x00000002 },
250 { 0x00661000, 0x00000002 },
251 { 0x0460299b, 0x00000020 },
252 { 0x00004000, 0000000000 },
253 { 0x01e00830, 0x00000002 },
254 { 0x21007000, 0000000000 },
255 { 0x00005000, 0x00000002 },
256 { 0x00038042, 0x00000002 },
257 { 0x040025e0, 0x00000002 },
258 { 0x000075e1, 0000000000 },
259 { 0x00000001, 0000000000 },
260 { 0x000380d9, 0x00000002 },
261 { 0x04007394, 0000000000 },
262 { 0000000000, 0000000000 },
263 { 0000000000, 0000000000 },
264 { 0000000000, 0000000000 },
265 { 0000000000, 0000000000 },
266 { 0000000000, 0000000000 },
267 { 0000000000, 0000000000 },
268 { 0000000000, 0000000000 },
269 { 0000000000, 0000000000 },
270 { 0000000000, 0000000000 },
271 { 0000000000, 0000000000 },
272 { 0000000000, 0000000000 },
273 { 0000000000, 0000000000 },
274 { 0000000000, 0000000000 },
275 { 0000000000, 0000000000 },
276 { 0000000000, 0000000000 },
277 { 0000000000, 0000000000 },
278 { 0000000000, 0000000000 },
279 { 0000000000, 0000000000 },
280 { 0000000000, 0000000000 },
281 { 0000000000, 0000000000 },
282 { 0000000000, 0000000000 },
283 { 0000000000, 0000000000 },
284 { 0000000000, 0000000000 },
285 { 0000000000, 0000000000 },
286 { 0000000000, 0000000000 },
287 { 0000000000, 0000000000 },
288 { 0000000000, 0000000000 },
289 { 0000000000, 0000000000 },
290 { 0000000000, 0000000000 },
291 { 0000000000, 0000000000 },
292 { 0000000000, 0000000000 },
293 { 0000000000, 0000000000 },
294 { 0000000000, 0000000000 },
295 { 0000000000, 0000000000 },
296 { 0000000000, 0000000000 },
297 { 0000000000, 0000000000 },
301 static u32 radeon_cp_microcode[][2] = {
302 { 0x21007000, 0000000000 },
303 { 0x20007000, 0000000000 },
304 { 0x000000b4, 0x00000004 },
305 { 0x000000b8, 0x00000004 },
306 { 0x6f5b4d4c, 0000000000 },
307 { 0x4c4c427f, 0000000000 },
308 { 0x5b568a92, 0000000000 },
309 { 0x4ca09c6d, 0000000000 },
310 { 0xad4c4c4c, 0000000000 },
311 { 0x4ce1af3d, 0000000000 },
312 { 0xd8afafaf, 0000000000 },
313 { 0xd64c4cdc, 0000000000 },
314 { 0x4cd10d10, 0000000000 },
315 { 0x000f0000, 0x00000016 },
316 { 0x362f242d, 0000000000 },
317 { 0x00000012, 0x00000004 },
318 { 0x000f0000, 0x00000016 },
319 { 0x362f282d, 0000000000 },
320 { 0x000380e7, 0x00000002 },
321 { 0x04002c97, 0x00000002 },
322 { 0x000f0001, 0x00000016 },
323 { 0x333a3730, 0000000000 },
324 { 0x000077ef, 0x00000002 },
325 { 0x00061000, 0x00000002 },
326 { 0x00000021, 0x0000001a },
327 { 0x00004000, 0x0000001e },
328 { 0x00061000, 0x00000002 },
329 { 0x00000021, 0x0000001a },
330 { 0x00004000, 0x0000001e },
331 { 0x00061000, 0x00000002 },
332 { 0x00000021, 0x0000001a },
333 { 0x00004000, 0x0000001e },
334 { 0x00000017, 0x00000004 },
335 { 0x0003802b, 0x00000002 },
336 { 0x040067e0, 0x00000002 },
337 { 0x00000017, 0x00000004 },
338 { 0x000077e0, 0x00000002 },
339 { 0x00065000, 0x00000002 },
340 { 0x000037e1, 0x00000002 },
341 { 0x040067e1, 0x00000006 },
342 { 0x000077e0, 0x00000002 },
343 { 0x000077e1, 0x00000002 },
344 { 0x000077e1, 0x00000006 },
345 { 0xffffffff, 0000000000 },
346 { 0x10000000, 0000000000 },
347 { 0x0003802b, 0x00000002 },
348 { 0x040067e0, 0x00000006 },
349 { 0x00007675, 0x00000002 },
350 { 0x00007676, 0x00000002 },
351 { 0x00007677, 0x00000002 },
352 { 0x00007678, 0x00000006 },
353 { 0x0003802c, 0x00000002 },
354 { 0x04002676, 0x00000002 },
355 { 0x00007677, 0x00000002 },
356 { 0x00007678, 0x00000006 },
357 { 0x0000002f, 0x00000018 },
358 { 0x0000002f, 0x00000018 },
359 { 0000000000, 0x00000006 },
360 { 0x00000030, 0x00000018 },
361 { 0x00000030, 0x00000018 },
362 { 0000000000, 0x00000006 },
363 { 0x01605000, 0x00000002 },
364 { 0x00065000, 0x00000002 },
365 { 0x00098000, 0x00000002 },
366 { 0x00061000, 0x00000002 },
367 { 0x64c0603e, 0x00000004 },
368 { 0x000380e6, 0x00000002 },
369 { 0x040025c5, 0x00000002 },
370 { 0x00080000, 0x00000016 },
371 { 0000000000, 0000000000 },
372 { 0x0400251d, 0x00000002 },
373 { 0x00007580, 0x00000002 },
374 { 0x00067581, 0x00000002 },
375 { 0x04002580, 0x00000002 },
376 { 0x00067581, 0x00000002 },
377 { 0x00000049, 0x00000004 },
378 { 0x00005000, 0000000000 },
379 { 0x000380e6, 0x00000002 },
380 { 0x040025c5, 0x00000002 },
381 { 0x00061000, 0x00000002 },
382 { 0x0000750e, 0x00000002 },
383 { 0x00019000, 0x00000002 },
384 { 0x00011055, 0x00000014 },
385 { 0x00000055, 0x00000012 },
386 { 0x0400250f, 0x00000002 },
387 { 0x0000504f, 0x00000004 },
388 { 0x000380e6, 0x00000002 },
389 { 0x040025c5, 0x00000002 },
390 { 0x00007565, 0x00000002 },
391 { 0x00007566, 0x00000002 },
392 { 0x00000058, 0x00000004 },
393 { 0x000380e6, 0x00000002 },
394 { 0x040025c5, 0x00000002 },
395 { 0x01e655b4, 0x00000002 },
396 { 0x4401b0e4, 0x00000002 },
397 { 0x01c110e4, 0x00000002 },
398 { 0x26667066, 0x00000018 },
399 { 0x040c2565, 0x00000002 },
400 { 0x00000066, 0x00000018 },
401 { 0x04002564, 0x00000002 },
402 { 0x00007566, 0x00000002 },
403 { 0x0000005d, 0x00000004 },
404 { 0x00401069, 0x00000008 },
405 { 0x00101000, 0x00000002 },
406 { 0x000d80ff, 0x00000002 },
407 { 0x0080006c, 0x00000008 },
408 { 0x000f9000, 0x00000002 },
409 { 0x000e00ff, 0x00000002 },
410 { 0000000000, 0x00000006 },
411 { 0x0000008f, 0x00000018 },
412 { 0x0000005b, 0x00000004 },
413 { 0x000380e6, 0x00000002 },
414 { 0x040025c5, 0x00000002 },
415 { 0x00007576, 0x00000002 },
416 { 0x00065000, 0x00000002 },
417 { 0x00009000, 0x00000002 },
418 { 0x00041000, 0x00000002 },
419 { 0x0c00350e, 0x00000002 },
420 { 0x00049000, 0x00000002 },
421 { 0x00051000, 0x00000002 },
422 { 0x01e785f8, 0x00000002 },
423 { 0x00200000, 0x00000002 },
424 { 0x0060007e, 0x0000000c },
425 { 0x00007563, 0x00000002 },
426 { 0x006075f0, 0x00000021 },
427 { 0x20007073, 0x00000004 },
428 { 0x00005073, 0x00000004 },
429 { 0x000380e6, 0x00000002 },
430 { 0x040025c5, 0x00000002 },
431 { 0x00007576, 0x00000002 },
432 { 0x00007577, 0x00000002 },
433 { 0x0000750e, 0x00000002 },
434 { 0x0000750f, 0x00000002 },
435 { 0x00a05000, 0x00000002 },
436 { 0x00600083, 0x0000000c },
437 { 0x006075f0, 0x00000021 },
438 { 0x000075f8, 0x00000002 },
439 { 0x00000083, 0x00000004 },
440 { 0x000a750e, 0x00000002 },
441 { 0x000380e6, 0x00000002 },
442 { 0x040025c5, 0x00000002 },
443 { 0x0020750f, 0x00000002 },
444 { 0x00600086, 0x00000004 },
445 { 0x00007570, 0x00000002 },
446 { 0x00007571, 0x00000002 },
447 { 0x00007572, 0x00000006 },
448 { 0x000380e6, 0x00000002 },
449 { 0x040025c5, 0x00000002 },
450 { 0x00005000, 0x00000002 },
451 { 0x00a05000, 0x00000002 },
452 { 0x00007568, 0x00000002 },
453 { 0x00061000, 0x00000002 },
454 { 0x00000095, 0x0000000c },
455 { 0x00058000, 0x00000002 },
456 { 0x0c607562, 0x00000002 },
457 { 0x00000097, 0x00000004 },
458 { 0x000380e6, 0x00000002 },
459 { 0x040025c5, 0x00000002 },
460 { 0x00600096, 0x00000004 },
461 { 0x400070e5, 0000000000 },
462 { 0x000380e6, 0x00000002 },
463 { 0x040025c5, 0x00000002 },
464 { 0x000380e5, 0x00000002 },
465 { 0x000000a8, 0x0000001c },
466 { 0x000650aa, 0x00000018 },
467 { 0x040025bb, 0x00000002 },
468 { 0x000610ab, 0x00000018 },
469 { 0x040075bc, 0000000000 },
470 { 0x000075bb, 0x00000002 },
471 { 0x000075bc, 0000000000 },
472 { 0x00090000, 0x00000006 },
473 { 0x00090000, 0x00000002 },
474 { 0x000d8002, 0x00000006 },
475 { 0x00007832, 0x00000002 },
476 { 0x00005000, 0x00000002 },
477 { 0x000380e7, 0x00000002 },
478 { 0x04002c97, 0x00000002 },
479 { 0x00007820, 0x00000002 },
480 { 0x00007821, 0x00000002 },
481 { 0x00007800, 0000000000 },
482 { 0x01200000, 0x00000002 },
483 { 0x20077000, 0x00000002 },
484 { 0x01200000, 0x00000002 },
485 { 0x20007000, 0x00000002 },
486 { 0x00061000, 0x00000002 },
487 { 0x0120751b, 0x00000002 },
488 { 0x8040750a, 0x00000002 },
489 { 0x8040750b, 0x00000002 },
490 { 0x00110000, 0x00000002 },
491 { 0x000380e5, 0x00000002 },
492 { 0x000000c6, 0x0000001c },
493 { 0x000610ab, 0x00000018 },
494 { 0x844075bd, 0x00000002 },
495 { 0x000610aa, 0x00000018 },
496 { 0x840075bb, 0x00000002 },
497 { 0x000610ab, 0x00000018 },
498 { 0x844075bc, 0x00000002 },
499 { 0x000000c9, 0x00000004 },
500 { 0x804075bd, 0x00000002 },
501 { 0x800075bb, 0x00000002 },
502 { 0x804075bc, 0x00000002 },
503 { 0x00108000, 0x00000002 },
504 { 0x01400000, 0x00000002 },
505 { 0x006000cd, 0x0000000c },
506 { 0x20c07000, 0x00000020 },
507 { 0x000000cf, 0x00000012 },
508 { 0x00800000, 0x00000006 },
509 { 0x0080751d, 0x00000006 },
510 { 0000000000, 0000000000 },
511 { 0x0000775c, 0x00000002 },
512 { 0x00a05000, 0x00000002 },
513 { 0x00661000, 0x00000002 },
514 { 0x0460275d, 0x00000020 },
515 { 0x00004000, 0000000000 },
516 { 0x01e00830, 0x00000002 },
517 { 0x21007000, 0000000000 },
518 { 0x6464614d, 0000000000 },
519 { 0x69687420, 0000000000 },
520 { 0x00000073, 0000000000 },
521 { 0000000000, 0000000000 },
522 { 0x00005000, 0x00000002 },
523 { 0x000380d0, 0x00000002 },
524 { 0x040025e0, 0x00000002 },
525 { 0x000075e1, 0000000000 },
526 { 0x00000001, 0000000000 },
527 { 0x000380e0, 0x00000002 },
528 { 0x04002394, 0x00000002 },
529 { 0x00005000, 0000000000 },
530 { 0000000000, 0000000000 },
531 { 0000000000, 0000000000 },
532 { 0x00000008, 0000000000 },
533 { 0x00000004, 0000000000 },
534 { 0000000000, 0000000000 },
535 { 0000000000, 0000000000 },
536 { 0000000000, 0000000000 },
537 { 0000000000, 0000000000 },
538 { 0000000000, 0000000000 },
539 { 0000000000, 0000000000 },
540 { 0000000000, 0000000000 },
541 { 0000000000, 0000000000 },
542 { 0000000000, 0000000000 },
543 { 0000000000, 0000000000 },
544 { 0000000000, 0000000000 },
545 { 0000000000, 0000000000 },
546 { 0000000000, 0000000000 },
547 { 0000000000, 0000000000 },
548 { 0000000000, 0000000000 },
549 { 0000000000, 0000000000 },
550 { 0000000000, 0000000000 },
551 { 0000000000, 0000000000 },
552 { 0000000000, 0000000000 },
553 { 0000000000, 0000000000 },
554 { 0000000000, 0000000000 },
555 { 0000000000, 0000000000 },
556 { 0000000000, 0000000000 },
557 { 0000000000, 0000000000 },
561 int RADEON_READ_PLL(drm_device_t *dev, int addr)
563 drm_radeon_private_t *dev_priv = dev->dev_private;
565 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
566 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
569 #if RADEON_FIFO_DEBUG
570 static void radeon_status( drm_radeon_private_t *dev_priv )
572 printk( "%s:\n", __FUNCTION__ );
573 printk( "RBBM_STATUS = 0x%08x\n",
574 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
575 printk( "CP_RB_RTPR = 0x%08x\n",
576 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
577 printk( "CP_RB_WTPR = 0x%08x\n",
578 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
579 printk( "AIC_CNTL = 0x%08x\n",
580 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
581 printk( "AIC_STAT = 0x%08x\n",
582 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
583 printk( "AIC_PT_BASE = 0x%08x\n",
584 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
585 printk( "TLB_ADDR = 0x%08x\n",
586 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
587 printk( "TLB_DATA = 0x%08x\n",
588 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
593 /* ================================================================
594 * Engine, FIFO control
597 static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
602 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
604 tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
605 tmp |= RADEON_RB2D_DC_FLUSH_ALL;
606 RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
608 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
609 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
610 & RADEON_RB2D_DC_BUSY) ) {
616 #if RADEON_FIFO_DEBUG
617 DRM_ERROR( "failed!\n" );
618 radeon_status( dev_priv );
620 return DRM_ERR(EBUSY);
623 static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
628 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
630 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
631 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
632 & RADEON_RBBM_FIFOCNT_MASK );
633 if ( slots >= entries ) return 0;
637 #if RADEON_FIFO_DEBUG
638 DRM_ERROR( "failed!\n" );
639 radeon_status( dev_priv );
641 return DRM_ERR(EBUSY);
644 static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
648 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
650 ret = radeon_do_wait_for_fifo( dev_priv, 64 );
651 if ( ret ) return ret;
653 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
654 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
655 & RADEON_RBBM_ACTIVE) ) {
656 radeon_do_pixcache_flush( dev_priv );
662 #if RADEON_FIFO_DEBUG
663 DRM_ERROR( "failed!\n" );
664 radeon_status( dev_priv );
666 return DRM_ERR(EBUSY);
670 /* ================================================================
671 * CP control, initialization
674 /* Load the microcode for the CP */
675 static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
680 radeon_do_wait_for_idle( dev_priv );
682 RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
684 if (dev_priv->is_r200)
686 DRM_INFO("Loading R200 Microcode\n");
687 for ( i = 0 ; i < 256 ; i++ )
689 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
690 R200_cp_microcode[i][1] );
691 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
692 R200_cp_microcode[i][0] );
697 for ( i = 0 ; i < 256 ; i++ ) {
698 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
699 radeon_cp_microcode[i][1] );
700 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
701 radeon_cp_microcode[i][0] );
706 /* Flush any pending commands to the CP. This should only be used just
707 * prior to a wait for idle, as it informs the engine that the command
710 static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
716 tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
717 RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
721 /* Wait for the CP to go idle.
723 int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
730 RADEON_PURGE_CACHE();
731 RADEON_PURGE_ZCACHE();
732 RADEON_WAIT_UNTIL_IDLE();
737 return radeon_do_wait_for_idle( dev_priv );
740 /* Start the Command Processor.
742 static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
747 radeon_do_wait_for_idle( dev_priv );
749 RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
751 dev_priv->cp_running = 1;
755 RADEON_PURGE_CACHE();
756 RADEON_PURGE_ZCACHE();
757 RADEON_WAIT_UNTIL_IDLE();
763 /* Reset the Command Processor. This will not flush any pending
764 * commands, so you must wait for the CP command stream to complete
765 * before calling this routine.
767 static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
772 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
773 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
774 SET_RING_HEAD( dev_priv, cur_read_ptr );
775 dev_priv->ring.tail = cur_read_ptr;
778 /* Stop the Command Processor. This will not flush any pending
779 * commands, so you must flush the command stream and wait for the CP
780 * to go idle before calling this routine.
782 static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
786 RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
788 dev_priv->cp_running = 0;
791 /* Reset the engine. This will stop the CP if it is running.
793 static int radeon_do_engine_reset( drm_device_t *dev )
795 drm_radeon_private_t *dev_priv = dev->dev_private;
796 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
799 radeon_do_pixcache_flush( dev_priv );
801 clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
802 mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
804 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
805 RADEON_FORCEON_MCLKA |
806 RADEON_FORCEON_MCLKB |
807 RADEON_FORCEON_YCLKA |
808 RADEON_FORCEON_YCLKB |
810 RADEON_FORCEON_AIC ) );
812 rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
814 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
815 RADEON_SOFT_RESET_CP |
816 RADEON_SOFT_RESET_HI |
817 RADEON_SOFT_RESET_SE |
818 RADEON_SOFT_RESET_RE |
819 RADEON_SOFT_RESET_PP |
820 RADEON_SOFT_RESET_E2 |
821 RADEON_SOFT_RESET_RB ) );
822 RADEON_READ( RADEON_RBBM_SOFT_RESET );
823 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
824 ~( RADEON_SOFT_RESET_CP |
825 RADEON_SOFT_RESET_HI |
826 RADEON_SOFT_RESET_SE |
827 RADEON_SOFT_RESET_RE |
828 RADEON_SOFT_RESET_PP |
829 RADEON_SOFT_RESET_E2 |
830 RADEON_SOFT_RESET_RB ) ) );
831 RADEON_READ( RADEON_RBBM_SOFT_RESET );
834 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
835 RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
836 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset );
838 /* Reset the CP ring */
839 radeon_do_cp_reset( dev_priv );
841 /* The CP is no longer running after an engine reset */
842 dev_priv->cp_running = 0;
844 /* Reset any pending vertex, indirect buffers */
845 radeon_freelist_reset( dev );
850 static void radeon_cp_init_ring_buffer( drm_device_t *dev,
851 drm_radeon_private_t *dev_priv )
853 u32 ring_start, cur_read_ptr;
856 /* Initialize the memory controller */
857 RADEON_WRITE( RADEON_MC_FB_LOCATION,
858 (dev_priv->agp_vm_start - 1) & 0xffff0000 );
860 if ( !dev_priv->is_pci ) {
861 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
862 (((dev_priv->agp_vm_start - 1 +
863 dev_priv->agp_size) & 0xffff0000) |
864 (dev_priv->agp_vm_start >> 16)) );
867 #if __REALLY_HAVE_AGP
868 if ( !dev_priv->is_pci )
869 ring_start = (dev_priv->cp_ring->offset
871 + dev_priv->agp_vm_start);
874 ring_start = (dev_priv->cp_ring->offset
876 + dev_priv->agp_vm_start);
878 RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
880 /* Set the write pointer delay */
881 RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
883 /* Initialize the ring buffer's read and write pointers */
884 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
885 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
886 SET_RING_HEAD( dev_priv, cur_read_ptr );
887 dev_priv->ring.tail = cur_read_ptr;
889 #if __REALLY_HAVE_AGP
890 if ( !dev_priv->is_pci ) {
891 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
892 dev_priv->ring_rptr->offset
894 + dev_priv->agp_vm_start);
898 drm_sg_mem_t *entry = dev->sg;
899 unsigned long tmp_ofs, page_ofs;
901 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
902 page_ofs = tmp_ofs >> PAGE_SHIFT;
904 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
905 entry->busaddr[page_ofs]);
906 DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n",
907 entry->busaddr[page_ofs],
908 entry->handle + tmp_ofs );
911 /* Initialize the scratch register pointer. This will cause
912 * the scratch register values to be written out to memory
913 * whenever they are updated.
915 * We simply put this behind the ring read pointer, this works
916 * with PCI GART as well as (whatever kind of) AGP GART
918 RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
919 + RADEON_SCRATCH_REG_OFFSET );
921 dev_priv->scratch = ((__volatile__ u32 *)
922 dev_priv->ring_rptr->handle +
923 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
925 RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
927 /* Writeback doesn't seem to work everywhere, test it first */
928 DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
929 RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
931 for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
932 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
937 if ( tmp < dev_priv->usec_timeout ) {
938 dev_priv->writeback_works = 1;
939 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
941 dev_priv->writeback_works = 0;
942 DRM_DEBUG( "writeback test failed\n" );
945 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
946 RADEON_WRITE( RADEON_LAST_FRAME_REG,
947 dev_priv->sarea_priv->last_frame );
949 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
950 RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
951 dev_priv->sarea_priv->last_dispatch );
953 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
954 RADEON_WRITE( RADEON_LAST_CLEAR_REG,
955 dev_priv->sarea_priv->last_clear );
957 /* Set ring buffer size */
959 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
961 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
964 radeon_do_wait_for_idle( dev_priv );
966 /* Turn on bus mastering */
967 tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
968 RADEON_WRITE( RADEON_BUS_CNTL, tmp );
970 /* Sync everything up */
971 RADEON_WRITE( RADEON_ISYNC_CNTL,
972 (RADEON_ISYNC_ANY2D_IDLE3D |
973 RADEON_ISYNC_ANY3D_IDLE2D |
974 RADEON_ISYNC_WAIT_IDLEGUI |
975 RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
978 static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
980 drm_radeon_private_t *dev_priv;
984 dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
985 if ( dev_priv == NULL )
986 return DRM_ERR(ENOMEM);
988 memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
990 dev_priv->is_pci = init->is_pci;
992 if ( dev_priv->is_pci && !dev->sg ) {
993 DRM_ERROR( "PCI GART memory not allocated!\n" );
994 dev->dev_private = (void *)dev_priv;
995 radeon_do_cleanup_cp(dev);
996 return DRM_ERR(EINVAL);
999 dev_priv->usec_timeout = init->usec_timeout;
1000 if ( dev_priv->usec_timeout < 1 ||
1001 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
1002 DRM_DEBUG( "TIMEOUT problem!\n" );
1003 dev->dev_private = (void *)dev_priv;
1004 radeon_do_cleanup_cp(dev);
1005 return DRM_ERR(EINVAL);
1008 dev_priv->is_r200 = (init->func == RADEON_INIT_R200_CP);
1009 dev_priv->do_boxes = 0;
1010 dev_priv->cp_mode = init->cp_mode;
1012 /* We don't support anything other than bus-mastering ring mode,
1013 * but the ring can be in either AGP or PCI space for the ring
1016 if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1017 ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1018 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1019 dev->dev_private = (void *)dev_priv;
1020 radeon_do_cleanup_cp(dev);
1021 return DRM_ERR(EINVAL);
1024 switch ( init->fb_bpp ) {
1026 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1030 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1033 dev_priv->front_offset = init->front_offset;
1034 dev_priv->front_pitch = init->front_pitch;
1035 dev_priv->back_offset = init->back_offset;
1036 dev_priv->back_pitch = init->back_pitch;
1038 switch ( init->depth_bpp ) {
1040 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1044 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1047 dev_priv->depth_offset = init->depth_offset;
1048 dev_priv->depth_pitch = init->depth_pitch;
1050 dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1051 (dev_priv->front_offset >> 10));
1052 dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1053 (dev_priv->back_offset >> 10));
1054 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1055 (dev_priv->depth_offset >> 10));
1057 /* Hardware state for depth clears. Remove this if/when we no
1058 * longer clear the depth buffer with a 3D rectangle. Hard-code
1059 * all values to prevent unwanted 3D state from slipping through
1060 * and screwing with the clear operation.
1062 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1063 (dev_priv->color_fmt << 10) |
1066 dev_priv->depth_clear.rb3d_zstencilcntl =
1067 (dev_priv->depth_fmt |
1068 RADEON_Z_TEST_ALWAYS |
1069 RADEON_STENCIL_TEST_ALWAYS |
1070 RADEON_STENCIL_S_FAIL_REPLACE |
1071 RADEON_STENCIL_ZPASS_REPLACE |
1072 RADEON_STENCIL_ZFAIL_REPLACE |
1073 RADEON_Z_WRITE_ENABLE);
1075 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1076 RADEON_BFACE_SOLID |
1077 RADEON_FFACE_SOLID |
1078 RADEON_FLAT_SHADE_VTX_LAST |
1079 RADEON_DIFFUSE_SHADE_FLAT |
1080 RADEON_ALPHA_SHADE_FLAT |
1081 RADEON_SPECULAR_SHADE_FLAT |
1082 RADEON_FOG_SHADE_FLAT |
1083 RADEON_VTX_PIX_CENTER_OGL |
1084 RADEON_ROUND_MODE_TRUNC |
1085 RADEON_ROUND_PREC_8TH_PIX);
1089 dev_priv->fb_offset = init->fb_offset;
1090 dev_priv->mmio_offset = init->mmio_offset;
1091 dev_priv->ring_offset = init->ring_offset;
1092 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1093 dev_priv->buffers_offset = init->buffers_offset;
1094 dev_priv->agp_textures_offset = init->agp_textures_offset;
1096 if(!dev_priv->sarea) {
1097 DRM_ERROR("could not find sarea!\n");
1098 dev->dev_private = (void *)dev_priv;
1099 radeon_do_cleanup_cp(dev);
1100 return DRM_ERR(EINVAL);
1103 DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
1105 DRM_ERROR("could not find framebuffer!\n");
1106 dev->dev_private = (void *)dev_priv;
1107 radeon_do_cleanup_cp(dev);
1108 return DRM_ERR(EINVAL);
1110 DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
1111 if(!dev_priv->mmio) {
1112 DRM_ERROR("could not find mmio region!\n");
1113 dev->dev_private = (void *)dev_priv;
1114 radeon_do_cleanup_cp(dev);
1115 return DRM_ERR(EINVAL);
1117 DRM_FIND_MAP( dev_priv->cp_ring, init->ring_offset );
1118 if(!dev_priv->cp_ring) {
1119 DRM_ERROR("could not find cp ring region!\n");
1120 dev->dev_private = (void *)dev_priv;
1121 radeon_do_cleanup_cp(dev);
1122 return DRM_ERR(EINVAL);
1124 DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
1125 if(!dev_priv->ring_rptr) {
1126 DRM_ERROR("could not find ring read pointer!\n");
1127 dev->dev_private = (void *)dev_priv;
1128 radeon_do_cleanup_cp(dev);
1129 return DRM_ERR(EINVAL);
1131 DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
1132 if(!dev_priv->buffers) {
1133 DRM_ERROR("could not find dma buffer region!\n");
1134 dev->dev_private = (void *)dev_priv;
1135 radeon_do_cleanup_cp(dev);
1136 return DRM_ERR(EINVAL);
1139 if ( !dev_priv->is_pci ) {
1140 DRM_FIND_MAP( dev_priv->agp_textures,
1141 init->agp_textures_offset );
1142 if(!dev_priv->agp_textures) {
1143 DRM_ERROR("could not find agp texture region!\n");
1144 dev->dev_private = (void *)dev_priv;
1145 radeon_do_cleanup_cp(dev);
1146 return DRM_ERR(EINVAL);
1150 dev_priv->sarea_priv =
1151 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1152 init->sarea_priv_offset);
1154 if ( !dev_priv->is_pci ) {
1155 DRM_IOREMAP( dev_priv->cp_ring );
1156 DRM_IOREMAP( dev_priv->ring_rptr );
1157 DRM_IOREMAP( dev_priv->buffers );
1158 if(!dev_priv->cp_ring->handle ||
1159 !dev_priv->ring_rptr->handle ||
1160 !dev_priv->buffers->handle) {
1161 DRM_ERROR("could not find ioremap agp regions!\n");
1162 dev->dev_private = (void *)dev_priv;
1163 radeon_do_cleanup_cp(dev);
1164 return DRM_ERR(EINVAL);
1167 dev_priv->cp_ring->handle =
1168 (void *)dev_priv->cp_ring->offset;
1169 dev_priv->ring_rptr->handle =
1170 (void *)dev_priv->ring_rptr->offset;
1171 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
1173 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1174 dev_priv->cp_ring->handle );
1175 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1176 dev_priv->ring_rptr->handle );
1177 DRM_DEBUG( "dev_priv->buffers->handle %p\n",
1178 dev_priv->buffers->handle );
1182 dev_priv->agp_size = init->agp_size;
1183 dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
1184 #if __REALLY_HAVE_AGP
1185 if ( !dev_priv->is_pci )
1186 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1188 + dev_priv->agp_vm_start);
1191 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1193 + dev_priv->agp_vm_start);
1195 DRM_DEBUG( "dev_priv->agp_size %d\n",
1196 dev_priv->agp_size );
1197 DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
1198 dev_priv->agp_vm_start );
1199 DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
1200 dev_priv->agp_buffers_offset );
1202 dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1203 dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1204 + init->ring_size / sizeof(u32));
1205 dev_priv->ring.size = init->ring_size;
1206 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
1208 dev_priv->ring.tail_mask =
1209 (dev_priv->ring.size / sizeof(u32)) - 1;
1211 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1213 #if __REALLY_HAVE_SG
1214 if ( dev_priv->is_pci ) {
1215 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
1216 &dev_priv->bus_pci_gart)) {
1217 DRM_ERROR( "failed to init PCI GART!\n" );
1218 dev->dev_private = (void *)dev_priv;
1219 radeon_do_cleanup_cp(dev);
1220 return DRM_ERR(ENOMEM);
1224 tmp = RADEON_READ( RADEON_AIC_CNTL )
1225 | RADEON_PCIGART_TRANSLATE_EN;
1226 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
1228 /* set PCI GART page-table base address
1230 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
1232 /* set address range for PCI address translate
1234 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
1235 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
1236 + dev_priv->agp_size - 1);
1238 /* Turn off AGP aperture -- is this required for PCIGART?
1240 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
1241 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1243 #endif /* __REALLY_HAVE_SG */
1244 /* Turn off PCI GART
1246 tmp = RADEON_READ( RADEON_AIC_CNTL )
1247 & ~RADEON_PCIGART_TRANSLATE_EN;
1248 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
1249 #if __REALLY_HAVE_SG
1251 #endif /* __REALLY_HAVE_SG */
1253 radeon_cp_load_microcode( dev_priv );
1254 radeon_cp_init_ring_buffer( dev, dev_priv );
1256 dev_priv->last_buf = 0;
1258 dev->dev_private = (void *)dev_priv;
1260 radeon_do_engine_reset( dev );
1265 int radeon_do_cleanup_cp( drm_device_t *dev )
1270 /* Make sure interrupts are disabled here because the uninstall ioctl
1271 * may not have been called from userspace and after dev_private
1272 * is freed, it's too late.
1274 if ( dev->irq ) DRM(irq_uninstall)(dev);
1277 if ( dev->dev_private ) {
1278 drm_radeon_private_t *dev_priv = dev->dev_private;
1280 if ( !dev_priv->is_pci ) {
1281 if ( dev_priv->cp_ring != NULL )
1282 DRM_IOREMAPFREE( dev_priv->cp_ring );
1283 if ( dev_priv->ring_rptr != NULL )
1284 DRM_IOREMAPFREE( dev_priv->ring_rptr );
1285 if ( dev_priv->buffers != NULL )
1286 DRM_IOREMAPFREE( dev_priv->buffers );
1288 #if __REALLY_HAVE_SG
1289 if (!DRM(ati_pcigart_cleanup)( dev,
1290 dev_priv->phys_pci_gart,
1291 dev_priv->bus_pci_gart ))
1292 DRM_ERROR( "failed to cleanup PCI GART!\n" );
1293 #endif /* __REALLY_HAVE_SG */
1296 DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
1298 dev->dev_private = NULL;
1304 int radeon_cp_init( DRM_IOCTL_ARGS )
1307 drm_radeon_init_t init;
1309 LOCK_TEST_WITH_RETURN( dev, filp );
1311 DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t *)data, sizeof(init) );
1313 switch ( init.func ) {
1314 case RADEON_INIT_CP:
1315 case RADEON_INIT_R200_CP:
1316 return radeon_do_init_cp( dev, &init );
1317 case RADEON_CLEANUP_CP:
1318 return radeon_do_cleanup_cp( dev );
1321 return DRM_ERR(EINVAL);
1324 int radeon_cp_start( DRM_IOCTL_ARGS )
1327 drm_radeon_private_t *dev_priv = dev->dev_private;
1330 LOCK_TEST_WITH_RETURN( dev, filp );
1332 if ( dev_priv->cp_running ) {
1333 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1336 if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1337 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1338 __FUNCTION__, dev_priv->cp_mode );
1342 radeon_do_cp_start( dev_priv );
1347 /* Stop the CP. The engine must have been idled before calling this
1350 int radeon_cp_stop( DRM_IOCTL_ARGS )
1353 drm_radeon_private_t *dev_priv = dev->dev_private;
1354 drm_radeon_cp_stop_t stop;
1358 LOCK_TEST_WITH_RETURN( dev, filp );
1360 DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t *)data, sizeof(stop) );
1362 if (!dev_priv->cp_running)
1365 /* Flush any pending CP commands. This ensures any outstanding
1366 * commands are exectuted by the engine before we turn it off.
1369 radeon_do_cp_flush( dev_priv );
1372 /* If we fail to make the engine go idle, we return an error
1373 * code so that the DRM ioctl wrapper can try again.
1376 ret = radeon_do_cp_idle( dev_priv );
1377 if ( ret ) return ret;
1380 /* Finally, we can turn off the CP. If the engine isn't idle,
1381 * we will get some dropped triangles as they won't be fully
1382 * rendered before the CP is shut down.
1384 radeon_do_cp_stop( dev_priv );
1386 /* Reset the engine */
1387 radeon_do_engine_reset( dev );
1393 void radeon_do_release( drm_device_t *dev )
1395 drm_radeon_private_t *dev_priv = dev->dev_private;
1399 if (dev_priv->cp_running) {
1401 while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
1402 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1406 tsleep(&ret, PZERO, "rdnrel", 1);
1409 radeon_do_cp_stop( dev_priv );
1410 radeon_do_engine_reset( dev );
1413 /* Disable *all* interrupts */
1414 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1416 /* Free memory heap structures */
1417 radeon_mem_takedown( &(dev_priv->agp_heap) );
1418 radeon_mem_takedown( &(dev_priv->fb_heap) );
1420 /* deallocate kernel resources */
1421 radeon_do_cleanup_cp( dev );
1425 /* Just reset the CP ring. Called as part of an X Server engine reset.
1427 int radeon_cp_reset( DRM_IOCTL_ARGS )
1430 drm_radeon_private_t *dev_priv = dev->dev_private;
1433 LOCK_TEST_WITH_RETURN( dev, filp );
1436 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1437 return DRM_ERR(EINVAL);
1440 radeon_do_cp_reset( dev_priv );
1442 /* The CP is no longer running after an engine reset */
1443 dev_priv->cp_running = 0;
1448 int radeon_cp_idle( DRM_IOCTL_ARGS )
1451 drm_radeon_private_t *dev_priv = dev->dev_private;
1454 LOCK_TEST_WITH_RETURN( dev, filp );
1456 return radeon_do_cp_idle( dev_priv );
1459 int radeon_engine_reset( DRM_IOCTL_ARGS )
1464 LOCK_TEST_WITH_RETURN( dev, filp );
1466 return radeon_do_engine_reset( dev );
1470 /* ================================================================
1474 /* KW: Deprecated to say the least:
1476 int radeon_fullscreen( DRM_IOCTL_ARGS )
1482 /* ================================================================
1483 * Freelist management
1486 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1487 * bufs until freelist code is used. Note this hides a problem with
1488 * the scratch register * (used to keep track of last buffer
1489 * completed) being written to before * the last buffer has actually
1490 * completed rendering.
1492 * KW: It's also a good way to find free buffers quickly.
1494 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1495 * sleep. However, bugs in older versions of radeon_accel.c mean that
1496 * we essentially have to do this, else old clients will break.
1498 * However, it does leave open a potential deadlock where all the
1499 * buffers are held by other clients, which can't release them because
1500 * they can't get the lock.
1503 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1505 drm_device_dma_t *dma = dev->dma;
1506 drm_radeon_private_t *dev_priv = dev->dev_private;
1507 drm_radeon_buf_priv_t *buf_priv;
1512 if ( ++dev_priv->last_buf >= dma->buf_count )
1513 dev_priv->last_buf = 0;
1515 start = dev_priv->last_buf;
1517 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1518 u32 done_age = GET_SCRATCH( 1 );
1519 DRM_DEBUG("done_age = %d\n",done_age);
1520 for ( i = start ; i < dma->buf_count ; i++ ) {
1521 buf = dma->buflist[i];
1522 buf_priv = buf->dev_private;
1523 if ( buf->filp == 0 || (buf->pending &&
1524 buf_priv->age <= done_age) ) {
1525 dev_priv->stats.requested_bufs++;
1534 dev_priv->stats.freelist_loops++;
1538 DRM_DEBUG( "returning NULL!\n" );
1542 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1544 drm_device_dma_t *dma = dev->dma;
1545 drm_radeon_private_t *dev_priv = dev->dev_private;
1546 drm_radeon_buf_priv_t *buf_priv;
1550 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1552 if ( ++dev_priv->last_buf >= dma->buf_count )
1553 dev_priv->last_buf = 0;
1555 start = dev_priv->last_buf;
1556 dev_priv->stats.freelist_loops++;
1558 for ( t = 0 ; t < 2 ; t++ ) {
1559 for ( i = start ; i < dma->buf_count ; i++ ) {
1560 buf = dma->buflist[i];
1561 buf_priv = buf->dev_private;
1562 if ( buf->filp == 0 || (buf->pending &&
1563 buf_priv->age <= done_age) ) {
1564 dev_priv->stats.requested_bufs++;
1576 void radeon_freelist_reset( drm_device_t *dev )
1578 drm_device_dma_t *dma = dev->dma;
1579 drm_radeon_private_t *dev_priv = dev->dev_private;
1582 dev_priv->last_buf = 0;
1583 for ( i = 0 ; i < dma->buf_count ; i++ ) {
1584 drm_buf_t *buf = dma->buflist[i];
1585 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1591 /* ================================================================
1592 * CP command submission
1595 int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1597 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1599 u32 last_head = GET_RING_HEAD( dev_priv );
1601 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1602 u32 head = GET_RING_HEAD( dev_priv );
1604 ring->space = (head - ring->tail) * sizeof(u32);
1605 if ( ring->space <= 0 )
1606 ring->space += ring->size;
1607 if ( ring->space > n )
1610 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1612 if (head != last_head)
1619 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1620 #if RADEON_FIFO_DEBUG
1621 radeon_status( dev_priv );
1622 DRM_ERROR( "failed!\n" );
1624 return DRM_ERR(EBUSY);
1627 static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
1632 for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1633 buf = radeon_freelist_get( dev );
1634 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
1638 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1639 sizeof(buf->idx) ) )
1640 return DRM_ERR(EFAULT);
1641 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1642 sizeof(buf->total) ) )
1643 return DRM_ERR(EFAULT);
1650 int radeon_cp_buffers( DRM_IOCTL_ARGS )
1653 drm_device_dma_t *dma = dev->dma;
1657 LOCK_TEST_WITH_RETURN( dev, filp );
1659 DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) );
1661 /* Please don't send us buffers.
1663 if ( d.send_count != 0 ) {
1664 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1665 DRM_CURRENTPID, d.send_count );
1666 return DRM_ERR(EINVAL);
1669 /* We'll send you buffers.
1671 if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1672 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1673 DRM_CURRENTPID, d.request_count, dma->buf_count );
1674 return DRM_ERR(EINVAL);
1677 d.granted_count = 0;
1679 if ( d.request_count ) {
1680 ret = radeon_cp_get_buffers( filp, dev, &d );
1683 DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) );