4 * Copyright (C) 1999 Intel Corp.
5 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
6 * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
7 * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 1999 VA Linux Systems
10 * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
12 * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O APIC code.
13 * In particular, we now have separate handlers for edge
14 * and level triggered interrupts.
15 * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector allocation
16 * PCI to vector mapping, shared PCI interrupts.
17 * 00/10/27 D. Mosberger Document things a bit more to make them more understandable.
18 * Clean up much of the old IOSAPIC cruft.
19 * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts and fixes for
20 * ACPI S5(SoftOff) support.
21 * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT
22 * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt vectors in
23 * iosapic_set_affinity(), initializations for
24 * /proc/irq/#/smp_affinity
25 * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing.
26 * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq
27 * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to IOSAPIC mapping
29 * 02/07/29 T. Kochi Allocate interrupt vectors dynamically
30 * 02/08/04 T. Kochi Cleaned up terminology (irq, global system interrupt, vector, etc.)
31 * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's pci_irq code.
32 * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC.
33 * Remove iosapic_address & gsi_base from external interfaces.
34 * Rationalize __init/__devinit attributes.
37 * Here is what the interrupt logic between a PCI device and the kernel looks like:
39 * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, INTD). The
40 * device is uniquely identified by its bus--, and slot-number (the function
41 * number does not matter here because all functions share the same interrupt
44 * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC controller.
45 * Multiple interrupt lines may have to share the same IOSAPIC pin (if they're level
46 * triggered and use the same polarity). Each interrupt line has a unique Global
47 * System Interrupt (GSI) number which can be calculated as the sum of the controller's
48 * base GSI number and the IOSAPIC pin number to which the line connects.
50 * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the IOSAPIC pin
51 * into the IA-64 interrupt vector. This interrupt vector is then sent to the CPU.
53 * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is used as
54 * architecture-independent interrupt handling mechanism in Linux. As an
55 * IRQ is a number, we have to have IA-64 interrupt vector number <-> IRQ number
56 * mapping. On smaller systems, we use one-to-one mapping between IA-64 vector and
57 * IRQ. A platform can implement platform_irq_to_vector(irq) and
58 * platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
59 * Please see also include/asm-ia64/hw_irq.h for those APIs.
61 * To sum up, there are three levels of mappings involved:
63 * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
65 * Note: The term "IRQ" is loosely used everywhere in Linux kernel to describe interrupts.
66 * Now we use "IRQ" only for Linux IRQ's. ISA IRQ (isa_irq) is the only exception in this
69 #include <linux/config.h>
71 #include <linux/acpi.h>
72 #include <linux/init.h>
73 #include <linux/irq.h>
74 #include <linux/kernel.h>
75 #include <linux/list.h>
76 #include <linux/pci.h>
77 #include <linux/smp.h>
78 #include <linux/smp_lock.h>
79 #include <linux/string.h>
81 #include <asm/delay.h>
82 #include <asm/hw_irq.h>
84 #include <asm/iosapic.h>
85 #include <asm/machvec.h>
86 #include <asm/processor.h>
87 #include <asm/ptrace.h>
88 #include <asm/system.h>
91 #undef DEBUG_INTERRUPT_ROUTING
94 #ifdef DEBUG_INTERRUPT_ROUTING
95 #define DBG(fmt...) printk(fmt)
100 static spinlock_t iosapic_lock = SPIN_LOCK_UNLOCKED;
102 /* These tables map IA-64 vectors to the IOSAPIC pin that generates this vector. */
104 static struct iosapic_intr_info {
105 char *addr; /* base address of IOSAPIC */
106 unsigned int gsi_base; /* first GSI assigned to this IOSAPIC */
107 char rte_index; /* IOSAPIC RTE index (-1 => not an IOSAPIC interrupt) */
108 unsigned char dmode : 3; /* delivery mode (see iosapic.h) */
109 unsigned char polarity: 1; /* interrupt polarity (see iosapic.h) */
110 unsigned char trigger : 1; /* trigger mode (see iosapic.h) */
111 } iosapic_intr_info[IA64_NUM_VECTORS];
113 static struct iosapic {
114 char *addr; /* base address of IOSAPIC */
115 unsigned int gsi_base; /* first GSI assigned to this IOSAPIC */
116 unsigned short num_rte; /* number of RTE in this IOSAPIC */
117 } iosapic_lists[256];
119 static int num_iosapic;
121 static unsigned char pcat_compat __initdata; /* 8259 compatibility flag */
125 * Find an IOSAPIC associated with a GSI
128 find_iosapic (unsigned int gsi)
132 for (i = 0; i < num_iosapic; i++) {
133 if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < iosapic_lists[i].num_rte)
141 _gsi_to_vector (unsigned int gsi)
143 struct iosapic_intr_info *info;
145 for (info = iosapic_intr_info; info < iosapic_intr_info + IA64_NUM_VECTORS; ++info)
146 if (info->gsi_base + info->rte_index == gsi)
147 return info - iosapic_intr_info;
152 * Translate GSI number to the corresponding IA-64 interrupt vector. If no
153 * entry exists, return -1.
156 gsi_to_vector (unsigned int gsi)
158 return _gsi_to_vector(gsi);
162 gsi_to_irq (unsigned int gsi)
165 * XXX fix me: this assumes an identity mapping vetween IA-64 vector and Linux irq
168 return _gsi_to_vector(gsi);
172 set_rte (unsigned int vector, unsigned int dest)
174 unsigned long pol, trigger, dmode;
180 DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
182 rte_index = iosapic_intr_info[vector].rte_index;
184 return; /* not an IOSAPIC interrupt */
186 addr = iosapic_intr_info[vector].addr;
187 pol = iosapic_intr_info[vector].polarity;
188 trigger = iosapic_intr_info[vector].trigger;
189 dmode = iosapic_intr_info[vector].dmode;
191 redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
196 for (irq = 0; irq < NR_IRQS; ++irq)
197 if (irq_to_vector(irq) == vector) {
198 set_irq_affinity_info(irq, (int)(dest & 0xffff), redir);
204 low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
205 (trigger << IOSAPIC_TRIGGER_SHIFT) |
206 (dmode << IOSAPIC_DELIVERY_SHIFT) |
209 /* dest contains both id and eid */
210 high32 = (dest << IOSAPIC_DEST_SHIFT);
212 writel(IOSAPIC_RTE_HIGH(rte_index), addr + IOSAPIC_REG_SELECT);
213 writel(high32, addr + IOSAPIC_WINDOW);
214 writel(IOSAPIC_RTE_LOW(rte_index), addr + IOSAPIC_REG_SELECT);
215 writel(low32, addr + IOSAPIC_WINDOW);
219 nop (unsigned int vector)
225 mask_irq (unsigned int irq)
231 ia64_vector vec = irq_to_vector(irq);
233 addr = iosapic_intr_info[vec].addr;
234 rte_index = iosapic_intr_info[vec].rte_index;
237 return; /* not an IOSAPIC interrupt! */
239 spin_lock_irqsave(&iosapic_lock, flags);
241 writel(IOSAPIC_RTE_LOW(rte_index), addr + IOSAPIC_REG_SELECT);
242 low32 = readl(addr + IOSAPIC_WINDOW);
244 low32 |= (1 << IOSAPIC_MASK_SHIFT); /* set only the mask bit */
245 writel(low32, addr + IOSAPIC_WINDOW);
247 spin_unlock_irqrestore(&iosapic_lock, flags);
251 unmask_irq (unsigned int irq)
257 ia64_vector vec = irq_to_vector(irq);
259 addr = iosapic_intr_info[vec].addr;
260 rte_index = iosapic_intr_info[vec].rte_index;
262 return; /* not an IOSAPIC interrupt! */
264 spin_lock_irqsave(&iosapic_lock, flags);
266 writel(IOSAPIC_RTE_LOW(rte_index), addr + IOSAPIC_REG_SELECT);
267 low32 = readl(addr + IOSAPIC_WINDOW);
269 low32 &= ~(1 << IOSAPIC_MASK_SHIFT); /* clear only the mask bit */
270 writel(low32, addr + IOSAPIC_WINDOW);
272 spin_unlock_irqrestore(&iosapic_lock, flags);
277 iosapic_set_affinity (unsigned int irq, unsigned long mask)
284 int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
287 irq &= (~IA64_IRQ_REDIRECTED);
288 vec = irq_to_vector(irq);
290 mask &= cpu_online_map;
292 if (!mask || vec >= IA64_NUM_VECTORS)
295 dest = cpu_physical_id(ffz(~mask));
297 rte_index = iosapic_intr_info[vec].rte_index;
298 addr = iosapic_intr_info[vec].addr;
301 return; /* not an IOSAPIC interrupt */
303 set_irq_affinity_info(irq, dest, redir);
305 /* dest contains both id and eid */
306 high32 = dest << IOSAPIC_DEST_SHIFT;
308 spin_lock_irqsave(&iosapic_lock, flags);
310 /* get current delivery mode by reading the low32 */
311 writel(IOSAPIC_RTE_LOW(rte_index), addr + IOSAPIC_REG_SELECT);
312 low32 = readl(addr + IOSAPIC_WINDOW);
314 low32 &= ~(7 << IOSAPIC_DELIVERY_SHIFT);
316 /* change delivery mode to lowest priority */
317 low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
319 /* change delivery mode to fixed */
320 low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
322 writel(IOSAPIC_RTE_HIGH(rte_index), addr + IOSAPIC_REG_SELECT);
323 writel(high32, addr + IOSAPIC_WINDOW);
324 writel(IOSAPIC_RTE_LOW(rte_index), addr + IOSAPIC_REG_SELECT);
325 writel(low32, addr + IOSAPIC_WINDOW);
327 spin_unlock_irqrestore(&iosapic_lock, flags);
332 * Handlers for level-triggered interrupts.
336 iosapic_startup_level_irq (unsigned int irq)
343 iosapic_end_level_irq (unsigned int irq)
345 ia64_vector vec = irq_to_vector(irq);
347 writel(vec, iosapic_intr_info[vec].addr + IOSAPIC_EOI);
350 #define iosapic_shutdown_level_irq mask_irq
351 #define iosapic_enable_level_irq unmask_irq
352 #define iosapic_disable_level_irq mask_irq
353 #define iosapic_ack_level_irq nop
355 struct hw_interrupt_type irq_type_iosapic_level = {
356 .typename = "IO-SAPIC-level",
357 .startup = iosapic_startup_level_irq,
358 .shutdown = iosapic_shutdown_level_irq,
359 .enable = iosapic_enable_level_irq,
360 .disable = iosapic_disable_level_irq,
361 .ack = iosapic_ack_level_irq,
362 .end = iosapic_end_level_irq,
363 .set_affinity = iosapic_set_affinity
367 * Handlers for edge-triggered interrupts.
371 iosapic_startup_edge_irq (unsigned int irq)
375 * IOSAPIC simply drops interrupts pended while the
376 * corresponding pin was masked, so we can't know if an
377 * interrupt is pending already. Let's hope not...
383 iosapic_ack_edge_irq (unsigned int irq)
385 irq_desc_t *idesc = irq_desc(irq);
387 * Once we have recorded IRQ_PENDING already, we can mask the
388 * interrupt for real. This prevents IRQ storms from unhandled
391 if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == (IRQ_PENDING|IRQ_DISABLED))
395 #define iosapic_enable_edge_irq unmask_irq
396 #define iosapic_disable_edge_irq nop
397 #define iosapic_end_edge_irq nop
399 struct hw_interrupt_type irq_type_iosapic_edge = {
400 .typename = "IO-SAPIC-edge",
401 .startup = iosapic_startup_edge_irq,
402 .shutdown = iosapic_disable_edge_irq,
403 .enable = iosapic_enable_edge_irq,
404 .disable = iosapic_disable_edge_irq,
405 .ack = iosapic_ack_edge_irq,
406 .end = iosapic_end_edge_irq,
407 .set_affinity = iosapic_set_affinity
411 iosapic_version (char *addr)
414 * IOSAPIC Version Register return 32 bit structure like:
416 * unsigned int version : 8;
417 * unsigned int reserved1 : 8;
418 * unsigned int max_redir : 8;
419 * unsigned int reserved2 : 8;
422 writel(IOSAPIC_VERSION, addr + IOSAPIC_REG_SELECT);
423 return readl(IOSAPIC_WINDOW + addr);
427 * if the given vector is already owned by other,
428 * assign a new vector for the other and make the vector available
431 iosapic_reassign_vector (int vector)
435 if (iosapic_intr_info[vector].rte_index >= 0 || iosapic_intr_info[vector].addr
436 || iosapic_intr_info[vector].gsi_base || iosapic_intr_info[vector].dmode
437 || iosapic_intr_info[vector].polarity || iosapic_intr_info[vector].trigger)
439 new_vector = ia64_alloc_vector();
440 printk(KERN_INFO "Reassigning vector %d to %d\n", vector, new_vector);
441 memcpy(&iosapic_intr_info[new_vector], &iosapic_intr_info[vector],
442 sizeof(struct iosapic_intr_info));
443 memset(&iosapic_intr_info[vector], 0, sizeof(struct iosapic_intr_info));
444 iosapic_intr_info[vector].rte_index = -1;
449 register_intr (unsigned int gsi, int vector, unsigned char delivery,
450 unsigned long polarity, unsigned long trigger)
453 struct hw_interrupt_type *irq_type;
456 unsigned long gsi_base;
457 char *iosapic_address;
459 index = find_iosapic(gsi);
461 printk(KERN_WARNING "%s: No IOSAPIC for GSI 0x%x\n", __FUNCTION__, gsi);
465 iosapic_address = iosapic_lists[index].addr;
466 gsi_base = iosapic_lists[index].gsi_base;
468 rte_index = gsi - gsi_base;
469 iosapic_intr_info[vector].rte_index = rte_index;
470 iosapic_intr_info[vector].polarity = polarity;
471 iosapic_intr_info[vector].dmode = delivery;
472 iosapic_intr_info[vector].addr = iosapic_address;
473 iosapic_intr_info[vector].gsi_base = gsi_base;
474 iosapic_intr_info[vector].trigger = trigger;
476 if (trigger == IOSAPIC_EDGE)
477 irq_type = &irq_type_iosapic_edge;
479 irq_type = &irq_type_iosapic_level;
481 idesc = irq_desc(vector);
482 if (idesc->handler != irq_type) {
483 if (idesc->handler != &no_irq_type)
484 printk(KERN_WARNING "%s: changing vector %d from %s to %s\n",
485 __FUNCTION__, vector, idesc->handler->typename, irq_type->typename);
486 idesc->handler = irq_type;
491 * ACPI can describe IOSAPIC interrupts via static tables and namespace
492 * methods. This provides an interface to register those interrupts and
493 * program the IOSAPIC RTE.
496 iosapic_register_intr (unsigned int gsi,
497 unsigned long polarity, unsigned long trigger)
500 unsigned int dest = (ia64_get_lid() >> 16) & 0xffff;
502 vector = gsi_to_vector(gsi);
504 vector = ia64_alloc_vector();
506 register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY,
509 printk(KERN_INFO "GSI 0x%x(%s,%s) -> CPU 0x%04x vector %d\n",
510 gsi, (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
511 (trigger == IOSAPIC_EDGE ? "edge" : "level"), dest, vector);
513 /* program the IOSAPIC routing table */
514 set_rte(vector, dest);
519 * ACPI calls this when it finds an entry for a platform interrupt.
520 * Note that the irq_base and IOSAPIC address must be set in iosapic_init().
523 iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
524 int iosapic_vector, u16 eid, u16 id,
525 unsigned long polarity, unsigned long trigger)
527 unsigned char delivery;
529 unsigned int dest = ((id << 8) | eid) & 0xffff;
532 case ACPI_INTERRUPT_PMI:
533 vector = iosapic_vector;
535 * since PMI vector is alloc'd by FW(ACPI) not by kernel,
536 * we need to make sure the vector is available
538 iosapic_reassign_vector(vector);
539 delivery = IOSAPIC_PMI;
541 case ACPI_INTERRUPT_INIT:
542 vector = ia64_alloc_vector();
543 delivery = IOSAPIC_INIT;
545 case ACPI_INTERRUPT_CPEI:
546 vector = IA64_PCE_VECTOR;
547 delivery = IOSAPIC_LOWEST_PRIORITY;
550 printk(KERN_ERR "iosapic_register_platform_irq(): invalid int type\n");
554 register_intr(gsi, vector, delivery, polarity,
557 printk(KERN_INFO "PLATFORM int 0x%x: GSI 0x%x(%s,%s) -> CPU 0x%04x vector %d\n",
558 int_type, gsi, (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
559 (trigger == IOSAPIC_EDGE ? "edge" : "level"), dest, vector);
561 /* program the IOSAPIC routing table */
562 set_rte(vector, dest);
568 * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
569 * Note that the gsi_base and IOSAPIC address must be set in iosapic_init().
572 iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
573 unsigned long polarity,
574 unsigned long trigger)
577 unsigned int dest = (ia64_get_lid() >> 16) & 0xffff;
579 vector = isa_irq_to_vector(isa_irq);
581 register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, polarity, trigger);
583 DBG("ISA: IRQ %u -> GSI 0x%x (%s,%s) -> CPU 0x%04x vector %d\n",
585 polarity == IOSAPIC_POL_HIGH ? "high" : "low", trigger == IOSAPIC_EDGE ? "edge" : "level",
588 /* program the IOSAPIC routing table */
589 set_rte(vector, dest);
593 iosapic_system_init (int system_pcat_compat)
597 for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
598 iosapic_intr_info[vector].rte_index = -1; /* mark as unused */
600 pcat_compat = system_pcat_compat;
603 * Disable the compatibility mode interrupts (8259 style), needs IN/OUT support
606 printk(KERN_INFO "%s: Disabling PC-AT compatible 8259 interrupts\n", __FUNCTION__);
613 iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
616 unsigned int isa_irq, ver;
619 addr = ioremap(phys_addr, 0);
620 ver = iosapic_version(addr);
623 * The MAX_REDIR register holds the highest input pin
624 * number (starting from 0).
625 * We add 1 so that we can use it for number of pins (= RTEs)
627 num_rte = ((ver >> 16) & 0xff) + 1;
629 iosapic_lists[num_iosapic].addr = addr;
630 iosapic_lists[num_iosapic].gsi_base = gsi_base;
631 iosapic_lists[num_iosapic].num_rte = num_rte;
634 printk(KERN_INFO " IOSAPIC v%x.%x, address 0x%lx, GSIs 0x%x-0x%x\n",
635 (ver & 0xf0) >> 4, (ver & 0x0f), phys_addr, gsi_base, gsi_base + num_rte - 1);
637 if ((gsi_base == 0) && pcat_compat) {
640 * Map the legacy ISA devices into the IOSAPIC data. Some of these may
641 * get reprogrammed later on with data from the ACPI Interrupt Source
644 for (isa_irq = 0; isa_irq < 16; ++isa_irq)
645 iosapic_override_isa_irq(isa_irq, isa_irq, IOSAPIC_POL_HIGH, IOSAPIC_EDGE);
650 fixup_vector (int vector, unsigned int gsi, const char *pci_id)
652 struct hw_interrupt_type *irq_type = &irq_type_iosapic_level;
656 idesc = irq_desc(vector);
657 if (idesc->handler != irq_type) {
658 if (idesc->handler != &no_irq_type)
659 printk(KERN_INFO "IOSAPIC: changing vector %d from %s to %s\n",
660 vector, idesc->handler->typename, irq_type->typename);
661 idesc->handler = irq_type;
665 * For platforms that do not support interrupt redirect via the XTP interface, we
666 * can round-robin the PCI device interrupts to the processors
668 if (!(smp_int_redirect & SMP_IRQ_REDIRECTION)) {
669 static int cpu_index = -1;
672 if (++cpu_index >= NR_CPUS)
674 while (!cpu_online(cpu_index));
676 dest = cpu_physical_id(cpu_index) & 0xffff;
679 * Direct the interrupt vector to the current cpu, platform redirection
680 * will distribute them.
682 dest = (ia64_get_lid() >> 16) & 0xffff;
685 /* direct the interrupt vector to the running cpu id */
686 dest = (ia64_get_lid() >> 16) & 0xffff;
688 set_rte(vector, dest);
690 printk(KERN_INFO "IOSAPIC: %s -> GSI 0x%x -> CPU 0x%04x vector %d\n",
691 pci_id, gsi, dest, vector);
695 iosapic_parse_prt (void)
697 struct acpi_prt_entry *entry;
698 struct list_head *node;
703 list_for_each(node, &acpi_prt.entries) {
704 entry = list_entry(node, struct acpi_prt_entry, node);
706 /* We're only interested in static (non-link) entries. */
707 if (entry->link.handle)
710 gsi = entry->link.index;
712 vector = gsi_to_vector(gsi);
714 /* allocate a vector for this interrupt line */
715 if (pcat_compat && (gsi < 16))
716 vector = isa_irq_to_vector(gsi);
718 /* new GSI; allocate a vector for it */
719 vector = ia64_alloc_vector();
721 register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, IOSAPIC_POL_LOW, IOSAPIC_LEVEL);
723 snprintf(pci_id, sizeof(pci_id), "%02x:%02x:%02x[%c]",
724 entry->id.segment, entry->id.bus, entry->id.device, 'A' + entry->pin);
726 fixup_vector(vector, gsi, pci_id);