2 * Low-Level PCI Support for PC -- Routing of Interrupts
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
7 #include <linux/config.h>
8 #include <linux/types.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
17 #include <asm/io_apic.h>
21 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
22 #define PIRQ_VERSION 0x0100
24 int broken_hp_bios_irq9;
26 static struct irq_routing_table *pirq_table;
29 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
30 * Avoid using: 13, 14 and 15 (FP error and IDE).
31 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
33 unsigned int pcibios_irq_mask = 0xfff8;
35 static int pirq_penalty[16] = {
36 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
37 0, 0, 0, 0, 1000, 100000, 100000, 100000
43 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
44 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new);
47 int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL;
50 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
53 static struct irq_routing_table * __init pirq_find_routing_table(void)
56 struct irq_routing_table *rt;
60 for(addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
61 rt = (struct irq_routing_table *) addr;
62 if (rt->signature != PIRQ_SIGNATURE ||
63 rt->version != PIRQ_VERSION ||
65 rt->size < sizeof(struct irq_routing_table))
68 for(i=0; i<rt->size; i++)
71 DBG("PCI: Interrupt Routing Table found at 0x%p\n", rt);
79 * If we have a IRQ routing table, use it to search for peer host
80 * bridges. It's a gross hack, but since there are no other known
81 * ways how to get a list of buses, we have to go this way.
84 static void __init pirq_peer_trick(void)
86 struct irq_routing_table *rt = pirq_table;
91 memset(busmap, 0, sizeof(busmap));
92 for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
97 DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
99 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
105 for(i = 1; i < 256; i++) {
106 if (!busmap[i] || pci_find_bus(0, i))
108 if (pci_scan_bus(i, &pci_root_ops, NULL))
109 printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
111 pcibios_last_bus = -1;
115 * Code for querying and setting of IRQ routes on various interrupt routers.
118 void eisa_set_level_irq(unsigned int irq)
120 unsigned char mask = 1 << (irq & 7);
121 unsigned int port = 0x4d0 + (irq >> 3);
122 unsigned char val = inb(port);
126 outb(val | mask, port);
131 * Common IRQ routing practice: nybbles in config space,
132 * offset by some magic constant.
134 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
137 unsigned reg = offset + (nr >> 1);
139 pci_read_config_byte(router, reg, &x);
140 return (nr & 1) ? (x >> 4) : (x & 0xf);
143 static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val)
146 unsigned reg = offset + (nr >> 1);
148 pci_read_config_byte(router, reg, &x);
149 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
150 pci_write_config_byte(router, reg, x);
154 * ALI pirq entries are damn ugly, and completely undocumented.
155 * This has been figured out from pirq tables, and it's not a pretty
158 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
160 static unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
162 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
165 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
167 static unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
168 unsigned int val = irqmap[irq];
171 write_config_nybble(router, 0x48, pirq-1, val);
178 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
179 * just a pointer to the config space.
181 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
185 pci_read_config_byte(router, pirq, &x);
186 return (x < 16) ? x : 0;
189 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
191 pci_write_config_byte(router, pirq, irq);
196 * The VIA pirq rules are nibble-based, like ALI,
197 * but without the ugly irq number munging.
198 * However, PIRQD is in the upper instead of lower 4 bits.
200 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
202 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
205 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
207 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
212 * ITE 8330G pirq rules are nibble-based
213 * FIXME: pirqmap may be { 1, 0, 3, 2 },
214 * 2+3 are both mapped to irq 9 on my system
216 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
218 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
219 return read_config_nybble(router,0x43, pirqmap[pirq-1]);
222 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
224 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
225 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
230 * OPTI: high four bits are nibble pointer..
231 * I wonder what the low bits do?
233 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
235 return read_config_nybble(router, 0xb8, pirq >> 4);
238 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
240 write_config_nybble(router, 0xb8, pirq >> 4, irq);
245 * Cyrix: nibble offset 0x5C
246 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
247 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
249 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
251 return read_config_nybble(router, 0x5C, (pirq-1)^1);
254 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
256 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
261 * PIRQ routing for SiS 85C503 router used in several SiS chipsets
262 * According to the SiS 5595 datasheet (preliminary V1.0, 12/24/1997)
263 * the related registers work as follows:
265 * general: one byte per re-routable IRQ,
266 * bit 7 IRQ mapping enabled (0) or disabled (1)
267 * bits [6:4] reserved
268 * bits [3:0] IRQ to map to
269 * allowed: 3-7, 9-12, 14-15
270 * reserved: 0, 1, 2, 8, 13
272 * individual registers in device config space:
274 * 0x41/0x42/0x43/0x44: PCI INT A/B/C/D - bits as in general case
276 * 0x61: IDEIRQ: bits as in general case - but:
277 * bits [6:5] must be written 01
278 * bit 4 channel-select primary (0), secondary (1)
280 * 0x62: USBIRQ: bits as in general case - but:
281 * bit 4 OHCI function disabled (0), enabled (1)
283 * 0x6a: ACPI/SCI IRQ - bits as in general case
285 * 0x7e: Data Acq. Module IRQ - bits as in general case
287 * Apparently there are systems implementing PCI routing table using both
288 * link values 0x01-0x04 and 0x41-0x44 for PCI INTA..D, but register offsets
289 * like 0x62 as link values for USBIRQ e.g. So there is no simple
290 * "register = offset + pirq" relation.
291 * Currently we support PCI INTA..D and USBIRQ and try our best to handle
292 * both link mappings.
293 * IDE/ACPI/DAQ mapping is currently unsupported (left untouched as set by BIOS).
296 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
312 pci_read_config_byte(router, reg, &x);
321 printk(KERN_INFO "SiS pirq: advanced IDE/ACPI/DAQ mapping not yet implemented\n");
324 printk(KERN_INFO "SiS router pirq escape (%d)\n", pirq);
327 return (x & 0x80) ? 0 : (x & 0x0f);
330 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
346 x = (irq&0x0f) ? (irq&0x0f) : 0x80;
349 /* always mark OHCI enabled, as nothing else knows about this */
355 printk(KERN_INFO "advanced SiS pirq mapping not yet implemented\n");
358 printk(KERN_INFO "SiS router pirq escape (%d)\n", pirq);
361 pci_write_config_byte(router, reg, x);
367 * VLSI: nibble offset 0x74 - educated guess due to routing table and
368 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
369 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
370 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
371 * for the busbridge to the docking station.
374 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
377 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
380 return read_config_nybble(router, 0x74, pirq-1);
383 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
386 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
389 write_config_nybble(router, 0x74, pirq-1, irq);
394 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
395 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
396 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
397 * register is a straight binary coding of desired PIC IRQ (low nibble).
399 * The 'link' value in the PIRQ table is already in the correct format
400 * for the Index register. There are some special index values:
401 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
402 * and 0x03 for SMBus.
404 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
407 return inb(0xc01) & 0xf;
410 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
417 /* Support for AMD756 PCI IRQ Routing
418 * Jhon H. Caicedo <jhcaiced@osso.org.co>
419 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
420 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
421 * The AMD756 pirq rules are nibble-based
422 * offset 0x56 0-3 PIRQA 4-7 PIRQB
423 * offset 0x57 0-3 PIRQC 4-7 PIRQD
425 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
431 irq = read_config_nybble(router, 0x56, pirq - 1);
433 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
434 dev->vendor, dev->device, pirq, irq);
438 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
440 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
441 dev->vendor, dev->device, pirq, irq);
444 write_config_nybble(router, 0x56, pirq - 1, irq);
449 #ifdef CONFIG_PCI_BIOS
451 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
453 struct pci_dev *bridge;
454 int pin = pci_get_interrupt_pin(dev, &bridge);
455 return pcibios_set_irq_routing(bridge, pin, irq);
458 static struct irq_router pirq_bios_router =
459 { "BIOS", 0, 0, NULL, pirq_bios_set };
463 static struct irq_router pirq_routers[] = {
464 { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, pirq_piix_get, pirq_piix_set },
465 { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, pirq_piix_get, pirq_piix_set },
466 { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, pirq_piix_get, pirq_piix_set },
467 { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, pirq_piix_get, pirq_piix_set },
468 { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_0, pirq_piix_get, pirq_piix_set },
469 { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, pirq_piix_get, pirq_piix_set },
470 { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, pirq_piix_get, pirq_piix_set },
471 { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, pirq_piix_get, pirq_piix_set },
472 { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, pirq_piix_get, pirq_piix_set },
473 { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, pirq_piix_get, pirq_piix_set },
474 { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, pirq_piix_get, pirq_piix_set },
475 { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, pirq_piix_get, pirq_piix_set },
476 { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_0, pirq_piix_get, pirq_piix_set },
478 { "ALI", PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, pirq_ali_get, pirq_ali_set },
480 { "ITE", PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8330G_0, pirq_ite_get, pirq_ite_set },
482 { "VIA", PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, pirq_via_get, pirq_via_set },
483 { "VIA", PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, pirq_via_get, pirq_via_set },
484 { "VIA", PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, pirq_via_get, pirq_via_set },
486 { "OPTI", PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C700, pirq_opti_get, pirq_opti_set },
488 { "NatSemi", PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, pirq_cyrix_get, pirq_cyrix_set },
489 { "SIS", PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, pirq_sis_get, pirq_sis_set },
490 { "VLSI 82C534", PCI_VENDOR_ID_VLSI, PCI_DEVICE_ID_VLSI_82C534, pirq_vlsi_get, pirq_vlsi_set },
491 { "ServerWorks", PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4,
492 pirq_serverworks_get, pirq_serverworks_set },
493 { "ServerWorks", PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5,
494 pirq_serverworks_get, pirq_serverworks_set },
495 { "AMD756 VIPER", PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_740B,
496 pirq_amd756_get, pirq_amd756_set },
497 { "AMD766", PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7413,
498 pirq_amd756_get, pirq_amd756_set },
499 { "AMD768", PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7443,
500 pirq_amd756_get, pirq_amd756_set },
502 { "default", 0, 0, NULL, NULL }
505 static struct irq_router *pirq_router;
506 static struct pci_dev *pirq_router_dev;
508 static void __init pirq_find_router(void)
510 struct irq_routing_table *rt = pirq_table;
511 struct irq_router *r;
513 #ifdef CONFIG_PCI_BIOS
514 if (!rt->signature) {
515 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
516 pirq_router = &pirq_bios_router;
521 DBG("PCI: Attempting to find IRQ router for %04x:%04x\n",
522 rt->rtr_vendor, rt->rtr_device);
524 /* fall back to default router if nothing else found */
525 pirq_router = &pirq_routers[ARRAY_SIZE(pirq_routers) - 1];
527 pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn);
528 if (!pirq_router_dev) {
529 DBG("PCI: Interrupt router not found at %02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
533 for(r=pirq_routers; r->vendor; r++) {
534 /* Exact match against router table entry? Use it! */
535 if (r->vendor == rt->rtr_vendor && r->device == rt->rtr_device) {
539 /* Match against router device entry? Use it as a fallback */
540 if (r->vendor == pirq_router_dev->vendor && r->device == pirq_router_dev->device) {
544 printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n",
546 pirq_router_dev->vendor,
547 pirq_router_dev->device,
548 pirq_router_dev->slot_name);
551 static struct irq_info *pirq_get_info(struct pci_dev *dev)
553 struct irq_routing_table *rt = pirq_table;
554 int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
555 struct irq_info *info;
557 for (info = rt->slots; entries--; info++)
558 if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
563 static irqreturn_t pcibios_test_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
568 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
571 struct irq_info *info;
575 struct irq_router *r = pirq_router;
576 struct pci_dev *dev2 = NULL;
580 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
582 DBG(" -> no interrupt pin\n");
587 /* Find IRQ routing entry */
592 DBG("IRQ for %s:%d", dev->slot_name, pin);
593 info = pirq_get_info(dev);
595 DBG(" -> not found in routing table\n");
598 pirq = info->irq[pin].link;
599 mask = info->irq[pin].bitmap;
601 DBG(" -> not routed\n");
604 DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs);
605 mask &= pcibios_irq_mask;
607 /* Work around broken HP Pavilion Notebooks which assign USB to
608 IRQ 9 even though it is actually wired to IRQ 11 */
610 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
612 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
613 r->set(pirq_router_dev, dev, pirq, 11);
617 * Find the best IRQ to assign: use the one
618 * reported by the device if possible.
621 if (!((1 << newirq) & mask)) {
622 if ( pci_probe & PCI_USE_PIRQ_MASK) newirq = 0;
623 else printk(KERN_WARNING "PCI: IRQ %i for device %s doesn't match PIRQ mask - try pci=usepirqmask\n", newirq, dev->slot_name);
625 if (!newirq && assign) {
626 for (i = 0; i < 16; i++) {
627 if (!(mask & (1 << i)))
629 if (pirq_penalty[i] < pirq_penalty[newirq] &&
630 !request_irq(i, pcibios_test_irq_handler, SA_SHIRQ, "pci-test", dev)) {
636 DBG(" -> newirq=%d", newirq);
638 /* Check if it is hardcoded */
639 if ((pirq & 0xf0) == 0xf0) {
641 DBG(" -> hardcoded IRQ %d\n", irq);
643 } else if ( r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
644 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask)) ) {
645 DBG(" -> got IRQ %d\n", irq);
647 } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
648 DBG(" -> assigning IRQ %d", newirq);
649 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
650 eisa_set_level_irq(newirq);
658 DBG(" ... failed\n");
659 if (newirq && mask == (1 << newirq)) {
665 printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, dev->slot_name);
667 /* Update IRQ for all devices with the same pirq value */
668 while ((dev2 = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) {
669 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
673 info = pirq_get_info(dev2);
676 if (info->irq[pin].link == pirq) {
677 /* We refuse to override the dev->irq information. Give a warning! */
678 if ( dev2->irq && dev2->irq != irq && \
679 (!(pci_probe & PCI_USE_PIRQ_MASK) || \
680 ((1 << dev2->irq) & mask)) ) {
681 printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
682 dev2->slot_name, dev2->irq, irq);
688 printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, dev2->slot_name);
694 static void __init pcibios_fixup_irqs(void)
696 struct pci_dev *dev = NULL;
699 DBG("PCI: IRQ fixup\n");
700 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
702 * If the BIOS has set an out of range IRQ number, just ignore it.
703 * Also keep track of which IRQ's are already in use.
705 if (dev->irq >= 16) {
706 DBG("%s: ignoring bogus IRQ %d\n", dev->slot_name, dev->irq);
709 /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */
710 if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000)
711 pirq_penalty[dev->irq] = 0;
712 pirq_penalty[dev->irq]++;
716 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
717 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
718 #ifdef CONFIG_X86_IO_APIC
720 * Recalculate IRQ numbers if we use the I/O APIC.
722 if (io_apic_assign_pci_irqs)
727 pin--; /* interrupt pins are numbered starting from 1 */
728 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
730 * Busses behind bridges are typically not listed in the MP-table.
731 * In this case we have to look up the IRQ based on the parent bus,
732 * parent slot, and pin number. The SMP code detects such bridged
733 * busses itself so we should get into this branch reliably.
735 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
736 struct pci_dev * bridge = dev->bus->self;
738 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
739 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
740 PCI_SLOT(bridge->devfn), pin);
742 printk(KERN_WARNING "PCI: using PPB(B%d,I%d,P%d) to get irq %d\n",
743 bridge->bus->number, PCI_SLOT(bridge->devfn), pin, irq);
746 printk(KERN_INFO "PCI->APIC IRQ transform: (B%d,I%d,P%d) -> %d\n",
747 dev->bus->number, PCI_SLOT(dev->devfn), pin, irq);
754 * Still no IRQ? Try to lookup one...
756 if (pin && !dev->irq)
757 pcibios_lookup_irq(dev, 0);
761 static int __init pcibios_irq_init(void)
763 DBG("PCI: IRQ init\n");
765 if (pcibios_enable_irq)
768 pirq_table = pirq_find_routing_table();
770 #ifdef CONFIG_PCI_BIOS
771 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
772 pirq_table = pcibios_get_irq_routing_table();
777 if (pirq_table->exclusive_irqs) {
780 if (!(pirq_table->exclusive_irqs & (1 << i)))
781 pirq_penalty[i] += 100;
783 /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */
784 if (io_apic_assign_pci_irqs)
788 pcibios_enable_irq = pirq_enable_irq;
790 pcibios_fixup_irqs();
794 subsys_initcall(pcibios_irq_init);
797 void pcibios_penalize_isa_irq(int irq)
800 * If any ISAPnP device reports an IRQ in its list of possible
801 * IRQ's, we try to avoid assigning it to PCI devices.
803 pirq_penalty[irq] += 100;
806 int pirq_enable_irq(struct pci_dev *dev)
809 extern int interrupt_line_quirk;
810 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
811 if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
813 if (io_apic_assign_pci_irqs)
814 msg = " Probably buggy MP table.";
815 else if (pci_probe & PCI_BIOS_IRQ_SCAN)
818 msg = " Please try using pci=biosirq.";
820 /* With IDE legacy devices the IRQ lookup failure is not a problem.. */
821 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5))
824 printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
825 'A' + pin - 1, dev->slot_name, msg);
827 /* VIA bridges use interrupt line for apic/pci steering across
829 else if (interrupt_line_quirk)
830 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);