2 * Copyright (c) 2010 Samsung Electronics
4 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
16 #include <linux/sched.h>
17 #include <linux/spinlock.h>
18 #include <linux/types.h>
19 #include <linux/videodev2.h>
21 #include <media/videobuf2-core.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-mem2mem.h>
24 #include <media/v4l2-mediabus.h>
25 #include <media/s5p_fimc.h>
27 #include "regs-fimc.h"
29 #define err(fmt, args...) \
30 printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
33 #define dbg(fmt, args...) \
34 printk(KERN_DEBUG "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
36 #define dbg(fmt, args...)
39 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
40 #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
41 #define MAX_FIMC_CLOCKS 3
42 #define MODULE_NAME "s5p-fimc"
43 #define FIMC_MAX_DEVS 4
44 #define FIMC_MAX_OUT_BUFS 4
45 #define SCALER_MAX_HRATIO 64
46 #define SCALER_MAX_VRATIO 64
47 #define DMA_MIN_SIZE 8
49 /* indices to the clocks array */
61 /* for capture node */
68 #define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
69 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
71 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
72 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
82 S5P_FIMC_RGB565 = 0x10,
86 S5P_FIMC_YCBCR420 = 0x20,
91 S5P_FIMC_YCBCR444_LOCAL,
94 #define fimc_fmt_is_rgb(x) ((x) & 0x10)
96 /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
97 #define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
99 /* The embedded image effect selection */
100 #define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS
101 #define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY
102 #define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE
103 #define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE
104 #define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING
105 #define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE
107 /* The hardware context state. */
108 #define FIMC_PARAMS (1 << 0)
109 #define FIMC_SRC_ADDR (1 << 1)
110 #define FIMC_DST_ADDR (1 << 2)
111 #define FIMC_SRC_FMT (1 << 3)
112 #define FIMC_DST_FMT (1 << 4)
113 #define FIMC_CTX_M2M (1 << 5)
114 #define FIMC_CTX_CAP (1 << 6)
115 #define FIMC_CTX_SHUT (1 << 7)
117 /* Image conversion flags */
118 #define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
119 #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
120 #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
121 #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
122 #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
123 #define FIMC_SCAN_MODE_INTERLACED (1 << 2)
125 * YCbCr data dynamic range for RGB-YUV color conversion.
126 * Y/Cb/Cr: (0 ~ 255) */
127 #define FIMC_COLOR_RANGE_WIDE (0 << 3)
128 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
129 #define FIMC_COLOR_RANGE_NARROW (1 << 3)
132 #define FLIP_X_AXIS 1
133 #define FLIP_Y_AXIS 2
134 #define FLIP_XY_AXIS (FLIP_X_AXIS | FLIP_Y_AXIS)
137 * struct fimc_fmt - the driver's internal color format data
138 * @mbus_code: Media Bus pixel code, -1 if not applicable
139 * @name: format description
140 * @fourcc: the fourcc code for this format, 0 if not applicable
141 * @color: the corresponding fimc_color_fmt
142 * @depth: per plane driver's private 'number of bits per pixel'
143 * @memplanes: number of physically non-contiguous data planes
144 * @colplanes: number of physically contiguous data planes
147 enum v4l2_mbus_pixelcode mbus_code;
153 u8 depth[VIDEO_MAX_PLANES];
155 #define FMT_FLAGS_CAM (1 << 0)
156 #define FMT_FLAGS_M2M (1 << 1)
160 * struct fimc_dma_offset - pixel offset information for DMA
161 * @y_h: y value horizontal offset
162 * @y_v: y value vertical offset
163 * @cb_h: cb value horizontal offset
164 * @cb_v: cb value vertical offset
165 * @cr_h: cr value horizontal offset
166 * @cr_v: cr value vertical offset
168 struct fimc_dma_offset {
178 * struct fimc_effect - the configuration data for the "Arbitrary" image effect
180 * @pat_cb: cr value when type is "arbitrary"
181 * @pat_cr: cr value when type is "arbitrary"
190 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
192 * @scaleup_h: flag indicating scaling up horizontally
193 * @scaleup_v: flag indicating scaling up vertically
194 * @copy_mode: flag indicating transparent DMA transfer (no scaling
195 * and color format conversion)
196 * @enabled: flag indicating if the scaler is used
197 * @hfactor: horizontal shift factor
198 * @vfactor: vertical shift factor
199 * @pre_hratio: horizontal ratio of the prescaler
200 * @pre_vratio: vertical ratio of the prescaler
201 * @pre_dst_width: the prescaler's destination width
202 * @pre_dst_height: the prescaler's destination height
203 * @main_hratio: the main scaler's horizontal ratio
204 * @main_vratio: the main scaler's vertical ratio
205 * @real_width: source pixel (width - offset)
206 * @real_height: source pixel (height - offset)
209 unsigned int scaleup_h:1;
210 unsigned int scaleup_v:1;
211 unsigned int copy_mode:1;
212 unsigned int enabled:1;
226 * struct fimc_addr - the FIMC physical address set for DMA
228 * @y: luminance plane physical address
229 * @cb: Cb plane physical address
230 * @cr: Cr plane physical address
239 * struct fimc_vid_buffer - the driver's video buffer
240 * @vb: v4l videobuf buffer
241 * @paddr: precalculated physical address set
242 * @index: buffer index for the output DMA engine
244 struct fimc_vid_buffer {
245 struct vb2_buffer vb;
246 struct list_head list;
247 struct fimc_addr paddr;
252 * struct fimc_frame - source/target frame properties
253 * @f_width: image full width (virtual screen size)
254 * @f_height: image full height (virtual screen size)
255 * @o_width: original image width as set by S_FMT
256 * @o_height: original image height as set by S_FMT
257 * @offs_h: image horizontal pixel offset
258 * @offs_v: image vertical pixel offset
259 * @width: image pixel width
260 * @height: image pixel weight
261 * @paddr: image frame buffer physical addresses
262 * @buf_cnt: number of buffers depending on a color format
263 * @payload: image size in bytes (w x h x bpp)
264 * @color: color format
265 * @dma_offset: DMA offset in bytes
276 unsigned long payload[VIDEO_MAX_PLANES];
277 struct fimc_addr paddr;
278 struct fimc_dma_offset dma_offset;
279 struct fimc_fmt *fmt;
283 * struct fimc_m2m_device - v4l2 memory-to-memory device data
284 * @vfd: the video device node for v4l2 m2m mode
285 * @v4l2_dev: v4l2 device for m2m mode
286 * @m2m_dev: v4l2 memory-to-memory device data
287 * @ctx: hardware context data
288 * @refcnt: the reference counter
290 struct fimc_m2m_device {
291 struct video_device *vfd;
292 struct v4l2_device v4l2_dev;
293 struct v4l2_m2m_dev *m2m_dev;
294 struct fimc_ctx *ctx;
299 * struct fimc_vid_cap - camera capture device information
300 * @ctx: hardware context data
301 * @vfd: video device node for camera capture mode
302 * @v4l2_dev: v4l2_device struct to manage subdevs
303 * @sd: pointer to camera sensor subdevice currently in use
304 * @fmt: Media Bus format configured at selected image sensor
305 * @pending_buf_q: the pending buffer queue head
306 * @active_buf_q: the queue head of buffers scheduled in hardware
307 * @vbq: the capture am video buffer queue
308 * @active_buf_cnt: number of video buffers scheduled in hardware
309 * @buf_index: index for managing the output DMA buffers
310 * @frame_count: the frame counter for statistics
311 * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
312 * @input_index: input (camera sensor) index
313 * @refcnt: driver's private reference counter
315 struct fimc_vid_cap {
316 struct fimc_ctx *ctx;
317 struct vb2_alloc_ctx *alloc_ctx;
318 struct video_device *vfd;
319 struct v4l2_device v4l2_dev;
320 struct v4l2_subdev *sd;;
321 struct v4l2_mbus_framefmt fmt;
322 struct list_head pending_buf_q;
323 struct list_head active_buf_q;
324 struct vb2_queue vbq;
327 unsigned int frame_count;
328 unsigned int reqbufs_count;
334 * struct fimc_pix_limit - image pixel size limits in various IP configurations
336 * @scaler_en_w: max input pixel width when the scaler is enabled
337 * @scaler_dis_w: max input pixel width when the scaler is disabled
338 * @in_rot_en_h: max input width with the input rotator is on
339 * @in_rot_dis_w: max input width with the input rotator is off
340 * @out_rot_en_w: max output width with the output rotator on
341 * @out_rot_dis_w: max output width with the output rotator off
343 struct fimc_pix_limit {
353 * struct samsung_fimc_variant - camera interface variant information
355 * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
356 * @has_inp_rot: set if has input rotator
357 * @has_out_rot: set if has output rotator
358 * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
359 * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
360 * are present in this IP revision
361 * @pix_limit: pixel size constraints for the scaler
362 * @min_inp_pixsize: minimum input pixel size
363 * @min_out_pixsize: minimum output pixel size
364 * @hor_offs_align: horizontal pixel offset aligment
365 * @out_buf_count: the number of buffers in output DMA sequence
367 struct samsung_fimc_variant {
368 unsigned int pix_hoff:1;
369 unsigned int has_inp_rot:1;
370 unsigned int has_out_rot:1;
371 unsigned int has_cistatus2:1;
372 unsigned int has_mainscaler_ext:1;
373 struct fimc_pix_limit *pix_limit;
381 * struct samsung_fimc_driverdata - per device type driver data for init time.
383 * @variant: the variant information for this driver.
384 * @dev_cnt: number of fimc sub-devices available in SoC
385 * @lclk_frequency: fimc bus clock frequency
387 struct samsung_fimc_driverdata {
388 struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
389 unsigned long lclk_frequency;
396 * struct fimc_dev - abstraction for FIMC entity
398 * @slock: the spinlock protecting this data structure
399 * @lock: the mutex protecting this data structure
400 * @pdev: pointer to the FIMC platform device
401 * @pdata: pointer to the device platform data
402 * @id: FIMC device index (0..FIMC_MAX_DEVS)
403 * @num_clocks: the number of clocks managed by this device instance
404 * @clock[]: the clocks required for FIMC operation
405 * @regs: the mapped hardware registers
406 * @regs_res: the resource claimed for IO registers
407 * @irq: interrupt number of the FIMC subdevice
409 * @m2m: memory-to-memory V4L2 device information
410 * @vid_cap: camera capture device information
411 * @state: flags used to synchronize m2m and capture mode operation
416 struct platform_device *pdev;
417 struct s5p_platform_fimc *pdata;
418 struct samsung_fimc_variant *variant;
421 struct clk *clock[MAX_FIMC_CLOCKS];
423 struct resource *regs_res;
425 wait_queue_head_t irq_queue;
426 struct fimc_m2m_device m2m;
427 struct fimc_vid_cap vid_cap;
429 struct vb2_alloc_ctx *alloc_ctx;
433 * fimc_ctx - the device context data
435 * @lock: mutex protecting this data structure
436 * @s_frame: source frame properties
437 * @d_frame: destination frame properties
438 * @out_order_1p: output 1-plane YCBCR order
439 * @out_order_2p: output 2-plane YCBCR order
440 * @in_order_1p input 1-plane YCBCR order
441 * @in_order_2p: input 2-plane YCBCR order
442 * @in_path: input mode (DMA or camera)
443 * @out_path: output mode (DMA or FIFO)
444 * @scaler: image scaler properties
445 * @effect: image effect
446 * @rotation: image clockwise rotation in degrees
447 * @flip: image flip mode
448 * @flags: additional flags for image conversion
449 * @state: flags to keep track of user configuration
450 * @fimc_dev: the FIMC device this context applies to
451 * @m2m_ctx: memory-to-memory device context
455 struct fimc_frame s_frame;
456 struct fimc_frame d_frame;
461 enum fimc_datapath in_path;
462 enum fimc_datapath out_path;
463 struct fimc_scaler scaler;
464 struct fimc_effect effect;
469 struct fimc_dev *fimc_dev;
470 struct v4l2_m2m_ctx *m2m_ctx;
473 static inline bool fimc_capture_active(struct fimc_dev *fimc)
478 spin_lock_irqsave(&fimc->slock, flags);
479 ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
480 fimc->state & (1 << ST_CAPT_PEND));
481 spin_unlock_irqrestore(&fimc->slock, flags);
485 static inline void fimc_ctx_state_lock_set(u32 state, struct fimc_ctx *ctx)
489 spin_lock_irqsave(&ctx->slock, flags);
491 spin_unlock_irqrestore(&ctx->slock, flags);
494 static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
499 spin_lock_irqsave(&ctx->slock, flags);
500 ret = (ctx->state & mask) == mask;
501 spin_unlock_irqrestore(&ctx->slock, flags);
505 static inline int tiled_fmt(struct fimc_fmt *fmt)
507 return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
510 static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
512 u32 cfg = readl(dev->regs + S5P_CIGCTRL);
513 cfg |= S5P_CIGCTRL_IRQ_CLR;
514 writel(cfg, dev->regs + S5P_CIGCTRL);
517 static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
519 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
521 cfg |= S5P_CISCCTRL_SCALERSTART;
523 cfg &= ~S5P_CISCCTRL_SCALERSTART;
524 writel(cfg, dev->regs + S5P_CISCCTRL);
527 static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
529 u32 cfg = readl(dev->regs + S5P_MSCTRL);
531 cfg |= S5P_MSCTRL_ENVID;
533 cfg &= ~S5P_MSCTRL_ENVID;
534 writel(cfg, dev->regs + S5P_MSCTRL);
537 static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
539 u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
540 cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
541 writel(cfg, dev->regs + S5P_CIIMGCPT);
545 * fimc_hw_set_dma_seq - configure output DMA buffer sequence
546 * @mask: each bit corresponds to one of 32 output buffer registers set
547 * 1 to include buffer in the sequence, 0 to disable
549 * This function mask output DMA ring buffers, i.e. it allows to configure
550 * which of the output buffer address registers will be used by the DMA
553 static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)
555 writel(mask, dev->regs + S5P_CIFCNTSEQ);
558 static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
559 enum v4l2_buf_type type)
561 struct fimc_frame *frame;
563 if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
564 if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
565 frame = &ctx->s_frame;
567 return ERR_PTR(-EINVAL);
568 } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
569 frame = &ctx->d_frame;
571 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
572 "Wrong buffer/video queue type (%d)\n", type);
573 return ERR_PTR(-EINVAL);
579 /* Return an index to the buffer actually being written. */
580 static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
584 if (dev->variant->has_cistatus2) {
585 reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F;
586 return reg > 0 ? --reg : reg;
588 reg = readl(dev->regs + S5P_CISTATUS);
589 return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
590 S5P_CISTATUS_FRAMECNT_SHIFT;
594 /* -----------------------------------------------------*/
596 void fimc_hw_reset(struct fimc_dev *fimc);
597 void fimc_hw_set_rotation(struct fimc_ctx *ctx);
598 void fimc_hw_set_target_format(struct fimc_ctx *ctx);
599 void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
600 void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable);
601 void fimc_hw_en_irq(struct fimc_dev *fimc, int enable);
602 void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
603 void fimc_hw_set_mainscaler(struct fimc_ctx *ctx);
604 void fimc_hw_en_capture(struct fimc_ctx *ctx);
605 void fimc_hw_set_effect(struct fimc_ctx *ctx);
606 void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
607 void fimc_hw_set_input_path(struct fimc_ctx *ctx);
608 void fimc_hw_set_output_path(struct fimc_ctx *ctx);
609 void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
610 void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
612 int fimc_hw_set_camera_source(struct fimc_dev *fimc,
613 struct s5p_fimc_isp_info *cam);
614 int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
615 int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
616 struct s5p_fimc_isp_info *cam);
617 int fimc_hw_set_camera_type(struct fimc_dev *fimc,
618 struct s5p_fimc_isp_info *cam);
620 /* -----------------------------------------------------*/
622 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
623 struct v4l2_fmtdesc *f);
624 int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
625 struct v4l2_format *f);
626 int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
627 struct v4l2_format *f);
628 int fimc_vidioc_queryctrl(struct file *file, void *priv,
629 struct v4l2_queryctrl *qc);
630 int fimc_vidioc_g_ctrl(struct file *file, void *priv,
631 struct v4l2_control *ctrl);
633 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr);
634 int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
635 int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
637 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask);
638 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
641 int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot);
642 int fimc_set_scaler_info(struct fimc_ctx *ctx);
643 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
644 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
645 struct fimc_frame *frame, struct fimc_addr *paddr);
647 /* -----------------------------------------------------*/
649 int fimc_register_capture_device(struct fimc_dev *fimc);
650 void fimc_unregister_capture_device(struct fimc_dev *fimc);
651 int fimc_sensor_sd_init(struct fimc_dev *fimc, int index);
652 int fimc_vid_cap_buf_queue(struct fimc_dev *fimc,
653 struct fimc_vid_buffer *fimc_vb);
655 /* Locking: the caller holds fimc->slock */
656 static inline void fimc_activate_capture(struct fimc_ctx *ctx)
658 fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
659 fimc_hw_en_capture(ctx);
662 static inline void fimc_deactivate_capture(struct fimc_dev *fimc)
664 fimc_hw_en_lastirq(fimc, true);
665 fimc_hw_dis_capture(fimc);
666 fimc_hw_enable_scaler(fimc, false);
667 fimc_hw_en_lastirq(fimc, false);
671 * Add buf to the capture active buffers queue.
672 * Locking: Need to be called with fimc_dev::slock held.
674 static inline void active_queue_add(struct fimc_vid_cap *vid_cap,
675 struct fimc_vid_buffer *buf)
677 list_add_tail(&buf->list, &vid_cap->active_buf_q);
678 vid_cap->active_buf_cnt++;
682 * Pop a video buffer from the capture active buffers queue
683 * Locking: Need to be called with fimc_dev::slock held.
685 static inline struct fimc_vid_buffer *
686 active_queue_pop(struct fimc_vid_cap *vid_cap)
688 struct fimc_vid_buffer *buf;
689 buf = list_entry(vid_cap->active_buf_q.next,
690 struct fimc_vid_buffer, list);
691 list_del(&buf->list);
692 vid_cap->active_buf_cnt--;
696 /* Add video buffer to the capture pending buffers queue */
697 static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
698 struct fimc_vid_buffer *buf)
700 list_add_tail(&buf->list, &vid_cap->pending_buf_q);
703 /* Add video buffer to the capture pending buffers queue */
704 static inline struct fimc_vid_buffer *
705 pending_queue_pop(struct fimc_vid_cap *vid_cap)
707 struct fimc_vid_buffer *buf;
708 buf = list_entry(vid_cap->pending_buf_q.next,
709 struct fimc_vid_buffer, list);
710 list_del(&buf->list);
714 #endif /* FIMC_CORE_H_ */