2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
41 #define WM8994_NUM_DRC 3
42 #define WM8994_NUM_EQ 3
44 static int wm8994_drc_base[] = {
50 static int wm8994_retune_mobile_base[] = {
51 WM8994_AIF1_DAC1_EQ_GAINS_1,
52 WM8994_AIF1_DAC2_EQ_GAINS_1,
53 WM8994_AIF2_EQ_GAINS_1,
56 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
58 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
59 struct wm8994 *control = wm8994->control_data;
73 case WM8994_INTERRUPT_STATUS_1:
74 case WM8994_INTERRUPT_STATUS_2:
75 case WM8994_INTERRUPT_RAW_STATUS_2:
78 case WM8958_DSP2_PROGRAM:
79 case WM8958_DSP2_CONFIG:
80 case WM8958_DSP2_EXECCONTROL:
81 if (control->type == WM8958)
90 if (reg >= WM8994_CACHE_SIZE)
92 return wm8994_access_masks[reg].readable != 0;
95 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
97 if (reg >= WM8994_CACHE_SIZE)
101 case WM8994_SOFTWARE_RESET:
102 case WM8994_CHIP_REVISION:
103 case WM8994_DC_SERVO_1:
104 case WM8994_DC_SERVO_READBACK:
105 case WM8994_RATE_STATUS:
108 case WM8958_DSP2_EXECCONTROL:
109 case WM8958_MIC_DETECT_3:
110 case WM8994_DC_SERVO_4E:
117 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
122 BUG_ON(reg > WM8994_MAX_REGISTER);
124 if (!wm8994_volatile(codec, reg)) {
125 ret = snd_soc_cache_write(codec, reg, value);
127 dev_err(codec->dev, "Cache write to %x failed: %d\n",
131 return wm8994_reg_write(codec->control_data, reg, value);
134 static unsigned int wm8994_read(struct snd_soc_codec *codec,
140 BUG_ON(reg > WM8994_MAX_REGISTER);
142 if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
143 reg < codec->driver->reg_cache_size) {
144 ret = snd_soc_cache_read(codec, reg, &val);
148 dev_err(codec->dev, "Cache read from %x failed: %d\n",
152 return wm8994_reg_read(codec->control_data, reg);
155 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
157 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
167 switch (wm8994->sysclk[aif]) {
168 case WM8994_SYSCLK_MCLK1:
169 rate = wm8994->mclk[0];
172 case WM8994_SYSCLK_MCLK2:
174 rate = wm8994->mclk[1];
177 case WM8994_SYSCLK_FLL1:
179 rate = wm8994->fll[0].out;
182 case WM8994_SYSCLK_FLL2:
184 rate = wm8994->fll[1].out;
191 if (rate >= 13500000) {
193 reg1 |= WM8994_AIF1CLK_DIV;
195 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
199 wm8994->aifclk[aif] = rate;
201 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
202 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
208 static int configure_clock(struct snd_soc_codec *codec)
210 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
213 /* Bring up the AIF clocks first */
214 configure_aif_clock(codec, 0);
215 configure_aif_clock(codec, 1);
217 /* Then switch CLK_SYS over to the higher of them; a change
218 * can only happen as a result of a clocking change which can
219 * only be made outside of DAPM so we can safely redo the
223 /* If they're equal it doesn't matter which is used */
224 if (wm8994->aifclk[0] == wm8994->aifclk[1])
227 if (wm8994->aifclk[0] < wm8994->aifclk[1])
228 new = WM8994_SYSCLK_SRC;
232 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
234 /* If there's no change then we're done. */
238 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
240 snd_soc_dapm_sync(&codec->dapm);
245 static int check_clk_sys(struct snd_soc_dapm_widget *source,
246 struct snd_soc_dapm_widget *sink)
248 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
251 /* Check what we're currently using for CLK_SYS */
252 if (reg & WM8994_SYSCLK_SRC)
257 return strcmp(source->name, clk) == 0;
260 static const char *sidetone_hpf_text[] = {
261 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
264 static const struct soc_enum sidetone_hpf =
265 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
267 static const char *adc_hpf_text[] = {
268 "HiFi", "Voice 1", "Voice 2", "Voice 3"
271 static const struct soc_enum aif1adc1_hpf =
272 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
274 static const struct soc_enum aif1adc2_hpf =
275 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
277 static const struct soc_enum aif2adc_hpf =
278 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
280 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
281 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
282 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
283 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
284 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
286 #define WM8994_DRC_SWITCH(xname, reg, shift) \
287 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
288 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
289 .put = wm8994_put_drc_sw, \
290 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
292 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
293 struct snd_ctl_elem_value *ucontrol)
295 struct soc_mixer_control *mc =
296 (struct soc_mixer_control *)kcontrol->private_value;
297 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
300 /* Can't enable both ADC and DAC paths simultaneously */
301 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
302 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
303 WM8994_AIF1ADC1R_DRC_ENA_MASK;
305 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
307 ret = snd_soc_read(codec, mc->reg);
313 return snd_soc_put_volsw(kcontrol, ucontrol);
316 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
318 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
319 struct wm8994_pdata *pdata = wm8994->pdata;
320 int base = wm8994_drc_base[drc];
321 int cfg = wm8994->drc_cfg[drc];
324 /* Save any enables; the configuration should clear them. */
325 save = snd_soc_read(codec, base);
326 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
327 WM8994_AIF1ADC1R_DRC_ENA;
329 for (i = 0; i < WM8994_DRC_REGS; i++)
330 snd_soc_update_bits(codec, base + i, 0xffff,
331 pdata->drc_cfgs[cfg].regs[i]);
333 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
334 WM8994_AIF1ADC1L_DRC_ENA |
335 WM8994_AIF1ADC1R_DRC_ENA, save);
338 /* Icky as hell but saves code duplication */
339 static int wm8994_get_drc(const char *name)
341 if (strcmp(name, "AIF1DRC1 Mode") == 0)
343 if (strcmp(name, "AIF1DRC2 Mode") == 0)
345 if (strcmp(name, "AIF2DRC Mode") == 0)
350 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
351 struct snd_ctl_elem_value *ucontrol)
353 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
354 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
355 struct wm8994_pdata *pdata = wm8994->pdata;
356 int drc = wm8994_get_drc(kcontrol->id.name);
357 int value = ucontrol->value.integer.value[0];
362 if (value >= pdata->num_drc_cfgs)
365 wm8994->drc_cfg[drc] = value;
367 wm8994_set_drc(codec, drc);
372 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
373 struct snd_ctl_elem_value *ucontrol)
375 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
376 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
377 int drc = wm8994_get_drc(kcontrol->id.name);
379 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
384 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
386 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
387 struct wm8994_pdata *pdata = wm8994->pdata;
388 int base = wm8994_retune_mobile_base[block];
389 int iface, best, best_val, save, i, cfg;
391 if (!pdata || !wm8994->num_retune_mobile_texts)
406 /* Find the version of the currently selected configuration
407 * with the nearest sample rate. */
408 cfg = wm8994->retune_mobile_cfg[block];
411 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
412 if (strcmp(pdata->retune_mobile_cfgs[i].name,
413 wm8994->retune_mobile_texts[cfg]) == 0 &&
414 abs(pdata->retune_mobile_cfgs[i].rate
415 - wm8994->dac_rates[iface]) < best_val) {
417 best_val = abs(pdata->retune_mobile_cfgs[i].rate
418 - wm8994->dac_rates[iface]);
422 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
424 pdata->retune_mobile_cfgs[best].name,
425 pdata->retune_mobile_cfgs[best].rate,
426 wm8994->dac_rates[iface]);
428 /* The EQ will be disabled while reconfiguring it, remember the
429 * current configuration.
431 save = snd_soc_read(codec, base);
432 save &= WM8994_AIF1DAC1_EQ_ENA;
434 for (i = 0; i < WM8994_EQ_REGS; i++)
435 snd_soc_update_bits(codec, base + i, 0xffff,
436 pdata->retune_mobile_cfgs[best].regs[i]);
438 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
441 /* Icky as hell but saves code duplication */
442 static int wm8994_get_retune_mobile_block(const char *name)
444 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
446 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
448 if (strcmp(name, "AIF2 EQ Mode") == 0)
453 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
454 struct snd_ctl_elem_value *ucontrol)
456 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
457 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
458 struct wm8994_pdata *pdata = wm8994->pdata;
459 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
460 int value = ucontrol->value.integer.value[0];
465 if (value >= pdata->num_retune_mobile_cfgs)
468 wm8994->retune_mobile_cfg[block] = value;
470 wm8994_set_retune_mobile(codec, block);
475 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
476 struct snd_ctl_elem_value *ucontrol)
478 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
479 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
480 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
482 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
487 static const char *aif_chan_src_text[] = {
491 static const struct soc_enum aif1adcl_src =
492 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
494 static const struct soc_enum aif1adcr_src =
495 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
497 static const struct soc_enum aif2adcl_src =
498 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
500 static const struct soc_enum aif2adcr_src =
501 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
503 static const struct soc_enum aif1dacl_src =
504 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
506 static const struct soc_enum aif1dacr_src =
507 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
509 static const struct soc_enum aif2dacl_src =
510 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
512 static const struct soc_enum aif2dacr_src =
513 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
515 static const char *osr_text[] = {
516 "Low Power", "High Performance",
519 static const struct soc_enum dac_osr =
520 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
522 static const struct soc_enum adc_osr =
523 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
525 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
526 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
527 WM8994_AIF1_ADC1_RIGHT_VOLUME,
528 1, 119, 0, digital_tlv),
529 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
530 WM8994_AIF1_ADC2_RIGHT_VOLUME,
531 1, 119, 0, digital_tlv),
532 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
533 WM8994_AIF2_ADC_RIGHT_VOLUME,
534 1, 119, 0, digital_tlv),
536 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
537 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
538 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
539 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
541 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
542 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
543 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
544 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
546 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
547 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
548 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
549 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
550 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
551 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
553 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
554 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
556 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
557 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
558 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
560 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
561 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
562 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
564 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
565 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
566 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
568 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
569 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
570 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
572 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
574 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
576 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
578 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
580 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
581 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
583 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
584 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
586 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
587 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
589 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
590 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
592 SOC_ENUM("ADC OSR", adc_osr),
593 SOC_ENUM("DAC OSR", dac_osr),
595 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
596 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
597 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
598 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
600 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
601 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
602 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
603 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
605 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
606 6, 1, 1, wm_hubs_spkmix_tlv),
607 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
608 2, 1, 1, wm_hubs_spkmix_tlv),
610 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
611 6, 1, 1, wm_hubs_spkmix_tlv),
612 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
613 2, 1, 1, wm_hubs_spkmix_tlv),
615 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
616 10, 15, 0, wm8994_3d_tlv),
617 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
619 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
620 10, 15, 0, wm8994_3d_tlv),
621 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
623 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
624 10, 15, 0, wm8994_3d_tlv),
625 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
629 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
630 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
632 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
634 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
636 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
638 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
641 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
643 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
645 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
647 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
649 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
652 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
654 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
656 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
658 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
660 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
664 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
665 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
668 static int clk_sys_event(struct snd_soc_dapm_widget *w,
669 struct snd_kcontrol *kcontrol, int event)
671 struct snd_soc_codec *codec = w->codec;
674 case SND_SOC_DAPM_PRE_PMU:
675 return configure_clock(codec);
677 case SND_SOC_DAPM_POST_PMD:
678 configure_clock(codec);
685 static void wm8994_update_class_w(struct snd_soc_codec *codec)
687 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
689 int source = 0; /* GCC flow analysis can't track enable */
692 /* Only support direct DAC->headphone paths */
693 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
694 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
695 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
699 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
700 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
701 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
705 /* We also need the same setting for L/R and only one path */
706 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
708 case WM8994_AIF2DACL_TO_DAC1L:
709 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
710 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
712 case WM8994_AIF1DAC2L_TO_DAC1L:
713 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
714 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
716 case WM8994_AIF1DAC1L_TO_DAC1L:
717 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
718 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
721 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
726 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
728 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
733 dev_dbg(codec->dev, "Class W enabled\n");
734 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
736 WM8994_CP_DYN_SRC_SEL_MASK,
737 source | WM8994_CP_DYN_PWR);
738 wm8994->hubs.class_w = true;
741 dev_dbg(codec->dev, "Class W disabled\n");
742 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
743 WM8994_CP_DYN_PWR, 0);
744 wm8994->hubs.class_w = false;
748 static int late_enable_ev(struct snd_soc_dapm_widget *w,
749 struct snd_kcontrol *kcontrol, int event)
751 struct snd_soc_codec *codec = w->codec;
752 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
755 case SND_SOC_DAPM_PRE_PMU:
756 if (wm8994->aif1clk_enable) {
757 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
758 WM8994_AIF1CLK_ENA_MASK,
760 wm8994->aif1clk_enable = 0;
762 if (wm8994->aif2clk_enable) {
763 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
764 WM8994_AIF2CLK_ENA_MASK,
766 wm8994->aif2clk_enable = 0;
771 /* We may also have postponed startup of DSP, handle that. */
772 wm8958_aif_ev(w, kcontrol, event);
777 static int late_disable_ev(struct snd_soc_dapm_widget *w,
778 struct snd_kcontrol *kcontrol, int event)
780 struct snd_soc_codec *codec = w->codec;
781 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
784 case SND_SOC_DAPM_POST_PMD:
785 if (wm8994->aif1clk_disable) {
786 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
787 WM8994_AIF1CLK_ENA_MASK, 0);
788 wm8994->aif1clk_disable = 0;
790 if (wm8994->aif2clk_disable) {
791 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
792 WM8994_AIF2CLK_ENA_MASK, 0);
793 wm8994->aif2clk_disable = 0;
801 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
802 struct snd_kcontrol *kcontrol, int event)
804 struct snd_soc_codec *codec = w->codec;
805 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
808 case SND_SOC_DAPM_PRE_PMU:
809 wm8994->aif1clk_enable = 1;
811 case SND_SOC_DAPM_POST_PMD:
812 wm8994->aif1clk_disable = 1;
819 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
820 struct snd_kcontrol *kcontrol, int event)
822 struct snd_soc_codec *codec = w->codec;
823 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
826 case SND_SOC_DAPM_PRE_PMU:
827 wm8994->aif2clk_enable = 1;
829 case SND_SOC_DAPM_POST_PMD:
830 wm8994->aif2clk_disable = 1;
837 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
838 struct snd_kcontrol *kcontrol, int event)
840 late_enable_ev(w, kcontrol, event);
844 static int micbias_ev(struct snd_soc_dapm_widget *w,
845 struct snd_kcontrol *kcontrol, int event)
847 late_enable_ev(w, kcontrol, event);
851 static int dac_ev(struct snd_soc_dapm_widget *w,
852 struct snd_kcontrol *kcontrol, int event)
854 struct snd_soc_codec *codec = w->codec;
855 unsigned int mask = 1 << w->shift;
857 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
862 static const char *hp_mux_text[] = {
867 #define WM8994_HP_ENUM(xname, xenum) \
868 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
869 .info = snd_soc_info_enum_double, \
870 .get = snd_soc_dapm_get_enum_double, \
871 .put = wm8994_put_hp_enum, \
872 .private_value = (unsigned long)&xenum }
874 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
875 struct snd_ctl_elem_value *ucontrol)
877 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
878 struct snd_soc_dapm_widget *w = wlist->widgets[0];
879 struct snd_soc_codec *codec = w->codec;
882 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
884 wm8994_update_class_w(codec);
889 static const struct soc_enum hpl_enum =
890 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
892 static const struct snd_kcontrol_new hpl_mux =
893 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
895 static const struct soc_enum hpr_enum =
896 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
898 static const struct snd_kcontrol_new hpr_mux =
899 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
901 static const char *adc_mux_text[] = {
906 static const struct soc_enum adc_enum =
907 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
909 static const struct snd_kcontrol_new adcl_mux =
910 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
912 static const struct snd_kcontrol_new adcr_mux =
913 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
915 static const struct snd_kcontrol_new left_speaker_mixer[] = {
916 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
917 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
918 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
919 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
920 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
923 static const struct snd_kcontrol_new right_speaker_mixer[] = {
924 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
925 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
926 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
927 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
928 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
931 /* Debugging; dump chip status after DAPM transitions */
932 static int post_ev(struct snd_soc_dapm_widget *w,
933 struct snd_kcontrol *kcontrol, int event)
935 struct snd_soc_codec *codec = w->codec;
936 dev_dbg(codec->dev, "SRC status: %x\n",
938 WM8994_RATE_STATUS));
942 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
943 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
945 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
949 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
950 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
952 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
956 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
957 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
959 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
963 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
964 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
966 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
970 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
971 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
973 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
975 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
977 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
979 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
983 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
984 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
986 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
988 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
990 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
992 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
996 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
997 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
998 .info = snd_soc_info_volsw, \
999 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1000 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1002 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1003 struct snd_ctl_elem_value *ucontrol)
1005 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1006 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1007 struct snd_soc_codec *codec = w->codec;
1010 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1012 wm8994_update_class_w(codec);
1017 static const struct snd_kcontrol_new dac1l_mix[] = {
1018 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1020 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1022 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1024 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1026 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1030 static const struct snd_kcontrol_new dac1r_mix[] = {
1031 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1033 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1035 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1037 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1039 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1043 static const char *sidetone_text[] = {
1044 "ADC/DMIC1", "DMIC2",
1047 static const struct soc_enum sidetone1_enum =
1048 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1050 static const struct snd_kcontrol_new sidetone1_mux =
1051 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1053 static const struct soc_enum sidetone2_enum =
1054 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1056 static const struct snd_kcontrol_new sidetone2_mux =
1057 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1059 static const char *aif1dac_text[] = {
1060 "AIF1DACDAT", "AIF3DACDAT",
1063 static const struct soc_enum aif1dac_enum =
1064 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1066 static const struct snd_kcontrol_new aif1dac_mux =
1067 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1069 static const char *aif2dac_text[] = {
1070 "AIF2DACDAT", "AIF3DACDAT",
1073 static const struct soc_enum aif2dac_enum =
1074 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1076 static const struct snd_kcontrol_new aif2dac_mux =
1077 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1079 static const char *aif2adc_text[] = {
1080 "AIF2ADCDAT", "AIF3DACDAT",
1083 static const struct soc_enum aif2adc_enum =
1084 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1086 static const struct snd_kcontrol_new aif2adc_mux =
1087 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1089 static const char *aif3adc_text[] = {
1090 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1093 static const struct soc_enum wm8994_aif3adc_enum =
1094 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1096 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1097 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1099 static const struct soc_enum wm8958_aif3adc_enum =
1100 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1102 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1103 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1105 static const char *mono_pcm_out_text[] = {
1106 "None", "AIF2ADCL", "AIF2ADCR",
1109 static const struct soc_enum mono_pcm_out_enum =
1110 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1112 static const struct snd_kcontrol_new mono_pcm_out_mux =
1113 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1115 static const char *aif2dac_src_text[] = {
1119 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1120 static const struct soc_enum aif2dacl_src_enum =
1121 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1123 static const struct snd_kcontrol_new aif2dacl_src_mux =
1124 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1126 static const struct soc_enum aif2dacr_src_enum =
1127 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1129 static const struct snd_kcontrol_new aif2dacr_src_mux =
1130 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1132 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1133 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1134 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1135 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1136 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1138 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1139 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1140 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1141 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1142 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1143 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1144 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1145 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1146 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1147 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1149 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1150 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1151 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1152 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1153 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1154 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1155 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1156 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1157 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1158 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1160 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1163 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1164 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1165 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1166 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1167 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1168 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1169 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1170 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1171 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1172 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1175 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1176 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1177 dac_ev, SND_SOC_DAPM_PRE_PMU),
1178 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1179 dac_ev, SND_SOC_DAPM_PRE_PMU),
1180 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1181 dac_ev, SND_SOC_DAPM_PRE_PMU),
1182 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1183 dac_ev, SND_SOC_DAPM_PRE_PMU),
1186 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1187 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1188 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1189 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1190 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1193 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1194 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1195 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1196 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1197 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1200 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1201 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1202 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1205 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1206 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1207 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1208 SND_SOC_DAPM_INPUT("Clock"),
1210 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1211 SND_SOC_DAPM_PRE_PMU),
1212 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, NULL, 0),
1214 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1215 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1217 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1218 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1219 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1221 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1222 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1223 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1224 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1225 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1226 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1227 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1228 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1229 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1230 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1232 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1233 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1234 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1235 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1236 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1237 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1238 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1239 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1240 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1241 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1243 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1244 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1245 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1246 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1248 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1249 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1250 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1251 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1253 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1254 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1255 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1256 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1258 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1259 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1261 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1262 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1263 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1264 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1266 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1267 WM8994_POWER_MANAGEMENT_4, 13, 0),
1268 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1269 WM8994_POWER_MANAGEMENT_4, 12, 0),
1270 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1271 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1272 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1273 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1274 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1275 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1277 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1278 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1279 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1280 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1282 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1283 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1284 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1286 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1287 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1289 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1291 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1292 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1293 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1294 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1296 /* Power is done with the muxes since the ADC power also controls the
1297 * downsampling chain, the chip will automatically manage the analogue
1298 * specific portions.
1300 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1301 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1303 SND_SOC_DAPM_POST("Debug log", post_ev),
1306 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1307 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1310 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1311 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1312 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1313 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1314 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1317 static const struct snd_soc_dapm_route intercon[] = {
1318 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1319 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1321 { "DSP1CLK", NULL, "CLK_SYS" },
1322 { "DSP2CLK", NULL, "CLK_SYS" },
1323 { "DSPINTCLK", NULL, "CLK_SYS" },
1325 { "AIF1ADC1L", NULL, "AIF1CLK" },
1326 { "AIF1ADC1L", NULL, "DSP1CLK" },
1327 { "AIF1ADC1R", NULL, "AIF1CLK" },
1328 { "AIF1ADC1R", NULL, "DSP1CLK" },
1329 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1331 { "AIF1DAC1L", NULL, "AIF1CLK" },
1332 { "AIF1DAC1L", NULL, "DSP1CLK" },
1333 { "AIF1DAC1R", NULL, "AIF1CLK" },
1334 { "AIF1DAC1R", NULL, "DSP1CLK" },
1335 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1337 { "AIF1ADC2L", NULL, "AIF1CLK" },
1338 { "AIF1ADC2L", NULL, "DSP1CLK" },
1339 { "AIF1ADC2R", NULL, "AIF1CLK" },
1340 { "AIF1ADC2R", NULL, "DSP1CLK" },
1341 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1343 { "AIF1DAC2L", NULL, "AIF1CLK" },
1344 { "AIF1DAC2L", NULL, "DSP1CLK" },
1345 { "AIF1DAC2R", NULL, "AIF1CLK" },
1346 { "AIF1DAC2R", NULL, "DSP1CLK" },
1347 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1349 { "AIF2ADCL", NULL, "AIF2CLK" },
1350 { "AIF2ADCL", NULL, "DSP2CLK" },
1351 { "AIF2ADCR", NULL, "AIF2CLK" },
1352 { "AIF2ADCR", NULL, "DSP2CLK" },
1353 { "AIF2ADCR", NULL, "DSPINTCLK" },
1355 { "AIF2DACL", NULL, "AIF2CLK" },
1356 { "AIF2DACL", NULL, "DSP2CLK" },
1357 { "AIF2DACR", NULL, "AIF2CLK" },
1358 { "AIF2DACR", NULL, "DSP2CLK" },
1359 { "AIF2DACR", NULL, "DSPINTCLK" },
1361 { "DMIC1L", NULL, "DMIC1DAT" },
1362 { "DMIC1L", NULL, "CLK_SYS" },
1363 { "DMIC1R", NULL, "DMIC1DAT" },
1364 { "DMIC1R", NULL, "CLK_SYS" },
1365 { "DMIC2L", NULL, "DMIC2DAT" },
1366 { "DMIC2L", NULL, "CLK_SYS" },
1367 { "DMIC2R", NULL, "DMIC2DAT" },
1368 { "DMIC2R", NULL, "CLK_SYS" },
1370 { "ADCL", NULL, "AIF1CLK" },
1371 { "ADCL", NULL, "DSP1CLK" },
1372 { "ADCL", NULL, "DSPINTCLK" },
1374 { "ADCR", NULL, "AIF1CLK" },
1375 { "ADCR", NULL, "DSP1CLK" },
1376 { "ADCR", NULL, "DSPINTCLK" },
1378 { "ADCL Mux", "ADC", "ADCL" },
1379 { "ADCL Mux", "DMIC", "DMIC1L" },
1380 { "ADCR Mux", "ADC", "ADCR" },
1381 { "ADCR Mux", "DMIC", "DMIC1R" },
1383 { "DAC1L", NULL, "AIF1CLK" },
1384 { "DAC1L", NULL, "DSP1CLK" },
1385 { "DAC1L", NULL, "DSPINTCLK" },
1387 { "DAC1R", NULL, "AIF1CLK" },
1388 { "DAC1R", NULL, "DSP1CLK" },
1389 { "DAC1R", NULL, "DSPINTCLK" },
1391 { "DAC2L", NULL, "AIF2CLK" },
1392 { "DAC2L", NULL, "DSP2CLK" },
1393 { "DAC2L", NULL, "DSPINTCLK" },
1395 { "DAC2R", NULL, "AIF2DACR" },
1396 { "DAC2R", NULL, "AIF2CLK" },
1397 { "DAC2R", NULL, "DSP2CLK" },
1398 { "DAC2R", NULL, "DSPINTCLK" },
1400 { "TOCLK", NULL, "CLK_SYS" },
1403 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1404 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1405 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1407 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1408 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1409 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1411 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1412 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1413 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1415 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1416 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1417 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1419 /* Pin level routing for AIF3 */
1420 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1421 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1422 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1423 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1425 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1426 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1427 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1428 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1429 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1430 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1431 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1434 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1435 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1436 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1437 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1438 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1440 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1441 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1442 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1443 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1444 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1446 /* DAC2/AIF2 outputs */
1447 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1448 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1449 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1450 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1451 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1452 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1454 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1455 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1456 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1457 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1458 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1459 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1461 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1462 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1463 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1464 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1466 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1469 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1470 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1471 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1472 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1473 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1474 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1475 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1476 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1479 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1480 { "Left Sidetone", "DMIC2", "DMIC2L" },
1481 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1482 { "Right Sidetone", "DMIC2", "DMIC2R" },
1485 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1486 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1488 { "SPKL", "DAC1 Switch", "DAC1L" },
1489 { "SPKL", "DAC2 Switch", "DAC2L" },
1491 { "SPKR", "DAC1 Switch", "DAC1R" },
1492 { "SPKR", "DAC2 Switch", "DAC2R" },
1494 { "Left Headphone Mux", "DAC", "DAC1L" },
1495 { "Right Headphone Mux", "DAC", "DAC1R" },
1498 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1499 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1500 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1501 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1502 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1503 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1504 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1505 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1506 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1509 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1510 { "DAC1L", NULL, "DAC1L Mixer" },
1511 { "DAC1R", NULL, "DAC1R Mixer" },
1512 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1513 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1516 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1517 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1518 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1519 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1520 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1521 { "MICBIAS1", NULL, "CLK_SYS" },
1522 { "MICBIAS1", NULL, "MICBIAS Supply" },
1523 { "MICBIAS2", NULL, "CLK_SYS" },
1524 { "MICBIAS2", NULL, "MICBIAS Supply" },
1527 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1528 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1529 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1530 { "MICBIAS1", NULL, "VMID" },
1531 { "MICBIAS2", NULL, "VMID" },
1534 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1535 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1536 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1538 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1539 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1540 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1541 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1543 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1544 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1546 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1549 /* The size in bits of the FLL divide multiplied by 10
1550 * to allow rounding later */
1551 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1561 static int wm8994_get_fll_config(struct fll_div *fll,
1562 int freq_in, int freq_out)
1565 unsigned int K, Ndiv, Nmod;
1567 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1569 /* Scale the input frequency down to <= 13.5MHz */
1570 fll->clk_ref_div = 0;
1571 while (freq_in > 13500000) {
1575 if (fll->clk_ref_div > 3)
1578 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1580 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1582 while (freq_out * (fll->outdiv + 1) < 90000000) {
1584 if (fll->outdiv > 63)
1587 freq_out *= fll->outdiv + 1;
1588 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1590 if (freq_in > 1000000) {
1591 fll->fll_fratio = 0;
1592 } else if (freq_in > 256000) {
1593 fll->fll_fratio = 1;
1595 } else if (freq_in > 128000) {
1596 fll->fll_fratio = 2;
1598 } else if (freq_in > 64000) {
1599 fll->fll_fratio = 3;
1602 fll->fll_fratio = 4;
1605 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1607 /* Now, calculate N.K */
1608 Ndiv = freq_out / freq_in;
1611 Nmod = freq_out % freq_in;
1612 pr_debug("Nmod=%d\n", Nmod);
1614 /* Calculate fractional part - scale up so we can round. */
1615 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1617 do_div(Kpart, freq_in);
1619 K = Kpart & 0xFFFFFFFF;
1624 /* Move down to proper range now rounding is done */
1627 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1632 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1633 unsigned int freq_in, unsigned int freq_out)
1635 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1636 int reg_offset, ret;
1638 u16 reg, aif1, aif2;
1639 unsigned long timeout;
1641 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1642 & WM8994_AIF1CLK_ENA;
1644 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1645 & WM8994_AIF2CLK_ENA;
1662 /* Allow no source specification when stopping */
1665 src = wm8994->fll[id].src;
1667 case WM8994_FLL_SRC_MCLK1:
1668 case WM8994_FLL_SRC_MCLK2:
1669 case WM8994_FLL_SRC_LRCLK:
1670 case WM8994_FLL_SRC_BCLK:
1676 /* Are we changing anything? */
1677 if (wm8994->fll[id].src == src &&
1678 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1681 /* If we're stopping the FLL redo the old config - no
1682 * registers will actually be written but we avoid GCC flow
1683 * analysis bugs spewing warnings.
1686 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1688 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1689 wm8994->fll[id].out);
1693 /* Gate the AIF clocks while we reclock */
1694 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1695 WM8994_AIF1CLK_ENA, 0);
1696 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1697 WM8994_AIF2CLK_ENA, 0);
1699 /* We always need to disable the FLL while reconfiguring */
1700 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1701 WM8994_FLL1_ENA, 0);
1703 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1704 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1705 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1706 WM8994_FLL1_OUTDIV_MASK |
1707 WM8994_FLL1_FRATIO_MASK, reg);
1709 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1711 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1713 fll.n << WM8994_FLL1_N_SHIFT);
1715 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1716 WM8994_FLL1_REFCLK_DIV_MASK |
1717 WM8994_FLL1_REFCLK_SRC_MASK,
1718 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1721 /* Clear any pending completion from a previous failure */
1722 try_wait_for_completion(&wm8994->fll_locked[id]);
1724 /* Enable (with fractional mode if required) */
1727 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1729 reg = WM8994_FLL1_ENA;
1730 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1731 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1734 if (wm8994->fll_locked_irq) {
1735 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1736 msecs_to_jiffies(10));
1738 dev_warn(codec->dev,
1739 "Timed out waiting for FLL lock\n");
1745 wm8994->fll[id].in = freq_in;
1746 wm8994->fll[id].out = freq_out;
1747 wm8994->fll[id].src = src;
1749 /* Enable any gated AIF clocks */
1750 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1751 WM8994_AIF1CLK_ENA, aif1);
1752 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1753 WM8994_AIF2CLK_ENA, aif2);
1755 configure_clock(codec);
1760 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1762 struct completion *completion = data;
1764 complete(completion);
1769 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1771 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1772 unsigned int freq_in, unsigned int freq_out)
1774 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1777 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1778 int clk_id, unsigned int freq, int dir)
1780 struct snd_soc_codec *codec = dai->codec;
1781 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1790 /* AIF3 shares clocking with AIF1/2 */
1795 case WM8994_SYSCLK_MCLK1:
1796 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1797 wm8994->mclk[0] = freq;
1798 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1802 case WM8994_SYSCLK_MCLK2:
1803 /* TODO: Set GPIO AF */
1804 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1805 wm8994->mclk[1] = freq;
1806 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1810 case WM8994_SYSCLK_FLL1:
1811 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1812 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1815 case WM8994_SYSCLK_FLL2:
1816 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1817 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1820 case WM8994_SYSCLK_OPCLK:
1821 /* Special case - a division (times 10) is given and
1822 * no effect on main clocking.
1825 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1826 if (opclk_divs[i] == freq)
1828 if (i == ARRAY_SIZE(opclk_divs))
1830 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1831 WM8994_OPCLK_DIV_MASK, i);
1832 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1833 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1835 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1836 WM8994_OPCLK_ENA, 0);
1843 configure_clock(codec);
1848 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1849 enum snd_soc_bias_level level)
1851 struct wm8994 *control = codec->control_data;
1852 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1855 case SND_SOC_BIAS_ON:
1858 case SND_SOC_BIAS_PREPARE:
1860 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1861 WM8994_VMID_SEL_MASK, 0x2);
1864 case SND_SOC_BIAS_STANDBY:
1865 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1866 pm_runtime_get_sync(codec->dev);
1868 switch (control->type) {
1870 if (wm8994->revision < 4) {
1871 /* Tweak DC servo and DSP
1872 * configuration for improved
1874 snd_soc_write(codec, 0x102, 0x3);
1875 snd_soc_write(codec, 0x56, 0x3);
1876 snd_soc_write(codec, 0x817, 0);
1877 snd_soc_write(codec, 0x102, 0);
1882 if (wm8994->revision == 0) {
1883 /* Optimise performance for rev A */
1884 snd_soc_write(codec, 0x102, 0x3);
1885 snd_soc_write(codec, 0xcb, 0x81);
1886 snd_soc_write(codec, 0x817, 0);
1887 snd_soc_write(codec, 0x102, 0);
1889 snd_soc_update_bits(codec,
1890 WM8958_CHARGE_PUMP_2,
1897 /* Discharge LINEOUT1 & 2 */
1898 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1899 WM8994_LINEOUT1_DISCH |
1900 WM8994_LINEOUT2_DISCH,
1901 WM8994_LINEOUT1_DISCH |
1902 WM8994_LINEOUT2_DISCH);
1904 /* Startup bias, VMID ramp & buffer */
1905 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1906 WM8994_STARTUP_BIAS_ENA |
1907 WM8994_VMID_BUF_ENA |
1908 WM8994_VMID_RAMP_MASK,
1909 WM8994_STARTUP_BIAS_ENA |
1910 WM8994_VMID_BUF_ENA |
1911 (0x11 << WM8994_VMID_RAMP_SHIFT));
1913 /* Main bias enable, VMID=2x40k */
1914 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1916 WM8994_VMID_SEL_MASK,
1917 WM8994_BIAS_ENA | 0x2);
1923 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1924 WM8994_VMID_SEL_MASK, 0x4);
1928 case SND_SOC_BIAS_OFF:
1929 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1930 /* Switch over to startup biases */
1931 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1933 WM8994_STARTUP_BIAS_ENA |
1934 WM8994_VMID_BUF_ENA |
1935 WM8994_VMID_RAMP_MASK,
1937 WM8994_STARTUP_BIAS_ENA |
1938 WM8994_VMID_BUF_ENA |
1939 (1 << WM8994_VMID_RAMP_SHIFT));
1941 /* Disable main biases */
1942 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1944 WM8994_VMID_SEL_MASK, 0);
1946 /* Discharge line */
1947 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1948 WM8994_LINEOUT1_DISCH |
1949 WM8994_LINEOUT2_DISCH,
1950 WM8994_LINEOUT1_DISCH |
1951 WM8994_LINEOUT2_DISCH);
1955 /* Switch off startup biases */
1956 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1958 WM8994_STARTUP_BIAS_ENA |
1959 WM8994_VMID_BUF_ENA |
1960 WM8994_VMID_RAMP_MASK, 0);
1962 wm8994->cur_fw = NULL;
1964 pm_runtime_put(codec->dev);
1968 codec->dapm.bias_level = level;
1972 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1974 struct snd_soc_codec *codec = dai->codec;
1975 struct wm8994 *control = codec->control_data;
1983 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1984 aif1_reg = WM8994_AIF1_CONTROL_1;
1987 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1988 aif1_reg = WM8994_AIF2_CONTROL_1;
1994 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1995 case SND_SOC_DAIFMT_CBS_CFS:
1997 case SND_SOC_DAIFMT_CBM_CFM:
1998 ms = WM8994_AIF1_MSTR;
2004 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2005 case SND_SOC_DAIFMT_DSP_B:
2006 aif1 |= WM8994_AIF1_LRCLK_INV;
2007 case SND_SOC_DAIFMT_DSP_A:
2010 case SND_SOC_DAIFMT_I2S:
2013 case SND_SOC_DAIFMT_RIGHT_J:
2015 case SND_SOC_DAIFMT_LEFT_J:
2022 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2023 case SND_SOC_DAIFMT_DSP_A:
2024 case SND_SOC_DAIFMT_DSP_B:
2025 /* frame inversion not valid for DSP modes */
2026 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2027 case SND_SOC_DAIFMT_NB_NF:
2029 case SND_SOC_DAIFMT_IB_NF:
2030 aif1 |= WM8994_AIF1_BCLK_INV;
2037 case SND_SOC_DAIFMT_I2S:
2038 case SND_SOC_DAIFMT_RIGHT_J:
2039 case SND_SOC_DAIFMT_LEFT_J:
2040 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2041 case SND_SOC_DAIFMT_NB_NF:
2043 case SND_SOC_DAIFMT_IB_IF:
2044 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2046 case SND_SOC_DAIFMT_IB_NF:
2047 aif1 |= WM8994_AIF1_BCLK_INV;
2049 case SND_SOC_DAIFMT_NB_IF:
2050 aif1 |= WM8994_AIF1_LRCLK_INV;
2060 /* The AIF2 format configuration needs to be mirrored to AIF3
2061 * on WM8958 if it's in use so just do it all the time. */
2062 if (control->type == WM8958 && dai->id == 2)
2063 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2064 WM8994_AIF1_LRCLK_INV |
2065 WM8958_AIF3_FMT_MASK, aif1);
2067 snd_soc_update_bits(codec, aif1_reg,
2068 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2069 WM8994_AIF1_FMT_MASK,
2071 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2093 static int fs_ratios[] = {
2094 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2097 static int bclk_divs[] = {
2098 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2099 640, 880, 960, 1280, 1760, 1920
2102 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2103 struct snd_pcm_hw_params *params,
2104 struct snd_soc_dai *dai)
2106 struct snd_soc_codec *codec = dai->codec;
2107 struct wm8994 *control = codec->control_data;
2108 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2119 int id = dai->id - 1;
2121 int i, cur_val, best_val, bclk_rate, best;
2125 aif1_reg = WM8994_AIF1_CONTROL_1;
2126 aif2_reg = WM8994_AIF1_CONTROL_2;
2127 bclk_reg = WM8994_AIF1_BCLK;
2128 rate_reg = WM8994_AIF1_RATE;
2129 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2130 wm8994->lrclk_shared[0]) {
2131 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2133 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2134 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2138 aif1_reg = WM8994_AIF2_CONTROL_1;
2139 aif2_reg = WM8994_AIF2_CONTROL_2;
2140 bclk_reg = WM8994_AIF2_BCLK;
2141 rate_reg = WM8994_AIF2_RATE;
2142 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2143 wm8994->lrclk_shared[1]) {
2144 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2146 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2147 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2151 switch (control->type) {
2153 aif1_reg = WM8958_AIF3_CONTROL_1;
2162 bclk_rate = params_rate(params) * 2;
2163 switch (params_format(params)) {
2164 case SNDRV_PCM_FORMAT_S16_LE:
2167 case SNDRV_PCM_FORMAT_S20_3LE:
2171 case SNDRV_PCM_FORMAT_S24_LE:
2175 case SNDRV_PCM_FORMAT_S32_LE:
2183 /* Try to find an appropriate sample rate; look for an exact match. */
2184 for (i = 0; i < ARRAY_SIZE(srs); i++)
2185 if (srs[i].rate == params_rate(params))
2187 if (i == ARRAY_SIZE(srs))
2189 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2191 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2192 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2193 dai->id, wm8994->aifclk[id], bclk_rate);
2195 if (params_channels(params) == 1 &&
2196 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2197 aif2 |= WM8994_AIF1_MONO;
2199 if (wm8994->aifclk[id] == 0) {
2200 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2204 /* AIFCLK/fs ratio; look for a close match in either direction */
2206 best_val = abs((fs_ratios[0] * params_rate(params))
2207 - wm8994->aifclk[id]);
2208 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2209 cur_val = abs((fs_ratios[i] * params_rate(params))
2210 - wm8994->aifclk[id]);
2211 if (cur_val >= best_val)
2216 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2217 dai->id, fs_ratios[best]);
2220 /* We may not get quite the right frequency if using
2221 * approximate clocks so look for the closest match that is
2222 * higher than the target (we need to ensure that there enough
2223 * BCLKs to clock out the samples).
2226 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2227 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2228 if (cur_val < 0) /* BCLK table is sorted */
2232 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2233 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2234 bclk_divs[best], bclk_rate);
2235 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2237 lrclk = bclk_rate / params_rate(params);
2238 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2239 lrclk, bclk_rate / lrclk);
2241 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2242 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2243 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2244 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2246 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2247 WM8994_AIF1CLK_RATE_MASK, rate_val);
2249 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2252 wm8994->dac_rates[0] = params_rate(params);
2253 wm8994_set_retune_mobile(codec, 0);
2254 wm8994_set_retune_mobile(codec, 1);
2257 wm8994->dac_rates[1] = params_rate(params);
2258 wm8994_set_retune_mobile(codec, 2);
2266 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2267 struct snd_pcm_hw_params *params,
2268 struct snd_soc_dai *dai)
2270 struct snd_soc_codec *codec = dai->codec;
2271 struct wm8994 *control = codec->control_data;
2277 switch (control->type) {
2279 aif1_reg = WM8958_AIF3_CONTROL_1;
2288 switch (params_format(params)) {
2289 case SNDRV_PCM_FORMAT_S16_LE:
2291 case SNDRV_PCM_FORMAT_S20_3LE:
2294 case SNDRV_PCM_FORMAT_S24_LE:
2297 case SNDRV_PCM_FORMAT_S32_LE:
2304 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2307 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2308 struct snd_soc_dai *dai)
2310 struct snd_soc_codec *codec = dai->codec;
2315 rate_reg = WM8994_AIF1_RATE;
2318 rate_reg = WM8994_AIF1_RATE;
2324 /* If the DAI is idle then configure the divider tree for the
2325 * lowest output rate to save a little power if the clock is
2326 * still active (eg, because it is system clock).
2328 if (rate_reg && !dai->playback_active && !dai->capture_active)
2329 snd_soc_update_bits(codec, rate_reg,
2330 WM8994_AIF1_SR_MASK |
2331 WM8994_AIF1CLK_RATE_MASK, 0x9);
2334 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2336 struct snd_soc_codec *codec = codec_dai->codec;
2340 switch (codec_dai->id) {
2342 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2345 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2352 reg = WM8994_AIF1DAC1_MUTE;
2356 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2361 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2363 struct snd_soc_codec *codec = codec_dai->codec;
2366 switch (codec_dai->id) {
2368 reg = WM8994_AIF1_MASTER_SLAVE;
2369 mask = WM8994_AIF1_TRI;
2372 reg = WM8994_AIF2_MASTER_SLAVE;
2373 mask = WM8994_AIF2_TRI;
2376 reg = WM8994_POWER_MANAGEMENT_6;
2377 mask = WM8994_AIF3_TRI;
2388 return snd_soc_update_bits(codec, reg, mask, val);
2391 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2393 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2394 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2396 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2397 .set_sysclk = wm8994_set_dai_sysclk,
2398 .set_fmt = wm8994_set_dai_fmt,
2399 .hw_params = wm8994_hw_params,
2400 .shutdown = wm8994_aif_shutdown,
2401 .digital_mute = wm8994_aif_mute,
2402 .set_pll = wm8994_set_fll,
2403 .set_tristate = wm8994_set_tristate,
2406 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2407 .set_sysclk = wm8994_set_dai_sysclk,
2408 .set_fmt = wm8994_set_dai_fmt,
2409 .hw_params = wm8994_hw_params,
2410 .shutdown = wm8994_aif_shutdown,
2411 .digital_mute = wm8994_aif_mute,
2412 .set_pll = wm8994_set_fll,
2413 .set_tristate = wm8994_set_tristate,
2416 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2417 .hw_params = wm8994_aif3_hw_params,
2418 .set_tristate = wm8994_set_tristate,
2421 static struct snd_soc_dai_driver wm8994_dai[] = {
2423 .name = "wm8994-aif1",
2426 .stream_name = "AIF1 Playback",
2429 .rates = WM8994_RATES,
2430 .formats = WM8994_FORMATS,
2433 .stream_name = "AIF1 Capture",
2436 .rates = WM8994_RATES,
2437 .formats = WM8994_FORMATS,
2439 .ops = &wm8994_aif1_dai_ops,
2442 .name = "wm8994-aif2",
2445 .stream_name = "AIF2 Playback",
2448 .rates = WM8994_RATES,
2449 .formats = WM8994_FORMATS,
2452 .stream_name = "AIF2 Capture",
2455 .rates = WM8994_RATES,
2456 .formats = WM8994_FORMATS,
2458 .ops = &wm8994_aif2_dai_ops,
2461 .name = "wm8994-aif3",
2464 .stream_name = "AIF3 Playback",
2467 .rates = WM8994_RATES,
2468 .formats = WM8994_FORMATS,
2471 .stream_name = "AIF3 Capture",
2474 .rates = WM8994_RATES,
2475 .formats = WM8994_FORMATS,
2477 .ops = &wm8994_aif3_dai_ops,
2482 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2484 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2485 struct wm8994 *control = codec->control_data;
2488 switch (control->type) {
2490 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2493 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2494 WM8958_MICD_ENA, 0);
2498 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2499 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2500 sizeof(struct wm8994_fll_config));
2501 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2503 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2507 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2512 static int wm8994_resume(struct snd_soc_codec *codec)
2514 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2515 struct wm8994 *control = codec->control_data;
2517 unsigned int val, mask;
2519 if (wm8994->revision < 4) {
2520 /* force a HW read */
2521 val = wm8994_reg_read(codec->control_data,
2522 WM8994_POWER_MANAGEMENT_5);
2524 /* modify the cache only */
2525 codec->cache_only = 1;
2526 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2527 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2529 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2531 codec->cache_only = 0;
2534 /* Restore the registers */
2535 ret = snd_soc_cache_sync(codec);
2537 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2539 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2541 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2542 if (!wm8994->fll_suspend[i].out)
2545 ret = _wm8994_set_fll(codec, i + 1,
2546 wm8994->fll_suspend[i].src,
2547 wm8994->fll_suspend[i].in,
2548 wm8994->fll_suspend[i].out);
2550 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2554 switch (control->type) {
2556 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2557 snd_soc_update_bits(codec, WM8994_MICBIAS,
2558 WM8994_MICD_ENA, WM8994_MICD_ENA);
2561 if (wm8994->jack_cb)
2562 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2563 WM8958_MICD_ENA, WM8958_MICD_ENA);
2570 #define wm8994_suspend NULL
2571 #define wm8994_resume NULL
2574 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2576 struct snd_soc_codec *codec = wm8994->codec;
2577 struct wm8994_pdata *pdata = wm8994->pdata;
2578 struct snd_kcontrol_new controls[] = {
2579 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2580 wm8994->retune_mobile_enum,
2581 wm8994_get_retune_mobile_enum,
2582 wm8994_put_retune_mobile_enum),
2583 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2584 wm8994->retune_mobile_enum,
2585 wm8994_get_retune_mobile_enum,
2586 wm8994_put_retune_mobile_enum),
2587 SOC_ENUM_EXT("AIF2 EQ Mode",
2588 wm8994->retune_mobile_enum,
2589 wm8994_get_retune_mobile_enum,
2590 wm8994_put_retune_mobile_enum),
2595 /* We need an array of texts for the enum API but the number
2596 * of texts is likely to be less than the number of
2597 * configurations due to the sample rate dependency of the
2598 * configurations. */
2599 wm8994->num_retune_mobile_texts = 0;
2600 wm8994->retune_mobile_texts = NULL;
2601 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2602 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2603 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2604 wm8994->retune_mobile_texts[j]) == 0)
2608 if (j != wm8994->num_retune_mobile_texts)
2611 /* Expand the array... */
2612 t = krealloc(wm8994->retune_mobile_texts,
2614 (wm8994->num_retune_mobile_texts + 1),
2619 /* ...store the new entry... */
2620 t[wm8994->num_retune_mobile_texts] =
2621 pdata->retune_mobile_cfgs[i].name;
2623 /* ...and remember the new version. */
2624 wm8994->num_retune_mobile_texts++;
2625 wm8994->retune_mobile_texts = t;
2628 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2629 wm8994->num_retune_mobile_texts);
2631 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2632 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2634 ret = snd_soc_add_controls(wm8994->codec, controls,
2635 ARRAY_SIZE(controls));
2637 dev_err(wm8994->codec->dev,
2638 "Failed to add ReTune Mobile controls: %d\n", ret);
2641 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2643 struct snd_soc_codec *codec = wm8994->codec;
2644 struct wm8994_pdata *pdata = wm8994->pdata;
2650 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2651 pdata->lineout2_diff,
2656 pdata->micbias1_lvl,
2657 pdata->micbias2_lvl);
2659 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2661 if (pdata->num_drc_cfgs) {
2662 struct snd_kcontrol_new controls[] = {
2663 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2664 wm8994_get_drc_enum, wm8994_put_drc_enum),
2665 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2666 wm8994_get_drc_enum, wm8994_put_drc_enum),
2667 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2668 wm8994_get_drc_enum, wm8994_put_drc_enum),
2671 /* We need an array of texts for the enum API */
2672 wm8994->drc_texts = kmalloc(sizeof(char *)
2673 * pdata->num_drc_cfgs, GFP_KERNEL);
2674 if (!wm8994->drc_texts) {
2675 dev_err(wm8994->codec->dev,
2676 "Failed to allocate %d DRC config texts\n",
2677 pdata->num_drc_cfgs);
2681 for (i = 0; i < pdata->num_drc_cfgs; i++)
2682 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2684 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2685 wm8994->drc_enum.texts = wm8994->drc_texts;
2687 ret = snd_soc_add_controls(wm8994->codec, controls,
2688 ARRAY_SIZE(controls));
2690 dev_err(wm8994->codec->dev,
2691 "Failed to add DRC mode controls: %d\n", ret);
2693 for (i = 0; i < WM8994_NUM_DRC; i++)
2694 wm8994_set_drc(codec, i);
2697 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2698 pdata->num_retune_mobile_cfgs);
2700 if (pdata->num_retune_mobile_cfgs)
2701 wm8994_handle_retune_mobile_pdata(wm8994);
2703 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2704 ARRAY_SIZE(wm8994_eq_controls));
2706 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2707 if (pdata->micbias[i]) {
2708 snd_soc_write(codec, WM8958_MICBIAS1 + i,
2709 pdata->micbias[i] & 0xffff);
2715 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2717 * @codec: WM8994 codec
2718 * @jack: jack to report detection events on
2719 * @micbias: microphone bias to detect on
2720 * @det: value to report for presence detection
2721 * @shrt: value to report for short detection
2723 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2724 * being used to bring out signals to the processor then only platform
2725 * data configuration is needed for WM8994 and processor GPIOs should
2726 * be configured using snd_soc_jack_add_gpios() instead.
2728 * Configuration of detection levels is available via the micbias1_lvl
2729 * and micbias2_lvl platform data members.
2731 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2732 int micbias, int det, int shrt)
2734 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2735 struct wm8994_micdet *micdet;
2736 struct wm8994 *control = codec->control_data;
2739 if (control->type != WM8994)
2744 micdet = &wm8994->micdet[0];
2747 micdet = &wm8994->micdet[1];
2753 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2754 micbias, det, shrt);
2756 /* Store the configuration */
2757 micdet->jack = jack;
2759 micdet->shrt = shrt;
2761 /* If either of the jacks is set up then enable detection */
2762 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2763 reg = WM8994_MICD_ENA;
2767 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2771 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2773 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2775 struct wm8994_priv *priv = data;
2776 struct snd_soc_codec *codec = priv->codec;
2780 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2781 trace_snd_soc_jack_irq(dev_name(codec->dev));
2784 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2786 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2791 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2794 if (reg & WM8994_MIC1_DET_STS)
2795 report |= priv->micdet[0].det;
2796 if (reg & WM8994_MIC1_SHRT_STS)
2797 report |= priv->micdet[0].shrt;
2798 snd_soc_jack_report(priv->micdet[0].jack, report,
2799 priv->micdet[0].det | priv->micdet[0].shrt);
2802 if (reg & WM8994_MIC2_DET_STS)
2803 report |= priv->micdet[1].det;
2804 if (reg & WM8994_MIC2_SHRT_STS)
2805 report |= priv->micdet[1].shrt;
2806 snd_soc_jack_report(priv->micdet[1].jack, report,
2807 priv->micdet[1].det | priv->micdet[1].shrt);
2812 /* Default microphone detection handler for WM8958 - the user can
2813 * override this if they wish.
2815 static void wm8958_default_micdet(u16 status, void *data)
2817 struct snd_soc_codec *codec = data;
2818 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2821 /* If nothing present then clear our statuses */
2822 if (!(status & WM8958_MICD_STS))
2825 report = SND_JACK_MICROPHONE;
2827 /* Everything else is buttons; just assign slots */
2829 report |= SND_JACK_BTN_0;
2832 snd_soc_jack_report(wm8994->micdet[0].jack, report,
2833 SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
2837 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2839 * @codec: WM8958 codec
2840 * @jack: jack to report detection events on
2842 * Enable microphone detection functionality for the WM8958. By
2843 * default simple detection which supports the detection of up to 6
2844 * buttons plus video and microphone functionality is supported.
2846 * The WM8958 has an advanced jack detection facility which is able to
2847 * support complex accessory detection, especially when used in
2848 * conjunction with external circuitry. In order to provide maximum
2849 * flexiblity a callback is provided which allows a completely custom
2850 * detection algorithm.
2852 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2853 wm8958_micdet_cb cb, void *cb_data)
2855 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2856 struct wm8994 *control = codec->control_data;
2858 if (control->type != WM8958)
2863 dev_dbg(codec->dev, "Using default micdet callback\n");
2864 cb = wm8958_default_micdet;
2868 wm8994->micdet[0].jack = jack;
2869 wm8994->jack_cb = cb;
2870 wm8994->jack_cb_data = cb_data;
2872 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2873 WM8958_MICD_ENA, WM8958_MICD_ENA);
2875 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2876 WM8958_MICD_ENA, 0);
2881 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2883 static irqreturn_t wm8958_mic_irq(int irq, void *data)
2885 struct wm8994_priv *wm8994 = data;
2886 struct snd_soc_codec *codec = wm8994->codec;
2889 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2891 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2896 if (!(reg & WM8958_MICD_VALID)) {
2897 dev_dbg(codec->dev, "Mic detect data not valid\n");
2901 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2902 trace_snd_soc_jack_irq(dev_name(codec->dev));
2905 if (wm8994->jack_cb)
2906 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2908 dev_warn(codec->dev, "Accessory detection with no callback\n");
2914 static irqreturn_t wm8994_fifo_error(int irq, void *data)
2916 struct snd_soc_codec *codec = data;
2918 dev_err(codec->dev, "FIFO error\n");
2923 static int wm8994_codec_probe(struct snd_soc_codec *codec)
2925 struct wm8994 *control;
2926 struct wm8994_priv *wm8994;
2927 struct snd_soc_dapm_context *dapm = &codec->dapm;
2930 codec->control_data = dev_get_drvdata(codec->dev->parent);
2931 control = codec->control_data;
2933 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2936 snd_soc_codec_set_drvdata(codec, wm8994);
2938 wm8994->pdata = dev_get_platdata(codec->dev->parent);
2939 wm8994->codec = codec;
2941 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2942 init_completion(&wm8994->fll_locked[i]);
2944 if (wm8994->pdata && wm8994->pdata->micdet_irq)
2945 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
2946 else if (wm8994->pdata && wm8994->pdata->irq_base)
2947 wm8994->micdet_irq = wm8994->pdata->irq_base +
2948 WM8994_IRQ_MIC1_DET;
2950 pm_runtime_enable(codec->dev);
2951 pm_runtime_resume(codec->dev);
2953 /* Read our current status back from the chip - we don't want to
2954 * reset as this may interfere with the GPIO or LDO operation. */
2955 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
2956 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
2959 ret = wm8994_reg_read(codec->control_data, i);
2963 ret = snd_soc_cache_write(codec, i, ret);
2966 "Failed to initialise cache for 0x%x: %d\n",
2972 /* Set revision-specific configuration */
2973 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
2974 switch (control->type) {
2976 switch (wm8994->revision) {
2979 wm8994->hubs.dcs_codes_l = -5;
2980 wm8994->hubs.dcs_codes_r = -5;
2981 wm8994->hubs.hp_startup_mode = 1;
2982 wm8994->hubs.dcs_readback_mode = 1;
2983 wm8994->hubs.series_startup = 1;
2986 wm8994->hubs.dcs_readback_mode = 2;
2992 wm8994->hubs.dcs_readback_mode = 1;
2999 wm8994_request_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR,
3000 wm8994_fifo_error, "FIFO error", codec);
3002 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3003 wm_hubs_dcs_done, "DC servo done",
3006 wm8994->hubs.dcs_done_irq = true;
3008 switch (control->type) {
3010 if (wm8994->micdet_irq) {
3011 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3013 IRQF_TRIGGER_RISING,
3017 dev_warn(codec->dev,
3018 "Failed to request Mic1 detect IRQ: %d\n",
3022 ret = wm8994_request_irq(codec->control_data,
3023 WM8994_IRQ_MIC1_SHRT,
3024 wm8994_mic_irq, "Mic 1 short",
3027 dev_warn(codec->dev,
3028 "Failed to request Mic1 short IRQ: %d\n",
3031 ret = wm8994_request_irq(codec->control_data,
3032 WM8994_IRQ_MIC2_DET,
3033 wm8994_mic_irq, "Mic 2 detect",
3036 dev_warn(codec->dev,
3037 "Failed to request Mic2 detect IRQ: %d\n",
3040 ret = wm8994_request_irq(codec->control_data,
3041 WM8994_IRQ_MIC2_SHRT,
3042 wm8994_mic_irq, "Mic 2 short",
3045 dev_warn(codec->dev,
3046 "Failed to request Mic2 short IRQ: %d\n",
3051 if (wm8994->micdet_irq) {
3052 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3054 IRQF_TRIGGER_RISING,
3058 dev_warn(codec->dev,
3059 "Failed to request Mic detect IRQ: %d\n",
3064 wm8994->fll_locked_irq = true;
3065 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3066 ret = wm8994_request_irq(codec->control_data,
3067 WM8994_IRQ_FLL1_LOCK + i,
3068 wm8994_fll_locked_irq, "FLL lock",
3069 &wm8994->fll_locked[i]);
3071 wm8994->fll_locked_irq = false;
3074 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3075 * configured on init - if a system wants to do this dynamically
3076 * at runtime we can deal with that then.
3078 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3080 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3083 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3084 wm8994->lrclk_shared[0] = 1;
3085 wm8994_dai[0].symmetric_rates = 1;
3087 wm8994->lrclk_shared[0] = 0;
3090 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3092 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3095 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3096 wm8994->lrclk_shared[1] = 1;
3097 wm8994_dai[1].symmetric_rates = 1;
3099 wm8994->lrclk_shared[1] = 0;
3102 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3104 /* Latch volume updates (right only; we always do left then right). */
3105 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3106 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3107 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3108 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3109 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3110 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3111 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3112 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3113 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3114 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3115 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3116 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3117 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3118 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3119 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3120 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3121 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3122 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3123 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3124 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3125 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3126 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3127 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3128 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3129 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3130 WM8994_DAC1_VU, WM8994_DAC1_VU);
3131 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3132 WM8994_DAC1_VU, WM8994_DAC1_VU);
3133 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3134 WM8994_DAC2_VU, WM8994_DAC2_VU);
3135 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3136 WM8994_DAC2_VU, WM8994_DAC2_VU);
3138 /* Set the low bit of the 3D stereo depth so TLV matches */
3139 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3140 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3141 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3142 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3143 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3144 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3145 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3146 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3147 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3149 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3150 * use this; it only affects behaviour on idle TDM clock
3152 switch (control->type) {
3155 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3156 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3162 wm8994_update_class_w(codec);
3164 wm8994_handle_pdata(wm8994);
3166 wm_hubs_add_analogue_controls(codec);
3167 snd_soc_add_controls(codec, wm8994_snd_controls,
3168 ARRAY_SIZE(wm8994_snd_controls));
3169 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3170 ARRAY_SIZE(wm8994_dapm_widgets));
3172 switch (control->type) {
3174 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3175 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3176 if (wm8994->revision < 4) {
3177 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3178 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3179 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3180 ARRAY_SIZE(wm8994_adc_revd_widgets));
3181 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3182 ARRAY_SIZE(wm8994_dac_revd_widgets));
3184 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3185 ARRAY_SIZE(wm8994_lateclk_widgets));
3186 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3187 ARRAY_SIZE(wm8994_adc_widgets));
3188 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3189 ARRAY_SIZE(wm8994_dac_widgets));
3193 snd_soc_add_controls(codec, wm8958_snd_controls,
3194 ARRAY_SIZE(wm8958_snd_controls));
3195 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3196 ARRAY_SIZE(wm8958_dapm_widgets));
3197 if (wm8994->revision < 1) {
3198 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3199 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3200 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3201 ARRAY_SIZE(wm8994_adc_revd_widgets));
3202 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3203 ARRAY_SIZE(wm8994_dac_revd_widgets));
3205 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3206 ARRAY_SIZE(wm8994_lateclk_widgets));
3207 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3208 ARRAY_SIZE(wm8994_adc_widgets));
3209 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3210 ARRAY_SIZE(wm8994_dac_widgets));
3216 wm_hubs_add_analogue_routes(codec, 0, 0);
3217 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3219 switch (control->type) {
3221 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3222 ARRAY_SIZE(wm8994_intercon));
3224 if (wm8994->revision < 4) {
3225 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3226 ARRAY_SIZE(wm8994_revd_intercon));
3227 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3228 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3230 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3231 ARRAY_SIZE(wm8994_lateclk_intercon));
3235 if (wm8994->revision < 1) {
3236 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3237 ARRAY_SIZE(wm8994_revd_intercon));
3238 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3239 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3241 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3242 ARRAY_SIZE(wm8994_lateclk_intercon));
3243 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3244 ARRAY_SIZE(wm8958_intercon));
3247 wm8958_dsp2_init(codec);
3254 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3255 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3256 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3257 if (wm8994->micdet_irq)
3258 free_irq(wm8994->micdet_irq, wm8994);
3259 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3260 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3261 &wm8994->fll_locked[i]);
3262 wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3264 wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3270 static int wm8994_codec_remove(struct snd_soc_codec *codec)
3272 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3273 struct wm8994 *control = codec->control_data;
3276 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3278 pm_runtime_disable(codec->dev);
3280 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3281 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3282 &wm8994->fll_locked[i]);
3284 wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3286 wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3288 switch (control->type) {
3290 if (wm8994->micdet_irq)
3291 free_irq(wm8994->micdet_irq, wm8994);
3292 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3294 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3296 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3301 if (wm8994->micdet_irq)
3302 free_irq(wm8994->micdet_irq, wm8994);
3306 release_firmware(wm8994->mbc);
3307 if (wm8994->mbc_vss)
3308 release_firmware(wm8994->mbc_vss);
3310 release_firmware(wm8994->enh_eq);
3311 kfree(wm8994->retune_mobile_texts);
3312 kfree(wm8994->drc_texts);
3318 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3319 .probe = wm8994_codec_probe,
3320 .remove = wm8994_codec_remove,
3321 .suspend = wm8994_suspend,
3322 .resume = wm8994_resume,
3323 .read = wm8994_read,
3324 .write = wm8994_write,
3325 .readable_register = wm8994_readable,
3326 .volatile_register = wm8994_volatile,
3327 .set_bias_level = wm8994_set_bias_level,
3329 .reg_cache_size = WM8994_CACHE_SIZE,
3330 .reg_cache_default = wm8994_reg_defaults,
3332 .compress_type = SND_SOC_RBTREE_COMPRESSION,
3335 static int __devinit wm8994_probe(struct platform_device *pdev)
3337 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3338 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3341 static int __devexit wm8994_remove(struct platform_device *pdev)
3343 snd_soc_unregister_codec(&pdev->dev);
3347 static struct platform_driver wm8994_codec_driver = {
3349 .name = "wm8994-codec",
3350 .owner = THIS_MODULE,
3352 .probe = wm8994_probe,
3353 .remove = __devexit_p(wm8994_remove),
3356 static __init int wm8994_init(void)
3358 return platform_driver_register(&wm8994_codec_driver);
3360 module_init(wm8994_init);
3362 static __exit void wm8994_exit(void)
3364 platform_driver_unregister(&wm8994_codec_driver);
3366 module_exit(wm8994_exit);
3369 MODULE_DESCRIPTION("ASoC WM8994 driver");
3370 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3371 MODULE_LICENSE("GPL");
3372 MODULE_ALIAS("platform:wm8994-codec");