drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47
  48 #ifdef RTL8169_DEBUG
  49 #define assert(expr) \
  50         if (!(expr)) {                                  \
  51                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  52                 #expr,__FILE__,__func__,__LINE__);              \
  53         }
  54 #define dprintk(fmt, args...) \
  55         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  56 #else
  57 #define assert(expr) do {} while (0)
  58 #define dprintk(fmt, args...)   do {} while (0)
  59 #endif /* RTL8169_DEBUG */
  60
  61 #define R8169_MSG_DEFAULT \
  62         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  63
  64 #define TX_SLOTS_AVAIL(tp) \
  65         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  66
  67 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  68 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  69         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  70
  71 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  72    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  73 static const int multicast_filter_limit = 32;
  74
  75 #define MAX_READ_REQUEST_SHIFT  12
  76 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  77 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  78 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  79
  80 #define R8169_REGS_SIZE         256
  81 #define R8169_NAPI_WEIGHT       64
  82 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  83 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  84 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  85 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  86 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  87
  88 #define RTL8169_TX_TIMEOUT      (6*HZ)
  89 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  90
  91 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  92 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  93 #define RTL_EEPROM_SIG_ADDR     0x0000
  94
  95 /* write/read MMIO register */
  96 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  97 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  98 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  99 #define RTL_R8(reg)             readb (ioaddr + (reg))
 100 #define RTL_R16(reg)            readw (ioaddr + (reg))
 101 #define RTL_R32(reg)            readl (ioaddr + (reg))
 102
 103 enum mac_version {
 104         RTL_GIGA_MAC_VER_01 = 0,
 105         RTL_GIGA_MAC_VER_02,
 106         RTL_GIGA_MAC_VER_03,
 107         RTL_GIGA_MAC_VER_04,
 108         RTL_GIGA_MAC_VER_05,
 109         RTL_GIGA_MAC_VER_06,
 110         RTL_GIGA_MAC_VER_07,
 111         RTL_GIGA_MAC_VER_08,
 112         RTL_GIGA_MAC_VER_09,
 113         RTL_GIGA_MAC_VER_10,
 114         RTL_GIGA_MAC_VER_11,
 115         RTL_GIGA_MAC_VER_12,
 116         RTL_GIGA_MAC_VER_13,
 117         RTL_GIGA_MAC_VER_14,
 118         RTL_GIGA_MAC_VER_15,
 119         RTL_GIGA_MAC_VER_16,
 120         RTL_GIGA_MAC_VER_17,
 121         RTL_GIGA_MAC_VER_18,
 122         RTL_GIGA_MAC_VER_19,
 123         RTL_GIGA_MAC_VER_20,
 124         RTL_GIGA_MAC_VER_21,
 125         RTL_GIGA_MAC_VER_22,
 126         RTL_GIGA_MAC_VER_23,
 127         RTL_GIGA_MAC_VER_24,
 128         RTL_GIGA_MAC_VER_25,
 129         RTL_GIGA_MAC_VER_26,
 130         RTL_GIGA_MAC_VER_27,
 131         RTL_GIGA_MAC_VER_28,
 132         RTL_GIGA_MAC_VER_29,
 133         RTL_GIGA_MAC_VER_30,
 134         RTL_GIGA_MAC_VER_31,
 135         RTL_GIGA_MAC_VER_32,
 136         RTL_GIGA_MAC_VER_33,
 137         RTL_GIGA_MAC_VER_34,
 138         RTL_GIGA_MAC_VER_35,
 139         RTL_GIGA_MAC_VER_36,
 140         RTL_GIGA_MAC_NONE   = 0xff,
 141 };
 142
 143 enum rtl_tx_desc_version {
 144         RTL_TD_0        = 0,
 145         RTL_TD_1        = 1,
 146 };
 147
 148 #define JUMBO_1K        ETH_DATA_LEN
 149 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 150 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 151 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 152 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 153
 154 #define _R(NAME,TD,FW,SZ,B) {   \
 155         .name = NAME,           \
 156         .txd_version = TD,      \
 157         .fw_name = FW,          \
 158         .jumbo_max = SZ,        \
 159         .jumbo_tx_csum = B      \
 160 }
 161
 162 static const struct {
 163         const char *name;
 164         enum rtl_tx_desc_version txd_version;
 165         const char *fw_name;
 166         u16 jumbo_max;
 167         bool jumbo_tx_csum;
 168 } rtl_chip_infos[] = {
 169         /* PCI devices. */
 170         [RTL_GIGA_MAC_VER_01] =
 171                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 172         [RTL_GIGA_MAC_VER_02] =
 173                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 174         [RTL_GIGA_MAC_VER_03] =
 175                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 176         [RTL_GIGA_MAC_VER_04] =
 177                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 178         [RTL_GIGA_MAC_VER_05] =
 179                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 180         [RTL_GIGA_MAC_VER_06] =
 181                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 182         /* PCI-E devices. */
 183         [RTL_GIGA_MAC_VER_07] =
 184                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 185         [RTL_GIGA_MAC_VER_08] =
 186                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 187         [RTL_GIGA_MAC_VER_09] =
 188                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 189         [RTL_GIGA_MAC_VER_10] =
 190                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 191         [RTL_GIGA_MAC_VER_11] =
 192                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 193         [RTL_GIGA_MAC_VER_12] =
 194                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 195         [RTL_GIGA_MAC_VER_13] =
 196                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 197         [RTL_GIGA_MAC_VER_14] =
 198                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 199         [RTL_GIGA_MAC_VER_15] =
 200                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 201         [RTL_GIGA_MAC_VER_16] =
 202                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 203         [RTL_GIGA_MAC_VER_17] =
 204                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 205         [RTL_GIGA_MAC_VER_18] =
 206                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 207         [RTL_GIGA_MAC_VER_19] =
 208                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 209         [RTL_GIGA_MAC_VER_20] =
 210                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 211         [RTL_GIGA_MAC_VER_21] =
 212                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 213         [RTL_GIGA_MAC_VER_22] =
 214                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 215         [RTL_GIGA_MAC_VER_23] =
 216                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 217         [RTL_GIGA_MAC_VER_24] =
 218                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 219         [RTL_GIGA_MAC_VER_25] =
 220                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 221                                                         JUMBO_9K, false),
 222         [RTL_GIGA_MAC_VER_26] =
 223                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 224                                                         JUMBO_9K, false),
 225         [RTL_GIGA_MAC_VER_27] =
 226                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 227         [RTL_GIGA_MAC_VER_28] =
 228                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 229         [RTL_GIGA_MAC_VER_29] =
 230                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 231                                                         JUMBO_1K, true),
 232         [RTL_GIGA_MAC_VER_30] =
 233                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 234                                                         JUMBO_1K, true),
 235         [RTL_GIGA_MAC_VER_31] =
 236                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 237         [RTL_GIGA_MAC_VER_32] =
 238                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 239                                                         JUMBO_9K, false),
 240         [RTL_GIGA_MAC_VER_33] =
 241                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_34] =
 244                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_35] =
 247                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 248                                                         JUMBO_9K, false),
 249         [RTL_GIGA_MAC_VER_36] =
 250                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 251                                                         JUMBO_9K, false),
 252 };
 253 #undef _R
 254
 255 enum cfg_version {
 256         RTL_CFG_0 = 0x00,
 257         RTL_CFG_1,
 258         RTL_CFG_2
 259 };
 260
 261 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 262         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 263         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 264         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 265         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 266         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 267         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 268         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 269         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 270         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 271         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 272                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 273         { 0x0001,                               0x8168,
 274                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 275         {0,},
 276 };
 277
 278 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 279
 280 static int rx_buf_sz = 16383;
 281 static int use_dac;
 282 static struct {
 283         u32 msg_enable;
 284 } debug = { -1 };
 285
 286 enum rtl_registers {
 287         MAC0            = 0,    /* Ethernet hardware address. */
 288         MAC4            = 4,
 289         MAR0            = 8,    /* Multicast filter. */
 290         CounterAddrLow          = 0x10,
 291         CounterAddrHigh         = 0x14,
 292         TxDescStartAddrLow      = 0x20,
 293         TxDescStartAddrHigh     = 0x24,
 294         TxHDescStartAddrLow     = 0x28,
 295         TxHDescStartAddrHigh    = 0x2c,
 296         FLASH           = 0x30,
 297         ERSR            = 0x36,
 298         ChipCmd         = 0x37,
 299         TxPoll          = 0x38,
 300         IntrMask        = 0x3c,
 301         IntrStatus      = 0x3e,
 302
 303         TxConfig        = 0x40,
 304 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 305 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 306
 307         RxConfig        = 0x44,
 308 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 309 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 310 #define RXCFG_FIFO_SHIFT                13
 311                                         /* No threshold before first PCI xfer */
 312 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 313 #define RXCFG_DMA_SHIFT                 8
 314                                         /* Unlimited maximum PCI burst. */
 315 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 316
 317         RxMissed        = 0x4c,
 318         Cfg9346         = 0x50,
 319         Config0         = 0x51,
 320         Config1         = 0x52,
 321         Config2         = 0x53,
 322         Config3         = 0x54,
 323         Config4         = 0x55,
 324         Config5         = 0x56,
 325         MultiIntr       = 0x5c,
 326         PHYAR           = 0x60,
 327         PHYstatus       = 0x6c,
 328         RxMaxSize       = 0xda,
 329         CPlusCmd        = 0xe0,
 330         IntrMitigate    = 0xe2,
 331         RxDescAddrLow   = 0xe4,
 332         RxDescAddrHigh  = 0xe8,
 333         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 334
 335 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 336
 337         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 338
 339 #define TxPacketMax     (8064 >> 7)
 340 #define EarlySize       0x27
 341
 342         FuncEvent       = 0xf0,
 343         FuncEventMask   = 0xf4,
 344         FuncPresetState = 0xf8,
 345         FuncForceEvent  = 0xfc,
 346 };
 347
 348 enum rtl8110_registers {
 349         TBICSR                  = 0x64,
 350         TBI_ANAR                = 0x68,
 351         TBI_LPAR                = 0x6a,
 352 };
 353
 354 enum rtl8168_8101_registers {
 355         CSIDR                   = 0x64,
 356         CSIAR                   = 0x68,
 357 #define CSIAR_FLAG                      0x80000000
 358 #define CSIAR_WRITE_CMD                 0x80000000
 359 #define CSIAR_BYTE_ENABLE               0x0f
 360 #define CSIAR_BYTE_ENABLE_SHIFT         12
 361 #define CSIAR_ADDR_MASK                 0x0fff
 362         PMCH                    = 0x6f,
 363         EPHYAR                  = 0x80,
 364 #define EPHYAR_FLAG                     0x80000000
 365 #define EPHYAR_WRITE_CMD                0x80000000
 366 #define EPHYAR_REG_MASK                 0x1f
 367 #define EPHYAR_REG_SHIFT                16
 368 #define EPHYAR_DATA_MASK                0xffff
 369         DLLPR                   = 0xd0,
 370 #define PFM_EN                          (1 << 6)
 371         DBG_REG                 = 0xd1,
 372 #define FIX_NAK_1                       (1 << 4)
 373 #define FIX_NAK_2                       (1 << 3)
 374         TWSI                    = 0xd2,
 375         MCU                     = 0xd3,
 376 #define NOW_IS_OOB                      (1 << 7)
 377 #define EN_NDP                          (1 << 3)
 378 #define EN_OOB_RESET                    (1 << 2)
 379         EFUSEAR                 = 0xdc,
 380 #define EFUSEAR_FLAG                    0x80000000
 381 #define EFUSEAR_WRITE_CMD               0x80000000
 382 #define EFUSEAR_READ_CMD                0x00000000
 383 #define EFUSEAR_REG_MASK                0x03ff
 384 #define EFUSEAR_REG_SHIFT               8
 385 #define EFUSEAR_DATA_MASK               0xff
 386 };
 387
 388 enum rtl8168_registers {
 389         LED_FREQ                = 0x1a,
 390         EEE_LED                 = 0x1b,
 391         ERIDR                   = 0x70,
 392         ERIAR                   = 0x74,
 393 #define ERIAR_FLAG                      0x80000000
 394 #define ERIAR_WRITE_CMD                 0x80000000
 395 #define ERIAR_READ_CMD                  0x00000000
 396 #define ERIAR_ADDR_BYTE_ALIGN           4
 397 #define ERIAR_TYPE_SHIFT                16
 398 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 399 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 400 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 401 #define ERIAR_MASK_SHIFT                12
 402 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 403 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 404 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 405         EPHY_RXER_NUM           = 0x7c,
 406         OCPDR                   = 0xb0, /* OCP GPHY access */
 407 #define OCPDR_WRITE_CMD                 0x80000000
 408 #define OCPDR_READ_CMD                  0x00000000
 409 #define OCPDR_REG_MASK                  0x7f
 410 #define OCPDR_GPHY_REG_SHIFT            16
 411 #define OCPDR_DATA_MASK                 0xffff
 412         OCPAR                   = 0xb4,
 413 #define OCPAR_FLAG                      0x80000000
 414 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 415 #define OCPAR_GPHY_READ_CMD             0x0000f060
 416         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 417         MISC                    = 0xf0, /* 8168e only. */
 418 #define TXPLA_RST                       (1 << 29)
 419 #define PWM_EN                          (1 << 22)
 420 };
 421
 422 enum rtl_register_content {
 423         /* InterruptStatusBits */
 424         SYSErr          = 0x8000,
 425         PCSTimeout      = 0x4000,
 426         SWInt           = 0x0100,
 427         TxDescUnavail   = 0x0080,
 428         RxFIFOOver      = 0x0040,
 429         LinkChg         = 0x0020,
 430         RxOverflow      = 0x0010,
 431         TxErr           = 0x0008,
 432         TxOK            = 0x0004,
 433         RxErr           = 0x0002,
 434         RxOK            = 0x0001,
 435
 436         /* RxStatusDesc */
 437         RxBOVF  = (1 << 24),
 438         RxFOVF  = (1 << 23),
 439         RxRWT   = (1 << 22),
 440         RxRES   = (1 << 21),
 441         RxRUNT  = (1 << 20),
 442         RxCRC   = (1 << 19),
 443
 444         /* ChipCmdBits */
 445         StopReq         = 0x80,
 446         CmdReset        = 0x10,
 447         CmdRxEnb        = 0x08,
 448         CmdTxEnb        = 0x04,
 449         RxBufEmpty      = 0x01,
 450
 451         /* TXPoll register p.5 */
 452         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 453         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 454         FSWInt          = 0x01,         /* Forced software interrupt */
 455
 456         /* Cfg9346Bits */
 457         Cfg9346_Lock    = 0x00,
 458         Cfg9346_Unlock  = 0xc0,
 459
 460         /* rx_mode_bits */
 461         AcceptErr       = 0x20,
 462         AcceptRunt      = 0x10,
 463         AcceptBroadcast = 0x08,
 464         AcceptMulticast = 0x04,
 465         AcceptMyPhys    = 0x02,
 466         AcceptAllPhys   = 0x01,
 467 #define RX_CONFIG_ACCEPT_MASK           0x3f
 468
 469         /* TxConfigBits */
 470         TxInterFrameGapShift = 24,
 471         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 472
 473         /* Config1 register p.24 */
 474         LEDS1           = (1 << 7),
 475         LEDS0           = (1 << 6),
 476         Speed_down      = (1 << 4),
 477         MEMMAP          = (1 << 3),
 478         IOMAP           = (1 << 2),
 479         VPD             = (1 << 1),
 480         PMEnable        = (1 << 0),     /* Power Management Enable */
 481
 482         /* Config2 register p. 25 */
 483         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 484         PCI_Clock_66MHz = 0x01,
 485         PCI_Clock_33MHz = 0x00,
 486
 487         /* Config3 register p.25 */
 488         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 489         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 490         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 491         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 492
 493         /* Config4 register */
 494         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 495
 496         /* Config5 register p.27 */
 497         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 498         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 499         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 500         Spi_en          = (1 << 3),
 501         LanWake         = (1 << 1),     /* LanWake enable/disable */
 502         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 503
 504         /* TBICSR p.28 */
 505         TBIReset        = 0x80000000,
 506         TBILoopback     = 0x40000000,
 507         TBINwEnable     = 0x20000000,
 508         TBINwRestart    = 0x10000000,
 509         TBILinkOk       = 0x02000000,
 510         TBINwComplete   = 0x01000000,
 511
 512         /* CPlusCmd p.31 */
 513         EnableBist      = (1 << 15),    // 8168 8101
 514         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 515         Normal_mode     = (1 << 13),    // unused
 516         Force_half_dup  = (1 << 12),    // 8168 8101
 517         Force_rxflow_en = (1 << 11),    // 8168 8101
 518         Force_txflow_en = (1 << 10),    // 8168 8101
 519         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 520         ASF             = (1 << 8),     // 8168 8101
 521         PktCntrDisable  = (1 << 7),     // 8168 8101
 522         Mac_dbgo_sel    = 0x001c,       // 8168
 523         RxVlan          = (1 << 6),
 524         RxChkSum        = (1 << 5),
 525         PCIDAC          = (1 << 4),
 526         PCIMulRW        = (1 << 3),
 527         INTT_0          = 0x0000,       // 8168
 528         INTT_1          = 0x0001,       // 8168
 529         INTT_2          = 0x0002,       // 8168
 530         INTT_3          = 0x0003,       // 8168
 531
 532         /* rtl8169_PHYstatus */
 533         TBI_Enable      = 0x80,
 534         TxFlowCtrl      = 0x40,
 535         RxFlowCtrl      = 0x20,
 536         _1000bpsF       = 0x10,
 537         _100bps         = 0x08,
 538         _10bps          = 0x04,
 539         LinkStatus      = 0x02,
 540         FullDup         = 0x01,
 541
 542         /* _TBICSRBit */
 543         TBILinkOK       = 0x02000000,
 544
 545         /* DumpCounterCommand */
 546         CounterDump     = 0x8,
 547 };
 548
 549 enum rtl_desc_bit {
 550         /* First doubleword. */
 551         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 552         RingEnd         = (1 << 30), /* End of descriptor ring */
 553         FirstFrag       = (1 << 29), /* First segment of a packet */
 554         LastFrag        = (1 << 28), /* Final segment of a packet */
 555 };
 556
 557 /* Generic case. */
 558 enum rtl_tx_desc_bit {
 559         /* First doubleword. */
 560         TD_LSO          = (1 << 27),            /* Large Send Offload */
 561 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 562
 563         /* Second doubleword. */
 564         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 565 };
 566
 567 /* 8169, 8168b and 810x except 8102e. */
 568 enum rtl_tx_desc_bit_0 {
 569         /* First doubleword. */
 570 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 571         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 572         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 573         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 574 };
 575
 576 /* 8102e, 8168c and beyond. */
 577 enum rtl_tx_desc_bit_1 {
 578         /* Second doubleword. */
 579 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 580         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 581         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 582         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 583 };
 584
 585 static const struct rtl_tx_desc_info {
 586         struct {
 587                 u32 udp;
 588                 u32 tcp;
 589         } checksum;
 590         u16 mss_shift;
 591         u16 opts_offset;
 592 } tx_desc_info [] = {
 593         [RTL_TD_0] = {
 594                 .checksum = {
 595                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 596                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 597                 },
 598                 .mss_shift      = TD0_MSS_SHIFT,
 599                 .opts_offset    = 0
 600         },
 601         [RTL_TD_1] = {
 602                 .checksum = {
 603                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 604                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 605                 },
 606                 .mss_shift      = TD1_MSS_SHIFT,
 607                 .opts_offset    = 1
 608         }
 609 };
 610
 611 enum rtl_rx_desc_bit {
 612         /* Rx private */
 613         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 614         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 615
 616 #define RxProtoUDP      (PID1)
 617 #define RxProtoTCP      (PID0)
 618 #define RxProtoIP       (PID1 | PID0)
 619 #define RxProtoMask     RxProtoIP
 620
 621         IPFail          = (1 << 16), /* IP checksum failed */
 622         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 623         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 624         RxVlanTag       = (1 << 16), /* VLAN tag available */
 625 };
 626
 627 #define RsvdMask        0x3fffc000
 628
 629 struct TxDesc {
 630         __le32 opts1;
 631         __le32 opts2;
 632         __le64 addr;
 633 };
 634
 635 struct RxDesc {
 636         __le32 opts1;
 637         __le32 opts2;
 638         __le64 addr;
 639 };
 640
 641 struct ring_info {
 642         struct sk_buff  *skb;
 643         u32             len;
 644         u8              __pad[sizeof(void *) - sizeof(u32)];
 645 };
 646
 647 enum features {
 648         RTL_FEATURE_WOL         = (1 << 0),
 649         RTL_FEATURE_MSI         = (1 << 1),
 650         RTL_FEATURE_GMII        = (1 << 2),
 651 };
 652
 653 struct rtl8169_counters {
 654         __le64  tx_packets;
 655         __le64  rx_packets;
 656         __le64  tx_errors;
 657         __le32  rx_errors;
 658         __le16  rx_missed;
 659         __le16  align_errors;
 660         __le32  tx_one_collision;
 661         __le32  tx_multi_collision;
 662         __le64  rx_unicast;
 663         __le64  rx_broadcast;
 664         __le32  rx_multicast;
 665         __le16  tx_aborted;
 666         __le16  tx_underun;
 667 };
 668
 669 enum rtl_flag {
 670         RTL_FLAG_TASK_ENABLED,
 671         RTL_FLAG_TASK_SLOW_PENDING,
 672         RTL_FLAG_TASK_RESET_PENDING,
 673         RTL_FLAG_TASK_PHY_PENDING,
 674         RTL_FLAG_MAX
 675 };
 676
 677 struct rtl8169_stats {
 678         u64                     packets;
 679         u64                     bytes;
 680         struct u64_stats_sync   syncp;
 681 };
 682
 683 struct rtl8169_private {
 684         void __iomem *mmio_addr;        /* memory map physical address */
 685         struct pci_dev *pci_dev;
 686         struct net_device *dev;
 687         struct napi_struct napi;
 688         u32 msg_enable;
 689         u16 txd_version;
 690         u16 mac_version;
 691         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 692         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 693         u32 dirty_rx;
 694         u32 dirty_tx;
 695         struct rtl8169_stats rx_stats;
 696         struct rtl8169_stats tx_stats;
 697         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 698         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 699         dma_addr_t TxPhyAddr;
 700         dma_addr_t RxPhyAddr;
 701         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 702         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 703         struct timer_list timer;
 704         u16 cp_cmd;
 705
 706         u16 event_slow;
 707
 708         struct mdio_ops {
 709                 void (*write)(void __iomem *, int, int);
 710                 int (*read)(void __iomem *, int);
 711         } mdio_ops;
 712
 713         struct pll_power_ops {
 714                 void (*down)(struct rtl8169_private *);
 715                 void (*up)(struct rtl8169_private *);
 716         } pll_power_ops;
 717
 718         struct jumbo_ops {
 719                 void (*enable)(struct rtl8169_private *);
 720                 void (*disable)(struct rtl8169_private *);
 721         } jumbo_ops;
 722
 723         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 724         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 725         void (*phy_reset_enable)(struct rtl8169_private *tp);
 726         void (*hw_start)(struct net_device *);
 727         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 728         unsigned int (*link_ok)(void __iomem *);
 729         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 730
 731         struct {
 732                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 733                 struct mutex mutex;
 734                 struct work_struct work;
 735         } wk;
 736
 737         unsigned features;
 738
 739         struct mii_if_info mii;
 740         struct rtl8169_counters counters;
 741         u32 saved_wolopts;
 742         u32 opts1_mask;
 743
 744         struct rtl_fw {
 745                 const struct firmware *fw;
 746
 747 #define RTL_VER_SIZE            32
 748
 749                 char version[RTL_VER_SIZE];
 750
 751                 struct rtl_fw_phy_action {
 752                         __le32 *code;
 753                         size_t size;
 754                 } phy_action;
 755         } *rtl_fw;
 756 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 757 };
 758
 759 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 760 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 761 module_param(use_dac, int, 0);
 762 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 763 module_param_named(debug, debug.msg_enable, int, 0);
 764 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 765 MODULE_LICENSE("GPL");
 766 MODULE_VERSION(RTL8169_VERSION);
 767 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 768 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 769 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 770 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 771 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 772 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 773 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 774 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 775
 776 static void rtl_lock_work(struct rtl8169_private *tp)
 777 {
 778         mutex_lock(&tp->wk.mutex);
 779 }
 780
 781 static void rtl_unlock_work(struct rtl8169_private *tp)
 782 {
 783         mutex_unlock(&tp->wk.mutex);
 784 }
 785
 786 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 787 {
 788         int cap = pci_pcie_cap(pdev);
 789
 790         if (cap) {
 791                 u16 ctl;
 792
 793                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 794                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 795                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 796         }
 797 }
 798
 799 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 800 {
 801         void __iomem *ioaddr = tp->mmio_addr;
 802         int i;
 803
 804         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 805         for (i = 0; i < 20; i++) {
 806                 udelay(100);
 807                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 808                         break;
 809         }
 810         return RTL_R32(OCPDR);
 811 }
 812
 813 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 814 {
 815         void __iomem *ioaddr = tp->mmio_addr;
 816         int i;
 817
 818         RTL_W32(OCPDR, data);
 819         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 820         for (i = 0; i < 20; i++) {
 821                 udelay(100);
 822                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 823                         break;
 824         }
 825 }
 826
 827 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 828 {
 829         void __iomem *ioaddr = tp->mmio_addr;
 830         int i;
 831
 832         RTL_W8(ERIDR, cmd);
 833         RTL_W32(ERIAR, 0x800010e8);
 834         msleep(2);
 835         for (i = 0; i < 5; i++) {
 836                 udelay(100);
 837                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 838                         break;
 839         }
 840
 841         ocp_write(tp, 0x1, 0x30, 0x00000001);
 842 }
 843
 844 #define OOB_CMD_RESET           0x00
 845 #define OOB_CMD_DRIVER_START    0x05
 846 #define OOB_CMD_DRIVER_STOP     0x06
 847
 848 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 849 {
 850         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 851 }
 852
 853 static void rtl8168_driver_start(struct rtl8169_private *tp)
 854 {
 855         u16 reg;
 856         int i;
 857
 858         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 859
 860         reg = rtl8168_get_ocp_reg(tp);
 861
 862         for (i = 0; i < 10; i++) {
 863                 msleep(10);
 864                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 865                         break;
 866         }
 867 }
 868
 869 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 870 {
 871         u16 reg;
 872         int i;
 873
 874         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 875
 876         reg = rtl8168_get_ocp_reg(tp);
 877
 878         for (i = 0; i < 10; i++) {
 879                 msleep(10);
 880                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 881                         break;
 882         }
 883 }
 884
 885 static int r8168dp_check_dash(struct rtl8169_private *tp)
 886 {
 887         u16 reg = rtl8168_get_ocp_reg(tp);
 888
 889         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 890 }
 891
 892 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 893 {
 894         int i;
 895
 896         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 897
 898         for (i = 20; i > 0; i--) {
 899                 /*
 900                  * Check if the RTL8169 has completed writing to the specified
 901                  * MII register.
 902                  */
 903                 if (!(RTL_R32(PHYAR) & 0x80000000))
 904                         break;
 905                 udelay(25);
 906         }
 907         /*
 908          * According to hardware specs a 20us delay is required after write
 909          * complete indication, but before sending next command.
 910          */
 911         udelay(20);
 912 }
 913
 914 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 915 {
 916         int i, value = -1;
 917
 918         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 919
 920         for (i = 20; i > 0; i--) {
 921                 /*
 922                  * Check if the RTL8169 has completed retrieving data from
 923                  * the specified MII register.
 924                  */
 925                 if (RTL_R32(PHYAR) & 0x80000000) {
 926                         value = RTL_R32(PHYAR) & 0xffff;
 927                         break;
 928                 }
 929                 udelay(25);
 930         }
 931         /*
 932          * According to hardware specs a 20us delay is required after read
 933          * complete indication, but before sending next command.
 934          */
 935         udelay(20);
 936
 937         return value;
 938 }
 939
 940 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 941 {
 942         int i;
 943
 944         RTL_W32(OCPDR, data |
 945                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 946         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 947         RTL_W32(EPHY_RXER_NUM, 0);
 948
 949         for (i = 0; i < 100; i++) {
 950                 mdelay(1);
 951                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 952                         break;
 953         }
 954 }
 955
 956 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 957 {
 958         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 959                 (value & OCPDR_DATA_MASK));
 960 }
 961
 962 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 963 {
 964         int i;
 965
 966         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 967
 968         mdelay(1);
 969         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 970         RTL_W32(EPHY_RXER_NUM, 0);
 971
 972         for (i = 0; i < 100; i++) {
 973                 mdelay(1);
 974                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 975                         break;
 976         }
 977
 978         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 979 }
 980
 981 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 982
 983 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 984 {
 985         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 986 }
 987
 988 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 989 {
 990         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 991 }
 992
 993 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 994 {
 995         r8168dp_2_mdio_start(ioaddr);
 996
 997         r8169_mdio_write(ioaddr, reg_addr, value);
 998
 999         r8168dp_2_mdio_stop(ioaddr);
1000 }
1001
1002 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1003 {
1004         int value;
1005
1006         r8168dp_2_mdio_start(ioaddr);
1007
1008         value = r8169_mdio_read(ioaddr, reg_addr);
1009
1010         r8168dp_2_mdio_stop(ioaddr);
1011
1012         return value;
1013 }
1014
1015 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1016 {
1017         tp->mdio_ops.write(tp->mmio_addr, location, val);
1018 }
1019
1020 static int rtl_readphy(struct rtl8169_private *tp, int location)
1021 {
1022         return tp->mdio_ops.read(tp->mmio_addr, location);
1023 }
1024
1025 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1026 {
1027         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1028 }
1029
1030 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1031 {
1032         int val;
1033
1034         val = rtl_readphy(tp, reg_addr);
1035         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1036 }
1037
1038 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1039                            int val)
1040 {
1041         struct rtl8169_private *tp = netdev_priv(dev);
1042
1043         rtl_writephy(tp, location, val);
1044 }
1045
1046 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1047 {
1048         struct rtl8169_private *tp = netdev_priv(dev);
1049
1050         return rtl_readphy(tp, location);
1051 }
1052
1053 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1054 {
1055         unsigned int i;
1056
1057         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1058                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1059
1060         for (i = 0; i < 100; i++) {
1061                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1062                         break;
1063                 udelay(10);
1064         }
1065 }
1066
1067 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1068 {
1069         u16 value = 0xffff;
1070         unsigned int i;
1071
1072         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1073
1074         for (i = 0; i < 100; i++) {
1075                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1076                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1077                         break;
1078                 }
1079                 udelay(10);
1080         }
1081
1082         return value;
1083 }
1084
1085 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1086 {
1087         unsigned int i;
1088
1089         RTL_W32(CSIDR, value);
1090         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1091                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1092
1093         for (i = 0; i < 100; i++) {
1094                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1095                         break;
1096                 udelay(10);
1097         }
1098 }
1099
1100 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1101 {
1102         u32 value = ~0x00;
1103         unsigned int i;
1104
1105         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1106                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1107
1108         for (i = 0; i < 100; i++) {
1109                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1110                         value = RTL_R32(CSIDR);
1111                         break;
1112                 }
1113                 udelay(10);
1114         }
1115
1116         return value;
1117 }
1118
1119 static
1120 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1121 {
1122         unsigned int i;
1123
1124         BUG_ON((addr & 3) || (mask == 0));
1125         RTL_W32(ERIDR, val);
1126         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1127
1128         for (i = 0; i < 100; i++) {
1129                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1130                         break;
1131                 udelay(100);
1132         }
1133 }
1134
1135 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1136 {
1137         u32 value = ~0x00;
1138         unsigned int i;
1139
1140         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1141
1142         for (i = 0; i < 100; i++) {
1143                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1144                         value = RTL_R32(ERIDR);
1145                         break;
1146                 }
1147                 udelay(100);
1148         }
1149
1150         return value;
1151 }
1152
1153 static void
1154 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1155 {
1156         u32 val;
1157
1158         val = rtl_eri_read(ioaddr, addr, type);
1159         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1160 }
1161
1162 struct exgmac_reg {
1163         u16 addr;
1164         u16 mask;
1165         u32 val;
1166 };
1167
1168 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1169                                    const struct exgmac_reg *r, int len)
1170 {
1171         while (len-- > 0) {
1172                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1173                 r++;
1174         }
1175 }
1176
1177 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1178 {
1179         u8 value = 0xff;
1180         unsigned int i;
1181
1182         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1183
1184         for (i = 0; i < 300; i++) {
1185                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1186                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1187                         break;
1188                 }
1189                 udelay(100);
1190         }
1191
1192         return value;
1193 }
1194
1195 static u16 rtl_get_events(struct rtl8169_private *tp)
1196 {
1197         void __iomem *ioaddr = tp->mmio_addr;
1198
1199         return RTL_R16(IntrStatus);
1200 }
1201
1202 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1203 {
1204         void __iomem *ioaddr = tp->mmio_addr;
1205
1206         RTL_W16(IntrStatus, bits);
1207         mmiowb();
1208 }
1209
1210 static void rtl_irq_disable(struct rtl8169_private *tp)
1211 {
1212         void __iomem *ioaddr = tp->mmio_addr;
1213
1214         RTL_W16(IntrMask, 0);
1215         mmiowb();
1216 }
1217
1218 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1219 {
1220         void __iomem *ioaddr = tp->mmio_addr;
1221
1222         RTL_W16(IntrMask, bits);
1223 }
1224
1225 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1226 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1227 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1228
1229 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1230 {
1231         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1232 }
1233
1234 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1235 {
1236         void __iomem *ioaddr = tp->mmio_addr;
1237
1238         rtl_irq_disable(tp);
1239         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1240         RTL_R8(ChipCmd);
1241 }
1242
1243 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1244 {
1245         void __iomem *ioaddr = tp->mmio_addr;
1246
1247         return RTL_R32(TBICSR) & TBIReset;
1248 }
1249
1250 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1251 {
1252         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1253 }
1254
1255 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1256 {
1257         return RTL_R32(TBICSR) & TBILinkOk;
1258 }
1259
1260 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1261 {
1262         return RTL_R8(PHYstatus) & LinkStatus;
1263 }
1264
1265 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1266 {
1267         void __iomem *ioaddr = tp->mmio_addr;
1268
1269         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1270 }
1271
1272 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1273 {
1274         unsigned int val;
1275
1276         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1277         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1278 }
1279
1280 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1281 {
1282         void __iomem *ioaddr = tp->mmio_addr;
1283         struct net_device *dev = tp->dev;
1284
1285         if (!netif_running(dev))
1286                 return;
1287
1288         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1289                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1290                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1291                                       0x00000011, ERIAR_EXGMAC);
1292                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1293                                       0x00000005, ERIAR_EXGMAC);
1294                 } else if (RTL_R8(PHYstatus) & _100bps) {
1295                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1296                                       0x0000001f, ERIAR_EXGMAC);
1297                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1298                                       0x00000005, ERIAR_EXGMAC);
1299                 } else {
1300                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1301                                       0x0000001f, ERIAR_EXGMAC);
1302                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1303                                       0x0000003f, ERIAR_EXGMAC);
1304                 }
1305                 /* Reset packet filter */
1306                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1307                              ERIAR_EXGMAC);
1308                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1309                              ERIAR_EXGMAC);
1310         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1311                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1312                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1313                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1314                                       0x00000011, ERIAR_EXGMAC);
1315                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1316                                       0x00000005, ERIAR_EXGMAC);
1317                 } else {
1318                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1319                                       0x0000001f, ERIAR_EXGMAC);
1320                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1321                                       0x0000003f, ERIAR_EXGMAC);
1322                 }
1323         }
1324 }
1325
1326 static void __rtl8169_check_link_status(struct net_device *dev,
1327                                         struct rtl8169_private *tp,
1328                                         void __iomem *ioaddr, bool pm)
1329 {
1330         if (tp->link_ok(ioaddr)) {
1331                 rtl_link_chg_patch(tp);
1332                 /* This is to cancel a scheduled suspend if there's one. */
1333                 if (pm)
1334                         pm_request_resume(&tp->pci_dev->dev);
1335                 netif_carrier_on(dev);
1336                 if (net_ratelimit())
1337                         netif_info(tp, ifup, dev, "link up\n");
1338         } else {
1339                 netif_carrier_off(dev);
1340                 netif_info(tp, ifdown, dev, "link down\n");
1341                 if (pm)
1342                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1343         }
1344 }
1345
1346 static void rtl8169_check_link_status(struct net_device *dev,
1347                                       struct rtl8169_private *tp,
1348                                       void __iomem *ioaddr)
1349 {
1350         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1351 }
1352
1353 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1354
1355 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1356 {
1357         void __iomem *ioaddr = tp->mmio_addr;
1358         u8 options;
1359         u32 wolopts = 0;
1360
1361         options = RTL_R8(Config1);
1362         if (!(options & PMEnable))
1363                 return 0;
1364
1365         options = RTL_R8(Config3);
1366         if (options & LinkUp)
1367                 wolopts |= WAKE_PHY;
1368         if (options & MagicPacket)
1369                 wolopts |= WAKE_MAGIC;
1370
1371         options = RTL_R8(Config5);
1372         if (options & UWF)
1373                 wolopts |= WAKE_UCAST;
1374         if (options & BWF)
1375                 wolopts |= WAKE_BCAST;
1376         if (options & MWF)
1377                 wolopts |= WAKE_MCAST;
1378
1379         return wolopts;
1380 }
1381
1382 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1383 {
1384         struct rtl8169_private *tp = netdev_priv(dev);
1385
1386         rtl_lock_work(tp);
1387
1388         wol->supported = WAKE_ANY;
1389         wol->wolopts = __rtl8169_get_wol(tp);
1390
1391         rtl_unlock_work(tp);
1392 }
1393
1394 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1395 {
1396         void __iomem *ioaddr = tp->mmio_addr;
1397         unsigned int i;
1398         static const struct {
1399                 u32 opt;
1400                 u16 reg;
1401                 u8  mask;
1402         } cfg[] = {
1403                 { WAKE_ANY,   Config1, PMEnable },
1404                 { WAKE_PHY,   Config3, LinkUp },
1405                 { WAKE_MAGIC, Config3, MagicPacket },
1406                 { WAKE_UCAST, Config5, UWF },
1407                 { WAKE_BCAST, Config5, BWF },
1408                 { WAKE_MCAST, Config5, MWF },
1409                 { WAKE_ANY,   Config5, LanWake }
1410         };
1411
1412         RTL_W8(Cfg9346, Cfg9346_Unlock);
1413
1414         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1415                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1416                 if (wolopts & cfg[i].opt)
1417                         options |= cfg[i].mask;
1418                 RTL_W8(cfg[i].reg, options);
1419         }
1420
1421         RTL_W8(Cfg9346, Cfg9346_Lock);
1422 }
1423
1424 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1425 {
1426         struct rtl8169_private *tp = netdev_priv(dev);
1427
1428         rtl_lock_work(tp);
1429
1430         if (wol->wolopts)
1431                 tp->features |= RTL_FEATURE_WOL;
1432         else
1433                 tp->features &= ~RTL_FEATURE_WOL;
1434         __rtl8169_set_wol(tp, wol->wolopts);
1435
1436         rtl_unlock_work(tp);
1437
1438         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1439
1440         return 0;
1441 }
1442
1443 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1444 {
1445         return rtl_chip_infos[tp->mac_version].fw_name;
1446 }
1447
1448 static void rtl8169_get_drvinfo(struct net_device *dev,
1449                                 struct ethtool_drvinfo *info)
1450 {
1451         struct rtl8169_private *tp = netdev_priv(dev);
1452         struct rtl_fw *rtl_fw = tp->rtl_fw;
1453
1454         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1455         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1456         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1457         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1458         if (!IS_ERR_OR_NULL(rtl_fw))
1459                 strlcpy(info->fw_version, rtl_fw->version,
1460                         sizeof(info->fw_version));
1461 }
1462
1463 static int rtl8169_get_regs_len(struct net_device *dev)
1464 {
1465         return R8169_REGS_SIZE;
1466 }
1467
1468 static int rtl8169_set_speed_tbi(struct net_device *dev,
1469                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1470 {
1471         struct rtl8169_private *tp = netdev_priv(dev);
1472         void __iomem *ioaddr = tp->mmio_addr;
1473         int ret = 0;
1474         u32 reg;
1475
1476         reg = RTL_R32(TBICSR);
1477         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1478             (duplex == DUPLEX_FULL)) {
1479                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1480         } else if (autoneg == AUTONEG_ENABLE)
1481                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1482         else {
1483                 netif_warn(tp, link, dev,
1484                            "incorrect speed setting refused in TBI mode\n");
1485                 ret = -EOPNOTSUPP;
1486         }
1487
1488         return ret;
1489 }
1490
1491 static int rtl8169_set_speed_xmii(struct net_device *dev,
1492                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1493 {
1494         struct rtl8169_private *tp = netdev_priv(dev);
1495         int giga_ctrl, bmcr;
1496         int rc = -EINVAL;
1497
1498         rtl_writephy(tp, 0x1f, 0x0000);
1499
1500         if (autoneg == AUTONEG_ENABLE) {
1501                 int auto_nego;
1502
1503                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1504                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1505                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1506
1507                 if (adv & ADVERTISED_10baseT_Half)
1508                         auto_nego |= ADVERTISE_10HALF;
1509                 if (adv & ADVERTISED_10baseT_Full)
1510                         auto_nego |= ADVERTISE_10FULL;
1511                 if (adv & ADVERTISED_100baseT_Half)
1512                         auto_nego |= ADVERTISE_100HALF;
1513                 if (adv & ADVERTISED_100baseT_Full)
1514                         auto_nego |= ADVERTISE_100FULL;
1515
1516                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1517
1518                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1519                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1520
1521                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1522                 if (tp->mii.supports_gmii) {
1523                         if (adv & ADVERTISED_1000baseT_Half)
1524                                 giga_ctrl |= ADVERTISE_1000HALF;
1525                         if (adv & ADVERTISED_1000baseT_Full)
1526                                 giga_ctrl |= ADVERTISE_1000FULL;
1527                 } else if (adv & (ADVERTISED_1000baseT_Half |
1528                                   ADVERTISED_1000baseT_Full)) {
1529                         netif_info(tp, link, dev,
1530                                    "PHY does not support 1000Mbps\n");
1531                         goto out;
1532                 }
1533
1534                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1535
1536                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1537                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1538         } else {
1539                 giga_ctrl = 0;
1540
1541                 if (speed == SPEED_10)
1542                         bmcr = 0;
1543                 else if (speed == SPEED_100)
1544                         bmcr = BMCR_SPEED100;
1545                 else
1546                         goto out;
1547
1548                 if (duplex == DUPLEX_FULL)
1549                         bmcr |= BMCR_FULLDPLX;
1550         }
1551
1552         rtl_writephy(tp, MII_BMCR, bmcr);
1553
1554         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1555             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1556                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1557                         rtl_writephy(tp, 0x17, 0x2138);
1558                         rtl_writephy(tp, 0x0e, 0x0260);
1559                 } else {
1560                         rtl_writephy(tp, 0x17, 0x2108);
1561                         rtl_writephy(tp, 0x0e, 0x0000);
1562                 }
1563         }
1564
1565         rc = 0;
1566 out:
1567         return rc;
1568 }
1569
1570 static int rtl8169_set_speed(struct net_device *dev,
1571                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1572 {
1573         struct rtl8169_private *tp = netdev_priv(dev);
1574         int ret;
1575
1576         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1577         if (ret < 0)
1578                 goto out;
1579
1580         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1581             (advertising & ADVERTISED_1000baseT_Full)) {
1582                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1583         }
1584 out:
1585         return ret;
1586 }
1587
1588 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1589 {
1590         struct rtl8169_private *tp = netdev_priv(dev);
1591         int ret;
1592
1593         del_timer_sync(&tp->timer);
1594
1595         rtl_lock_work(tp);
1596         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1597                                 cmd->duplex, cmd->advertising);
1598         rtl_unlock_work(tp);
1599
1600         return ret;
1601 }
1602
1603 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1604         netdev_features_t features)
1605 {
1606         struct rtl8169_private *tp = netdev_priv(dev);
1607
1608         if (dev->mtu > TD_MSS_MAX)
1609                 features &= ~NETIF_F_ALL_TSO;
1610
1611         if (dev->mtu > JUMBO_1K &&
1612             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1613                 features &= ~NETIF_F_IP_CSUM;
1614
1615         return features;
1616 }
1617
1618 static void __rtl8169_set_features(struct net_device *dev,
1619                                    netdev_features_t features)
1620 {
1621         struct rtl8169_private *tp = netdev_priv(dev);
1622         netdev_features_t changed = features ^ dev->features;
1623         void __iomem *ioaddr = tp->mmio_addr;
1624
1625         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1626                 return;
1627
1628         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1629                 if (features & NETIF_F_RXCSUM)
1630                         tp->cp_cmd |= RxChkSum;
1631                 else
1632                         tp->cp_cmd &= ~RxChkSum;
1633
1634                 if (dev->features & NETIF_F_HW_VLAN_RX)
1635                         tp->cp_cmd |= RxVlan;
1636                 else
1637                         tp->cp_cmd &= ~RxVlan;
1638
1639                 RTL_W16(CPlusCmd, tp->cp_cmd);
1640                 RTL_R16(CPlusCmd);
1641         }
1642         if (changed & NETIF_F_RXALL) {
1643                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1644                 if (features & NETIF_F_RXALL)
1645                         tmp |= (AcceptErr | AcceptRunt);
1646                 RTL_W32(RxConfig, tmp);
1647         }
1648 }
1649
1650 static int rtl8169_set_features(struct net_device *dev,
1651                                 netdev_features_t features)
1652 {
1653         struct rtl8169_private *tp = netdev_priv(dev);
1654
1655         rtl_lock_work(tp);
1656         __rtl8169_set_features(dev, features);
1657         rtl_unlock_work(tp);
1658
1659         return 0;
1660 }
1661
1662
1663 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1664                                       struct sk_buff *skb)
1665 {
1666         return (vlan_tx_tag_present(skb)) ?
1667                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1668 }
1669
1670 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1671 {
1672         u32 opts2 = le32_to_cpu(desc->opts2);
1673
1674         if (opts2 & RxVlanTag)
1675                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1676
1677         desc->opts2 = 0;
1678 }
1679
1680 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1681 {
1682         struct rtl8169_private *tp = netdev_priv(dev);
1683         void __iomem *ioaddr = tp->mmio_addr;
1684         u32 status;
1685
1686         cmd->supported =
1687                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1688         cmd->port = PORT_FIBRE;
1689         cmd->transceiver = XCVR_INTERNAL;
1690
1691         status = RTL_R32(TBICSR);
1692         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1693         cmd->autoneg = !!(status & TBINwEnable);
1694
1695         ethtool_cmd_speed_set(cmd, SPEED_1000);
1696         cmd->duplex = DUPLEX_FULL; /* Always set */
1697
1698         return 0;
1699 }
1700
1701 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1702 {
1703         struct rtl8169_private *tp = netdev_priv(dev);
1704
1705         return mii_ethtool_gset(&tp->mii, cmd);
1706 }
1707
1708 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1709 {
1710         struct rtl8169_private *tp = netdev_priv(dev);
1711         int rc;
1712
1713         rtl_lock_work(tp);
1714         rc = tp->get_settings(dev, cmd);
1715         rtl_unlock_work(tp);
1716
1717         return rc;
1718 }
1719
1720 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1721                              void *p)
1722 {
1723         struct rtl8169_private *tp = netdev_priv(dev);
1724
1725         if (regs->len > R8169_REGS_SIZE)
1726                 regs->len = R8169_REGS_SIZE;
1727
1728         rtl_lock_work(tp);
1729         memcpy_fromio(p, tp->mmio_addr, regs->len);
1730         rtl_unlock_work(tp);
1731 }
1732
1733 static u32 rtl8169_get_msglevel(struct net_device *dev)
1734 {
1735         struct rtl8169_private *tp = netdev_priv(dev);
1736
1737         return tp->msg_enable;
1738 }
1739
1740 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1741 {
1742         struct rtl8169_private *tp = netdev_priv(dev);
1743
1744         tp->msg_enable = value;
1745 }
1746
1747 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1748         "tx_packets",
1749         "rx_packets",
1750         "tx_errors",
1751         "rx_errors",
1752         "rx_missed",
1753         "align_errors",
1754         "tx_single_collisions",
1755         "tx_multi_collisions",
1756         "unicast",
1757         "broadcast",
1758         "multicast",
1759         "tx_aborted",
1760         "tx_underrun",
1761 };
1762
1763 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1764 {
1765         switch (sset) {
1766         case ETH_SS_STATS:
1767                 return ARRAY_SIZE(rtl8169_gstrings);
1768         default:
1769                 return -EOPNOTSUPP;
1770         }
1771 }
1772
1773 static void rtl8169_update_counters(struct net_device *dev)
1774 {
1775         struct rtl8169_private *tp = netdev_priv(dev);
1776         void __iomem *ioaddr = tp->mmio_addr;
1777         struct device *d = &tp->pci_dev->dev;
1778         struct rtl8169_counters *counters;
1779         dma_addr_t paddr;
1780         u32 cmd;
1781         int wait = 1000;
1782
1783         /*
1784          * Some chips are unable to dump tally counters when the receiver
1785          * is disabled.
1786          */
1787         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1788                 return;
1789
1790         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1791         if (!counters)
1792                 return;
1793
1794         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1795         cmd = (u64)paddr & DMA_BIT_MASK(32);
1796         RTL_W32(CounterAddrLow, cmd);
1797         RTL_W32(CounterAddrLow, cmd | CounterDump);
1798
1799         while (wait--) {
1800                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1801                         memcpy(&tp->counters, counters, sizeof(*counters));
1802                         break;
1803                 }
1804                 udelay(10);
1805         }
1806
1807         RTL_W32(CounterAddrLow, 0);
1808         RTL_W32(CounterAddrHigh, 0);
1809
1810         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1811 }
1812
1813 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1814                                       struct ethtool_stats *stats, u64 *data)
1815 {
1816         struct rtl8169_private *tp = netdev_priv(dev);
1817
1818         ASSERT_RTNL();
1819
1820         rtl8169_update_counters(dev);
1821
1822         data[0] = le64_to_cpu(tp->counters.tx_packets);
1823         data[1] = le64_to_cpu(tp->counters.rx_packets);
1824         data[2] = le64_to_cpu(tp->counters.tx_errors);
1825         data[3] = le32_to_cpu(tp->counters.rx_errors);
1826         data[4] = le16_to_cpu(tp->counters.rx_missed);
1827         data[5] = le16_to_cpu(tp->counters.align_errors);
1828         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1829         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1830         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1831         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1832         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1833         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1834         data[12] = le16_to_cpu(tp->counters.tx_underun);
1835 }
1836
1837 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1838 {
1839         switch(stringset) {
1840         case ETH_SS_STATS:
1841                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1842                 break;
1843         }
1844 }
1845
1846 static const struct ethtool_ops rtl8169_ethtool_ops = {
1847         .get_drvinfo            = rtl8169_get_drvinfo,
1848         .get_regs_len           = rtl8169_get_regs_len,
1849         .get_link               = ethtool_op_get_link,
1850         .get_settings           = rtl8169_get_settings,
1851         .set_settings           = rtl8169_set_settings,
1852         .get_msglevel           = rtl8169_get_msglevel,
1853         .set_msglevel           = rtl8169_set_msglevel,
1854         .get_regs               = rtl8169_get_regs,
1855         .get_wol                = rtl8169_get_wol,
1856         .set_wol                = rtl8169_set_wol,
1857         .get_strings            = rtl8169_get_strings,
1858         .get_sset_count         = rtl8169_get_sset_count,
1859         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1860 };
1861
1862 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1863                                     struct net_device *dev, u8 default_version)
1864 {
1865         void __iomem *ioaddr = tp->mmio_addr;
1866         /*
1867          * The driver currently handles the 8168Bf and the 8168Be identically
1868          * but they can be identified more specifically through the test below
1869          * if needed:
1870          *
1871          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1872          *
1873          * Same thing for the 8101Eb and the 8101Ec:
1874          *
1875          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1876          */
1877         static const struct rtl_mac_info {
1878                 u32 mask;
1879                 u32 val;
1880                 int mac_version;
1881         } mac_info[] = {
1882                 /* 8168F family. */
1883                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
1884                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
1885
1886                 /* 8168E family. */
1887                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1888                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1889                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1890                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1891
1892                 /* 8168D family. */
1893                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1894                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1895                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1896
1897                 /* 8168DP family. */
1898                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1899                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1900                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1901
1902                 /* 8168C family. */
1903                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1904                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1905                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1906                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1907                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1908                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1909                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1910                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1911                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1912
1913                 /* 8168B family. */
1914                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1915                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1916                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1917                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1918
1919                 /* 8101 family. */
1920                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1921                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1922                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1923                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1924                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1925                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1926                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1927                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1928                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1929                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1930                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1931                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1932                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1933                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1934                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1935                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1936                 /* FIXME: where did these entries come from ? -- FR */
1937                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1938                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1939
1940                 /* 8110 family. */
1941                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1942                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1943                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1944                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1945                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1946                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1947
1948                 /* Catch-all */
1949                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1950         };
1951         const struct rtl_mac_info *p = mac_info;
1952         u32 reg;
1953
1954         reg = RTL_R32(TxConfig);
1955         while ((reg & p->mask) != p->val)
1956                 p++;
1957         tp->mac_version = p->mac_version;
1958
1959         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1960                 netif_notice(tp, probe, dev,
1961                              "unknown MAC, using family default\n");
1962                 tp->mac_version = default_version;
1963         }
1964 }
1965
1966 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1967 {
1968         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1969 }
1970
1971 struct phy_reg {
1972         u16 reg;
1973         u16 val;
1974 };
1975
1976 static void rtl_writephy_batch(struct rtl8169_private *tp,
1977                                const struct phy_reg *regs, int len)
1978 {
1979         while (len-- > 0) {
1980                 rtl_writephy(tp, regs->reg, regs->val);
1981                 regs++;
1982         }
1983 }
1984
1985 #define PHY_READ                0x00000000
1986 #define PHY_DATA_OR             0x10000000
1987 #define PHY_DATA_AND            0x20000000
1988 #define PHY_BJMPN               0x30000000
1989 #define PHY_READ_EFUSE          0x40000000
1990 #define PHY_READ_MAC_BYTE       0x50000000
1991 #define PHY_WRITE_MAC_BYTE      0x60000000
1992 #define PHY_CLEAR_READCOUNT     0x70000000
1993 #define PHY_WRITE               0x80000000
1994 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1995 #define PHY_COMP_EQ_SKIPN       0xa0000000
1996 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1997 #define PHY_WRITE_PREVIOUS      0xc0000000
1998 #define PHY_SKIPN               0xd0000000
1999 #define PHY_DELAY_MS            0xe0000000
2000 #define PHY_WRITE_ERI_WORD      0xf0000000
2001
2002 struct fw_info {
2003         u32     magic;
2004         char    version[RTL_VER_SIZE];
2005         __le32  fw_start;
2006         __le32  fw_len;
2007         u8      chksum;
2008 } __packed;
2009
2010 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2011
2012 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2013 {
2014         const struct firmware *fw = rtl_fw->fw;
2015         struct fw_info *fw_info = (struct fw_info *)fw->data;
2016         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2017         char *version = rtl_fw->version;
2018         bool rc = false;
2019
2020         if (fw->size < FW_OPCODE_SIZE)
2021                 goto out;
2022
2023         if (!fw_info->magic) {
2024                 size_t i, size, start;
2025                 u8 checksum = 0;
2026
2027                 if (fw->size < sizeof(*fw_info))
2028                         goto out;
2029
2030                 for (i = 0; i < fw->size; i++)
2031                         checksum += fw->data[i];
2032                 if (checksum != 0)
2033                         goto out;
2034
2035                 start = le32_to_cpu(fw_info->fw_start);
2036                 if (start > fw->size)
2037                         goto out;
2038
2039                 size = le32_to_cpu(fw_info->fw_len);
2040                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2041                         goto out;
2042
2043                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2044
2045                 pa->code = (__le32 *)(fw->data + start);
2046                 pa->size = size;
2047         } else {
2048                 if (fw->size % FW_OPCODE_SIZE)
2049                         goto out;
2050
2051                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2052
2053                 pa->code = (__le32 *)fw->data;
2054                 pa->size = fw->size / FW_OPCODE_SIZE;
2055         }
2056         version[RTL_VER_SIZE - 1] = 0;
2057
2058         rc = true;
2059 out:
2060         return rc;
2061 }
2062
2063 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2064                            struct rtl_fw_phy_action *pa)
2065 {
2066         bool rc = false;
2067         size_t index;
2068
2069         for (index = 0; index < pa->size; index++) {
2070                 u32 action = le32_to_cpu(pa->code[index]);
2071                 u32 regno = (action & 0x0fff0000) >> 16;
2072
2073                 switch(action & 0xf0000000) {
2074                 case PHY_READ:
2075                 case PHY_DATA_OR:
2076                 case PHY_DATA_AND:
2077                 case PHY_READ_EFUSE:
2078                 case PHY_CLEAR_READCOUNT:
2079                 case PHY_WRITE:
2080                 case PHY_WRITE_PREVIOUS:
2081                 case PHY_DELAY_MS:
2082                         break;
2083
2084                 case PHY_BJMPN:
2085                         if (regno > index) {
2086                                 netif_err(tp, ifup, tp->dev,
2087                                           "Out of range of firmware\n");
2088                                 goto out;
2089                         }
2090                         break;
2091                 case PHY_READCOUNT_EQ_SKIP:
2092                         if (index + 2 >= pa->size) {
2093                                 netif_err(tp, ifup, tp->dev,
2094                                           "Out of range of firmware\n");
2095                                 goto out;
2096                         }
2097                         break;
2098                 case PHY_COMP_EQ_SKIPN:
2099                 case PHY_COMP_NEQ_SKIPN:
2100                 case PHY_SKIPN:
2101                         if (index + 1 + regno >= pa->size) {
2102                                 netif_err(tp, ifup, tp->dev,
2103                                           "Out of range of firmware\n");
2104                                 goto out;
2105                         }
2106                         break;
2107
2108                 case PHY_READ_MAC_BYTE:
2109                 case PHY_WRITE_MAC_BYTE:
2110                 case PHY_WRITE_ERI_WORD:
2111                 default:
2112                         netif_err(tp, ifup, tp->dev,
2113                                   "Invalid action 0x%08x\n", action);
2114                         goto out;
2115                 }
2116         }
2117         rc = true;
2118 out:
2119         return rc;
2120 }
2121
2122 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2123 {
2124         struct net_device *dev = tp->dev;
2125         int rc = -EINVAL;
2126
2127         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2128                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2129                 goto out;
2130         }
2131
2132         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2133                 rc = 0;
2134 out:
2135         return rc;
2136 }
2137
2138 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2139 {
2140         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2141         u32 predata, count;
2142         size_t index;
2143
2144         predata = count = 0;
2145
2146         for (index = 0; index < pa->size; ) {
2147                 u32 action = le32_to_cpu(pa->code[index]);
2148                 u32 data = action & 0x0000ffff;
2149                 u32 regno = (action & 0x0fff0000) >> 16;
2150
2151                 if (!action)
2152                         break;
2153
2154                 switch(action & 0xf0000000) {
2155                 case PHY_READ:
2156                         predata = rtl_readphy(tp, regno);
2157                         count++;
2158                         index++;
2159                         break;
2160                 case PHY_DATA_OR:
2161                         predata |= data;
2162                         index++;
2163                         break;
2164                 case PHY_DATA_AND:
2165                         predata &= data;
2166                         index++;
2167                         break;
2168                 case PHY_BJMPN:
2169                         index -= regno;
2170                         break;
2171                 case PHY_READ_EFUSE:
2172                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2173                         index++;
2174                         break;
2175                 case PHY_CLEAR_READCOUNT:
2176                         count = 0;
2177                         index++;
2178                         break;
2179                 case PHY_WRITE:
2180                         rtl_writephy(tp, regno, data);
2181                         index++;
2182                         break;
2183                 case PHY_READCOUNT_EQ_SKIP:
2184                         index += (count == data) ? 2 : 1;
2185                         break;
2186                 case PHY_COMP_EQ_SKIPN:
2187                         if (predata == data)
2188                                 index += regno;
2189                         index++;
2190                         break;
2191                 case PHY_COMP_NEQ_SKIPN:
2192                         if (predata != data)
2193                                 index += regno;
2194                         index++;
2195                         break;
2196                 case PHY_WRITE_PREVIOUS:
2197                         rtl_writephy(tp, regno, predata);
2198                         index++;
2199                         break;
2200                 case PHY_SKIPN:
2201                         index += regno + 1;
2202                         break;
2203                 case PHY_DELAY_MS:
2204                         mdelay(data);
2205                         index++;
2206                         break;
2207
2208                 case PHY_READ_MAC_BYTE:
2209                 case PHY_WRITE_MAC_BYTE:
2210                 case PHY_WRITE_ERI_WORD:
2211                 default:
2212                         BUG();
2213                 }
2214         }
2215 }
2216
2217 static void rtl_release_firmware(struct rtl8169_private *tp)
2218 {
2219         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2220                 release_firmware(tp->rtl_fw->fw);
2221                 kfree(tp->rtl_fw);
2222         }
2223         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2224 }
2225
2226 static void rtl_apply_firmware(struct rtl8169_private *tp)
2227 {
2228         struct rtl_fw *rtl_fw = tp->rtl_fw;
2229
2230         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2231         if (!IS_ERR_OR_NULL(rtl_fw))
2232                 rtl_phy_write_fw(tp, rtl_fw);
2233 }
2234
2235 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2236 {
2237         if (rtl_readphy(tp, reg) != val)
2238                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2239         else
2240                 rtl_apply_firmware(tp);
2241 }
2242
2243 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2244 {
2245         static const struct phy_reg phy_reg_init[] = {
2246                 { 0x1f, 0x0001 },
2247                 { 0x06, 0x006e },
2248                 { 0x08, 0x0708 },
2249                 { 0x15, 0x4000 },
2250                 { 0x18, 0x65c7 },
2251
2252                 { 0x1f, 0x0001 },
2253                 { 0x03, 0x00a1 },
2254                 { 0x02, 0x0008 },
2255                 { 0x01, 0x0120 },
2256                 { 0x00, 0x1000 },
2257                 { 0x04, 0x0800 },
2258                 { 0x04, 0x0000 },
2259
2260                 { 0x03, 0xff41 },
2261                 { 0x02, 0xdf60 },
2262                 { 0x01, 0x0140 },
2263                 { 0x00, 0x0077 },
2264                 { 0x04, 0x7800 },
2265                 { 0x04, 0x7000 },
2266
2267                 { 0x03, 0x802f },
2268                 { 0x02, 0x4f02 },
2269                 { 0x01, 0x0409 },
2270                 { 0x00, 0xf0f9 },
2271                 { 0x04, 0x9800 },
2272                 { 0x04, 0x9000 },
2273
2274                 { 0x03, 0xdf01 },
2275                 { 0x02, 0xdf20 },
2276                 { 0x01, 0xff95 },
2277                 { 0x00, 0xba00 },
2278                 { 0x04, 0xa800 },
2279                 { 0x04, 0xa000 },
2280
2281                 { 0x03, 0xff41 },
2282                 { 0x02, 0xdf20 },
2283                 { 0x01, 0x0140 },
2284                 { 0x00, 0x00bb },
2285                 { 0x04, 0xb800 },
2286                 { 0x04, 0xb000 },
2287
2288                 { 0x03, 0xdf41 },
2289                 { 0x02, 0xdc60 },
2290                 { 0x01, 0x6340 },
2291                 { 0x00, 0x007d },
2292                 { 0x04, 0xd800 },
2293                 { 0x04, 0xd000 },
2294
2295                 { 0x03, 0xdf01 },
2296                 { 0x02, 0xdf20 },
2297                 { 0x01, 0x100a },
2298                 { 0x00, 0xa0ff },
2299                 { 0x04, 0xf800 },
2300                 { 0x04, 0xf000 },
2301
2302                 { 0x1f, 0x0000 },
2303                 { 0x0b, 0x0000 },
2304                 { 0x00, 0x9200 }
2305         };
2306
2307         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2308 }
2309
2310 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2311 {
2312         static const struct phy_reg phy_reg_init[] = {
2313                 { 0x1f, 0x0002 },
2314                 { 0x01, 0x90d0 },
2315                 { 0x1f, 0x0000 }
2316         };
2317
2318         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2319 }
2320
2321 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2322 {
2323         struct pci_dev *pdev = tp->pci_dev;
2324
2325         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2326             (pdev->subsystem_device != 0xe000))
2327                 return;
2328
2329         rtl_writephy(tp, 0x1f, 0x0001);
2330         rtl_writephy(tp, 0x10, 0xf01b);
2331         rtl_writephy(tp, 0x1f, 0x0000);
2332 }
2333
2334 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2335 {
2336         static const struct phy_reg phy_reg_init[] = {
2337                 { 0x1f, 0x0001 },
2338                 { 0x04, 0x0000 },
2339                 { 0x03, 0x00a1 },
2340                 { 0x02, 0x0008 },
2341                 { 0x01, 0x0120 },
2342                 { 0x00, 0x1000 },
2343                 { 0x04, 0x0800 },
2344                 { 0x04, 0x9000 },
2345                 { 0x03, 0x802f },
2346                 { 0x02, 0x4f02 },
2347                 { 0x01, 0x0409 },
2348                 { 0x00, 0xf099 },
2349                 { 0x04, 0x9800 },
2350                 { 0x04, 0xa000 },
2351                 { 0x03, 0xdf01 },
2352                 { 0x02, 0xdf20 },
2353                 { 0x01, 0xff95 },
2354                 { 0x00, 0xba00 },
2355                 { 0x04, 0xa800 },
2356                 { 0x04, 0xf000 },
2357                 { 0x03, 0xdf01 },
2358                 { 0x02, 0xdf20 },
2359                 { 0x01, 0x101a },
2360                 { 0x00, 0xa0ff },
2361                 { 0x04, 0xf800 },
2362                 { 0x04, 0x0000 },
2363                 { 0x1f, 0x0000 },
2364
2365                 { 0x1f, 0x0001 },
2366                 { 0x10, 0xf41b },
2367                 { 0x14, 0xfb54 },
2368                 { 0x18, 0xf5c7 },
2369                 { 0x1f, 0x0000 },
2370
2371                 { 0x1f, 0x0001 },
2372                 { 0x17, 0x0cc0 },
2373                 { 0x1f, 0x0000 }
2374         };
2375
2376         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2377
2378         rtl8169scd_hw_phy_config_quirk(tp);
2379 }
2380
2381 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2382 {
2383         static const struct phy_reg phy_reg_init[] = {
2384                 { 0x1f, 0x0001 },
2385                 { 0x04, 0x0000 },
2386                 { 0x03, 0x00a1 },
2387                 { 0x02, 0x0008 },
2388                 { 0x01, 0x0120 },
2389                 { 0x00, 0x1000 },
2390                 { 0x04, 0x0800 },
2391                 { 0x04, 0x9000 },
2392                 { 0x03, 0x802f },
2393                 { 0x02, 0x4f02 },
2394                 { 0x01, 0x0409 },
2395                 { 0x00, 0xf099 },
2396                 { 0x04, 0x9800 },
2397                 { 0x04, 0xa000 },
2398                 { 0x03, 0xdf01 },
2399                 { 0x02, 0xdf20 },
2400                 { 0x01, 0xff95 },
2401                 { 0x00, 0xba00 },
2402                 { 0x04, 0xa800 },
2403                 { 0x04, 0xf000 },
2404                 { 0x03, 0xdf01 },
2405                 { 0x02, 0xdf20 },
2406                 { 0x01, 0x101a },
2407                 { 0x00, 0xa0ff },
2408                 { 0x04, 0xf800 },
2409                 { 0x04, 0x0000 },
2410                 { 0x1f, 0x0000 },
2411
2412                 { 0x1f, 0x0001 },
2413                 { 0x0b, 0x8480 },
2414                 { 0x1f, 0x0000 },
2415
2416                 { 0x1f, 0x0001 },
2417                 { 0x18, 0x67c7 },
2418                 { 0x04, 0x2000 },
2419                 { 0x03, 0x002f },
2420                 { 0x02, 0x4360 },
2421                 { 0x01, 0x0109 },
2422                 { 0x00, 0x3022 },
2423                 { 0x04, 0x2800 },
2424                 { 0x1f, 0x0000 },
2425
2426                 { 0x1f, 0x0001 },
2427                 { 0x17, 0x0cc0 },
2428                 { 0x1f, 0x0000 }
2429         };
2430
2431         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2432 }
2433
2434 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2435 {
2436         static const struct phy_reg phy_reg_init[] = {
2437                 { 0x10, 0xf41b },
2438                 { 0x1f, 0x0000 }
2439         };
2440
2441         rtl_writephy(tp, 0x1f, 0x0001);
2442         rtl_patchphy(tp, 0x16, 1 << 0);
2443
2444         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2445 }
2446
2447 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2448 {
2449         static const struct phy_reg phy_reg_init[] = {
2450                 { 0x1f, 0x0001 },
2451                 { 0x10, 0xf41b },
2452                 { 0x1f, 0x0000 }
2453         };
2454
2455         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2456 }
2457
2458 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2459 {
2460         static const struct phy_reg phy_reg_init[] = {
2461                 { 0x1f, 0x0000 },
2462                 { 0x1d, 0x0f00 },
2463                 { 0x1f, 0x0002 },
2464                 { 0x0c, 0x1ec8 },
2465                 { 0x1f, 0x0000 }
2466         };
2467
2468         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2469 }
2470
2471 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2472 {
2473         static const struct phy_reg phy_reg_init[] = {
2474                 { 0x1f, 0x0001 },
2475                 { 0x1d, 0x3d98 },
2476                 { 0x1f, 0x0000 }
2477         };
2478
2479         rtl_writephy(tp, 0x1f, 0x0000);
2480         rtl_patchphy(tp, 0x14, 1 << 5);
2481         rtl_patchphy(tp, 0x0d, 1 << 5);
2482
2483         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2484 }
2485
2486 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2487 {
2488         static const struct phy_reg phy_reg_init[] = {
2489                 { 0x1f, 0x0001 },
2490                 { 0x12, 0x2300 },
2491                 { 0x1f, 0x0002 },
2492                 { 0x00, 0x88d4 },
2493                 { 0x01, 0x82b1 },
2494                 { 0x03, 0x7002 },
2495                 { 0x08, 0x9e30 },
2496                 { 0x09, 0x01f0 },
2497                 { 0x0a, 0x5500 },
2498                 { 0x0c, 0x00c8 },
2499                 { 0x1f, 0x0003 },
2500                 { 0x12, 0xc096 },
2501                 { 0x16, 0x000a },
2502                 { 0x1f, 0x0000 },
2503                 { 0x1f, 0x0000 },
2504                 { 0x09, 0x2000 },
2505                 { 0x09, 0x0000 }
2506         };
2507
2508         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2509
2510         rtl_patchphy(tp, 0x14, 1 << 5);
2511         rtl_patchphy(tp, 0x0d, 1 << 5);
2512         rtl_writephy(tp, 0x1f, 0x0000);
2513 }
2514
2515 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2516 {
2517         static const struct phy_reg phy_reg_init[] = {
2518                 { 0x1f, 0x0001 },
2519                 { 0x12, 0x2300 },
2520                 { 0x03, 0x802f },
2521                 { 0x02, 0x4f02 },
2522                 { 0x01, 0x0409 },
2523                 { 0x00, 0xf099 },
2524                 { 0x04, 0x9800 },
2525                 { 0x04, 0x9000 },
2526                 { 0x1d, 0x3d98 },
2527                 { 0x1f, 0x0002 },
2528                 { 0x0c, 0x7eb8 },
2529                 { 0x06, 0x0761 },
2530                 { 0x1f, 0x0003 },
2531                 { 0x16, 0x0f0a },
2532                 { 0x1f, 0x0000 }
2533         };
2534
2535         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2536
2537         rtl_patchphy(tp, 0x16, 1 << 0);
2538         rtl_patchphy(tp, 0x14, 1 << 5);
2539         rtl_patchphy(tp, 0x0d, 1 << 5);
2540         rtl_writephy(tp, 0x1f, 0x0000);
2541 }
2542
2543 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2544 {
2545         static const struct phy_reg phy_reg_init[] = {
2546                 { 0x1f, 0x0001 },
2547                 { 0x12, 0x2300 },
2548                 { 0x1d, 0x3d98 },
2549                 { 0x1f, 0x0002 },
2550                 { 0x0c, 0x7eb8 },
2551                 { 0x06, 0x5461 },
2552                 { 0x1f, 0x0003 },
2553                 { 0x16, 0x0f0a },
2554                 { 0x1f, 0x0000 }
2555         };
2556
2557         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2558
2559         rtl_patchphy(tp, 0x16, 1 << 0);
2560         rtl_patchphy(tp, 0x14, 1 << 5);
2561         rtl_patchphy(tp, 0x0d, 1 << 5);
2562         rtl_writephy(tp, 0x1f, 0x0000);
2563 }
2564
2565 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2566 {
2567         rtl8168c_3_hw_phy_config(tp);
2568 }
2569
2570 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2571 {
2572         static const struct phy_reg phy_reg_init_0[] = {
2573                 /* Channel Estimation */
2574                 { 0x1f, 0x0001 },
2575                 { 0x06, 0x4064 },
2576                 { 0x07, 0x2863 },
2577                 { 0x08, 0x059c },
2578                 { 0x09, 0x26b4 },
2579                 { 0x0a, 0x6a19 },
2580                 { 0x0b, 0xdcc8 },
2581                 { 0x10, 0xf06d },
2582                 { 0x14, 0x7f68 },
2583                 { 0x18, 0x7fd9 },
2584                 { 0x1c, 0xf0ff },
2585                 { 0x1d, 0x3d9c },
2586                 { 0x1f, 0x0003 },
2587                 { 0x12, 0xf49f },
2588                 { 0x13, 0x070b },
2589                 { 0x1a, 0x05ad },
2590                 { 0x14, 0x94c0 },
2591
2592                 /*
2593                  * Tx Error Issue
2594                  * Enhance line driver power
2595                  */
2596                 { 0x1f, 0x0002 },
2597                 { 0x06, 0x5561 },
2598                 { 0x1f, 0x0005 },
2599                 { 0x05, 0x8332 },
2600                 { 0x06, 0x5561 },
2601
2602                 /*
2603                  * Can not link to 1Gbps with bad cable
2604                  * Decrease SNR threshold form 21.07dB to 19.04dB
2605                  */
2606                 { 0x1f, 0x0001 },
2607                 { 0x17, 0x0cc0 },
2608
2609                 { 0x1f, 0x0000 },
2610                 { 0x0d, 0xf880 }
2611         };
2612         void __iomem *ioaddr = tp->mmio_addr;
2613
2614         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2615
2616         /*
2617          * Rx Error Issue
2618          * Fine Tune Switching regulator parameter
2619          */
2620         rtl_writephy(tp, 0x1f, 0x0002);
2621         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2622         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2623
2624         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2625                 static const struct phy_reg phy_reg_init[] = {
2626                         { 0x1f, 0x0002 },
2627                         { 0x05, 0x669a },
2628                         { 0x1f, 0x0005 },
2629                         { 0x05, 0x8330 },
2630                         { 0x06, 0x669a },
2631                         { 0x1f, 0x0002 }
2632                 };
2633                 int val;
2634
2635                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2636
2637                 val = rtl_readphy(tp, 0x0d);
2638
2639                 if ((val & 0x00ff) != 0x006c) {
2640                         static const u32 set[] = {
2641                                 0x0065, 0x0066, 0x0067, 0x0068,
2642                                 0x0069, 0x006a, 0x006b, 0x006c
2643                         };
2644                         int i;
2645
2646                         rtl_writephy(tp, 0x1f, 0x0002);
2647
2648                         val &= 0xff00;
2649                         for (i = 0; i < ARRAY_SIZE(set); i++)
2650                                 rtl_writephy(tp, 0x0d, val | set[i]);
2651                 }
2652         } else {
2653                 static const struct phy_reg phy_reg_init[] = {
2654                         { 0x1f, 0x0002 },
2655                         { 0x05, 0x6662 },
2656                         { 0x1f, 0x0005 },
2657                         { 0x05, 0x8330 },
2658                         { 0x06, 0x6662 }
2659                 };
2660
2661                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2662         }
2663
2664         /* RSET couple improve */
2665         rtl_writephy(tp, 0x1f, 0x0002);
2666         rtl_patchphy(tp, 0x0d, 0x0300);
2667         rtl_patchphy(tp, 0x0f, 0x0010);
2668
2669         /* Fine tune PLL performance */
2670         rtl_writephy(tp, 0x1f, 0x0002);
2671         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2672         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2673
2674         rtl_writephy(tp, 0x1f, 0x0005);
2675         rtl_writephy(tp, 0x05, 0x001b);
2676
2677         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2678
2679         rtl_writephy(tp, 0x1f, 0x0000);
2680 }
2681
2682 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2683 {
2684         static const struct phy_reg phy_reg_init_0[] = {
2685                 /* Channel Estimation */
2686                 { 0x1f, 0x0001 },
2687                 { 0x06, 0x4064 },
2688                 { 0x07, 0x2863 },
2689                 { 0x08, 0x059c },
2690                 { 0x09, 0x26b4 },
2691                 { 0x0a, 0x6a19 },
2692                 { 0x0b, 0xdcc8 },
2693                 { 0x10, 0xf06d },
2694                 { 0x14, 0x7f68 },
2695                 { 0x18, 0x7fd9 },
2696                 { 0x1c, 0xf0ff },
2697                 { 0x1d, 0x3d9c },
2698                 { 0x1f, 0x0003 },
2699                 { 0x12, 0xf49f },
2700                 { 0x13, 0x070b },
2701                 { 0x1a, 0x05ad },
2702                 { 0x14, 0x94c0 },
2703
2704                 /*
2705                  * Tx Error Issue
2706                  * Enhance line driver power
2707                  */
2708                 { 0x1f, 0x0002 },
2709                 { 0x06, 0x5561 },
2710                 { 0x1f, 0x0005 },
2711                 { 0x05, 0x8332 },
2712                 { 0x06, 0x5561 },
2713
2714                 /*
2715                  * Can not link to 1Gbps with bad cable
2716                  * Decrease SNR threshold form 21.07dB to 19.04dB
2717                  */
2718                 { 0x1f, 0x0001 },
2719                 { 0x17, 0x0cc0 },
2720
2721                 { 0x1f, 0x0000 },
2722                 { 0x0d, 0xf880 }
2723         };
2724         void __iomem *ioaddr = tp->mmio_addr;
2725
2726         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2727
2728         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2729                 static const struct phy_reg phy_reg_init[] = {
2730                         { 0x1f, 0x0002 },
2731                         { 0x05, 0x669a },
2732                         { 0x1f, 0x0005 },
2733                         { 0x05, 0x8330 },
2734                         { 0x06, 0x669a },
2735
2736                         { 0x1f, 0x0002 }
2737                 };
2738                 int val;
2739
2740                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2741
2742                 val = rtl_readphy(tp, 0x0d);
2743                 if ((val & 0x00ff) != 0x006c) {
2744                         static const u32 set[] = {
2745                                 0x0065, 0x0066, 0x0067, 0x0068,
2746                                 0x0069, 0x006a, 0x006b, 0x006c
2747                         };
2748                         int i;
2749
2750                         rtl_writephy(tp, 0x1f, 0x0002);
2751
2752                         val &= 0xff00;
2753                         for (i = 0; i < ARRAY_SIZE(set); i++)
2754                                 rtl_writephy(tp, 0x0d, val | set[i]);
2755                 }
2756         } else {
2757                 static const struct phy_reg phy_reg_init[] = {
2758                         { 0x1f, 0x0002 },
2759                         { 0x05, 0x2642 },
2760                         { 0x1f, 0x0005 },
2761                         { 0x05, 0x8330 },
2762                         { 0x06, 0x2642 }
2763                 };
2764
2765                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2766         }
2767
2768         /* Fine tune PLL performance */
2769         rtl_writephy(tp, 0x1f, 0x0002);
2770         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2771         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2772
2773         /* Switching regulator Slew rate */
2774         rtl_writephy(tp, 0x1f, 0x0002);
2775         rtl_patchphy(tp, 0x0f, 0x0017);
2776
2777         rtl_writephy(tp, 0x1f, 0x0005);
2778         rtl_writephy(tp, 0x05, 0x001b);
2779
2780         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2781
2782         rtl_writephy(tp, 0x1f, 0x0000);
2783 }
2784
2785 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2786 {
2787         static const struct phy_reg phy_reg_init[] = {
2788                 { 0x1f, 0x0002 },
2789                 { 0x10, 0x0008 },
2790                 { 0x0d, 0x006c },
2791
2792                 { 0x1f, 0x0000 },
2793                 { 0x0d, 0xf880 },
2794
2795                 { 0x1f, 0x0001 },
2796                 { 0x17, 0x0cc0 },
2797
2798                 { 0x1f, 0x0001 },
2799                 { 0x0b, 0xa4d8 },
2800                 { 0x09, 0x281c },
2801                 { 0x07, 0x2883 },
2802                 { 0x0a, 0x6b35 },
2803                 { 0x1d, 0x3da4 },
2804                 { 0x1c, 0xeffd },
2805                 { 0x14, 0x7f52 },
2806                 { 0x18, 0x7fc6 },
2807                 { 0x08, 0x0601 },
2808                 { 0x06, 0x4063 },
2809                 { 0x10, 0xf074 },
2810                 { 0x1f, 0x0003 },
2811                 { 0x13, 0x0789 },
2812                 { 0x12, 0xf4bd },
2813                 { 0x1a, 0x04fd },
2814                 { 0x14, 0x84b0 },
2815                 { 0x1f, 0x0000 },
2816                 { 0x00, 0x9200 },
2817
2818                 { 0x1f, 0x0005 },
2819                 { 0x01, 0x0340 },
2820                 { 0x1f, 0x0001 },
2821                 { 0x04, 0x4000 },
2822                 { 0x03, 0x1d21 },
2823                 { 0x02, 0x0c32 },
2824                 { 0x01, 0x0200 },
2825                 { 0x00, 0x5554 },
2826                 { 0x04, 0x4800 },
2827                 { 0x04, 0x4000 },
2828                 { 0x04, 0xf000 },
2829                 { 0x03, 0xdf01 },
2830                 { 0x02, 0xdf20 },
2831                 { 0x01, 0x101a },
2832                 { 0x00, 0xa0ff },
2833                 { 0x04, 0xf800 },
2834                 { 0x04, 0xf000 },
2835                 { 0x1f, 0x0000 },
2836
2837                 { 0x1f, 0x0007 },
2838                 { 0x1e, 0x0023 },
2839                 { 0x16, 0x0000 },
2840                 { 0x1f, 0x0000 }
2841         };
2842
2843         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2844 }
2845
2846 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2847 {
2848         static const struct phy_reg phy_reg_init[] = {
2849                 { 0x1f, 0x0001 },
2850                 { 0x17, 0x0cc0 },
2851
2852                 { 0x1f, 0x0007 },
2853                 { 0x1e, 0x002d },
2854                 { 0x18, 0x0040 },
2855                 { 0x1f, 0x0000 }
2856         };
2857
2858         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2859         rtl_patchphy(tp, 0x0d, 1 << 5);
2860 }
2861
2862 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2863 {
2864         static const struct phy_reg phy_reg_init[] = {
2865                 /* Enable Delay cap */
2866                 { 0x1f, 0x0005 },
2867                 { 0x05, 0x8b80 },
2868                 { 0x06, 0xc896 },
2869                 { 0x1f, 0x0000 },
2870
2871                 /* Channel estimation fine tune */
2872                 { 0x1f, 0x0001 },
2873                 { 0x0b, 0x6c20 },
2874                 { 0x07, 0x2872 },
2875                 { 0x1c, 0xefff },
2876                 { 0x1f, 0x0003 },
2877                 { 0x14, 0x6420 },
2878                 { 0x1f, 0x0000 },
2879
2880                 /* Update PFM & 10M TX idle timer */
2881                 { 0x1f, 0x0007 },
2882                 { 0x1e, 0x002f },
2883                 { 0x15, 0x1919 },
2884                 { 0x1f, 0x0000 },
2885
2886                 { 0x1f, 0x0007 },
2887                 { 0x1e, 0x00ac },
2888                 { 0x18, 0x0006 },
2889                 { 0x1f, 0x0000 }
2890         };
2891
2892         rtl_apply_firmware(tp);
2893
2894         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2895
2896         /* DCO enable for 10M IDLE Power */
2897         rtl_writephy(tp, 0x1f, 0x0007);
2898         rtl_writephy(tp, 0x1e, 0x0023);
2899         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2900         rtl_writephy(tp, 0x1f, 0x0000);
2901
2902         /* For impedance matching */
2903         rtl_writephy(tp, 0x1f, 0x0002);
2904         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2905         rtl_writephy(tp, 0x1f, 0x0000);
2906
2907         /* PHY auto speed down */
2908         rtl_writephy(tp, 0x1f, 0x0007);
2909         rtl_writephy(tp, 0x1e, 0x002d);
2910         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2911         rtl_writephy(tp, 0x1f, 0x0000);
2912         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2913
2914         rtl_writephy(tp, 0x1f, 0x0005);
2915         rtl_writephy(tp, 0x05, 0x8b86);
2916         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2917         rtl_writephy(tp, 0x1f, 0x0000);
2918
2919         rtl_writephy(tp, 0x1f, 0x0005);
2920         rtl_writephy(tp, 0x05, 0x8b85);
2921         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2922         rtl_writephy(tp, 0x1f, 0x0007);
2923         rtl_writephy(tp, 0x1e, 0x0020);
2924         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2925         rtl_writephy(tp, 0x1f, 0x0006);
2926         rtl_writephy(tp, 0x00, 0x5a00);
2927         rtl_writephy(tp, 0x1f, 0x0000);
2928         rtl_writephy(tp, 0x0d, 0x0007);
2929         rtl_writephy(tp, 0x0e, 0x003c);
2930         rtl_writephy(tp, 0x0d, 0x4007);
2931         rtl_writephy(tp, 0x0e, 0x0000);
2932         rtl_writephy(tp, 0x0d, 0x0000);
2933 }
2934
2935 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2936 {
2937         static const struct phy_reg phy_reg_init[] = {
2938                 /* Enable Delay cap */
2939                 { 0x1f, 0x0004 },
2940                 { 0x1f, 0x0007 },
2941                 { 0x1e, 0x00ac },
2942                 { 0x18, 0x0006 },
2943                 { 0x1f, 0x0002 },
2944                 { 0x1f, 0x0000 },
2945                 { 0x1f, 0x0000 },
2946
2947                 /* Channel estimation fine tune */
2948                 { 0x1f, 0x0003 },
2949                 { 0x09, 0xa20f },
2950                 { 0x1f, 0x0000 },
2951                 { 0x1f, 0x0000 },
2952
2953                 /* Green Setting */
2954                 { 0x1f, 0x0005 },
2955                 { 0x05, 0x8b5b },
2956                 { 0x06, 0x9222 },
2957                 { 0x05, 0x8b6d },
2958                 { 0x06, 0x8000 },
2959                 { 0x05, 0x8b76 },
2960                 { 0x06, 0x8000 },
2961                 { 0x1f, 0x0000 }
2962         };
2963
2964         rtl_apply_firmware(tp);
2965
2966         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2967
2968         /* For 4-corner performance improve */
2969         rtl_writephy(tp, 0x1f, 0x0005);
2970         rtl_writephy(tp, 0x05, 0x8b80);
2971         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2972         rtl_writephy(tp, 0x1f, 0x0000);
2973
2974         /* PHY auto speed down */
2975         rtl_writephy(tp, 0x1f, 0x0004);
2976         rtl_writephy(tp, 0x1f, 0x0007);
2977         rtl_writephy(tp, 0x1e, 0x002d);
2978         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2979         rtl_writephy(tp, 0x1f, 0x0002);
2980         rtl_writephy(tp, 0x1f, 0x0000);
2981         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2982
2983         /* improve 10M EEE waveform */
2984         rtl_writephy(tp, 0x1f, 0x0005);
2985         rtl_writephy(tp, 0x05, 0x8b86);
2986         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2987         rtl_writephy(tp, 0x1f, 0x0000);
2988
2989         /* Improve 2-pair detection performance */
2990         rtl_writephy(tp, 0x1f, 0x0005);
2991         rtl_writephy(tp, 0x05, 0x8b85);
2992         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2993         rtl_writephy(tp, 0x1f, 0x0000);
2994
2995         /* EEE setting */
2996         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2997                      ERIAR_EXGMAC);
2998         rtl_writephy(tp, 0x1f, 0x0005);
2999         rtl_writephy(tp, 0x05, 0x8b85);
3000         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3001         rtl_writephy(tp, 0x1f, 0x0004);
3002         rtl_writephy(tp, 0x1f, 0x0007);
3003         rtl_writephy(tp, 0x1e, 0x0020);
3004         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3005         rtl_writephy(tp, 0x1f, 0x0002);
3006         rtl_writephy(tp, 0x1f, 0x0000);
3007         rtl_writephy(tp, 0x0d, 0x0007);
3008         rtl_writephy(tp, 0x0e, 0x003c);
3009         rtl_writephy(tp, 0x0d, 0x4007);
3010         rtl_writephy(tp, 0x0e, 0x0000);
3011         rtl_writephy(tp, 0x0d, 0x0000);
3012
3013         /* Green feature */
3014         rtl_writephy(tp, 0x1f, 0x0003);
3015         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3016         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3017         rtl_writephy(tp, 0x1f, 0x0000);
3018 }
3019
3020 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3021 {
3022         static const struct phy_reg phy_reg_init[] = {
3023                 /* Channel estimation fine tune */
3024                 { 0x1f, 0x0003 },
3025                 { 0x09, 0xa20f },
3026                 { 0x1f, 0x0000 },
3027
3028                 /* Modify green table for giga & fnet */
3029                 { 0x1f, 0x0005 },
3030                 { 0x05, 0x8b55 },
3031                 { 0x06, 0x0000 },
3032                 { 0x05, 0x8b5e },
3033                 { 0x06, 0x0000 },
3034                 { 0x05, 0x8b67 },
3035                 { 0x06, 0x0000 },
3036                 { 0x05, 0x8b70 },
3037                 { 0x06, 0x0000 },
3038                 { 0x1f, 0x0000 },
3039                 { 0x1f, 0x0007 },
3040                 { 0x1e, 0x0078 },
3041                 { 0x17, 0x0000 },
3042                 { 0x19, 0x00fb },
3043                 { 0x1f, 0x0000 },
3044
3045                 /* Modify green table for 10M */
3046                 { 0x1f, 0x0005 },
3047                 { 0x05, 0x8b79 },
3048                 { 0x06, 0xaa00 },
3049                 { 0x1f, 0x0000 },
3050
3051                 /* Disable hiimpedance detection (RTCT) */
3052                 { 0x1f, 0x0003 },
3053                 { 0x01, 0x328a },
3054                 { 0x1f, 0x0000 }
3055         };
3056
3057         rtl_apply_firmware(tp);
3058
3059         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3060
3061         /* For 4-corner performance improve */
3062         rtl_writephy(tp, 0x1f, 0x0005);
3063         rtl_writephy(tp, 0x05, 0x8b80);
3064         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3065         rtl_writephy(tp, 0x1f, 0x0000);
3066
3067         /* PHY auto speed down */
3068         rtl_writephy(tp, 0x1f, 0x0007);
3069         rtl_writephy(tp, 0x1e, 0x002d);
3070         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3071         rtl_writephy(tp, 0x1f, 0x0000);
3072         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3073
3074         /* Improve 10M EEE waveform */
3075         rtl_writephy(tp, 0x1f, 0x0005);
3076         rtl_writephy(tp, 0x05, 0x8b86);
3077         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3078         rtl_writephy(tp, 0x1f, 0x0000);
3079
3080         /* Improve 2-pair detection performance */
3081         rtl_writephy(tp, 0x1f, 0x0005);
3082         rtl_writephy(tp, 0x05, 0x8b85);
3083         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3084         rtl_writephy(tp, 0x1f, 0x0000);
3085 }
3086
3087 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3088 {
3089         rtl_apply_firmware(tp);
3090
3091         /* For 4-corner performance improve */
3092         rtl_writephy(tp, 0x1f, 0x0005);
3093         rtl_writephy(tp, 0x05, 0x8b80);
3094         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3095         rtl_writephy(tp, 0x1f, 0x0000);
3096
3097         /* PHY auto speed down */
3098         rtl_writephy(tp, 0x1f, 0x0007);
3099         rtl_writephy(tp, 0x1e, 0x002d);
3100         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3101         rtl_writephy(tp, 0x1f, 0x0000);
3102         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3103
3104         /* Improve 10M EEE waveform */
3105         rtl_writephy(tp, 0x1f, 0x0005);
3106         rtl_writephy(tp, 0x05, 0x8b86);
3107         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3108         rtl_writephy(tp, 0x1f, 0x0000);
3109 }
3110
3111 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3112 {
3113         static const struct phy_reg phy_reg_init[] = {
3114                 { 0x1f, 0x0003 },
3115                 { 0x08, 0x441d },
3116                 { 0x01, 0x9100 },
3117                 { 0x1f, 0x0000 }
3118         };
3119
3120         rtl_writephy(tp, 0x1f, 0x0000);
3121         rtl_patchphy(tp, 0x11, 1 << 12);
3122         rtl_patchphy(tp, 0x19, 1 << 13);
3123         rtl_patchphy(tp, 0x10, 1 << 15);
3124
3125         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3126 }
3127
3128 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3129 {
3130         static const struct phy_reg phy_reg_init[] = {
3131                 { 0x1f, 0x0005 },
3132                 { 0x1a, 0x0000 },
3133                 { 0x1f, 0x0000 },
3134
3135                 { 0x1f, 0x0004 },
3136                 { 0x1c, 0x0000 },
3137                 { 0x1f, 0x0000 },
3138
3139                 { 0x1f, 0x0001 },
3140                 { 0x15, 0x7701 },
3141                 { 0x1f, 0x0000 }
3142         };
3143
3144         /* Disable ALDPS before ram code */
3145         rtl_writephy(tp, 0x1f, 0x0000);
3146         rtl_writephy(tp, 0x18, 0x0310);
3147         msleep(100);
3148
3149         rtl_apply_firmware(tp);
3150
3151         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3152 }
3153
3154 static void rtl_hw_phy_config(struct net_device *dev)
3155 {
3156         struct rtl8169_private *tp = netdev_priv(dev);
3157
3158         rtl8169_print_mac_version(tp);
3159
3160         switch (tp->mac_version) {
3161         case RTL_GIGA_MAC_VER_01:
3162                 break;
3163         case RTL_GIGA_MAC_VER_02:
3164         case RTL_GIGA_MAC_VER_03:
3165                 rtl8169s_hw_phy_config(tp);
3166                 break;
3167         case RTL_GIGA_MAC_VER_04:
3168                 rtl8169sb_hw_phy_config(tp);
3169                 break;
3170         case RTL_GIGA_MAC_VER_05:
3171                 rtl8169scd_hw_phy_config(tp);
3172                 break;
3173         case RTL_GIGA_MAC_VER_06:
3174                 rtl8169sce_hw_phy_config(tp);
3175                 break;
3176         case RTL_GIGA_MAC_VER_07:
3177         case RTL_GIGA_MAC_VER_08:
3178         case RTL_GIGA_MAC_VER_09:
3179                 rtl8102e_hw_phy_config(tp);
3180                 break;
3181         case RTL_GIGA_MAC_VER_11:
3182                 rtl8168bb_hw_phy_config(tp);
3183                 break;
3184         case RTL_GIGA_MAC_VER_12:
3185                 rtl8168bef_hw_phy_config(tp);
3186                 break;
3187         case RTL_GIGA_MAC_VER_17:
3188                 rtl8168bef_hw_phy_config(tp);
3189                 break;
3190         case RTL_GIGA_MAC_VER_18:
3191                 rtl8168cp_1_hw_phy_config(tp);
3192                 break;
3193         case RTL_GIGA_MAC_VER_19:
3194                 rtl8168c_1_hw_phy_config(tp);
3195                 break;
3196         case RTL_GIGA_MAC_VER_20:
3197                 rtl8168c_2_hw_phy_config(tp);
3198                 break;
3199         case RTL_GIGA_MAC_VER_21:
3200                 rtl8168c_3_hw_phy_config(tp);
3201                 break;
3202         case RTL_GIGA_MAC_VER_22:
3203                 rtl8168c_4_hw_phy_config(tp);
3204                 break;
3205         case RTL_GIGA_MAC_VER_23:
3206         case RTL_GIGA_MAC_VER_24:
3207                 rtl8168cp_2_hw_phy_config(tp);
3208                 break;
3209         case RTL_GIGA_MAC_VER_25:
3210                 rtl8168d_1_hw_phy_config(tp);
3211                 break;
3212         case RTL_GIGA_MAC_VER_26:
3213                 rtl8168d_2_hw_phy_config(tp);
3214                 break;
3215         case RTL_GIGA_MAC_VER_27:
3216                 rtl8168d_3_hw_phy_config(tp);
3217                 break;
3218         case RTL_GIGA_MAC_VER_28:
3219                 rtl8168d_4_hw_phy_config(tp);
3220                 break;
3221         case RTL_GIGA_MAC_VER_29:
3222         case RTL_GIGA_MAC_VER_30:
3223                 rtl8105e_hw_phy_config(tp);
3224                 break;
3225         case RTL_GIGA_MAC_VER_31:
3226                 /* None. */
3227                 break;
3228         case RTL_GIGA_MAC_VER_32:
3229         case RTL_GIGA_MAC_VER_33:
3230                 rtl8168e_1_hw_phy_config(tp);
3231                 break;
3232         case RTL_GIGA_MAC_VER_34:
3233                 rtl8168e_2_hw_phy_config(tp);
3234                 break;
3235         case RTL_GIGA_MAC_VER_35:
3236                 rtl8168f_1_hw_phy_config(tp);
3237                 break;
3238         case RTL_GIGA_MAC_VER_36:
3239                 rtl8168f_2_hw_phy_config(tp);
3240                 break;
3241
3242         default:
3243                 break;
3244         }
3245 }
3246
3247 static void rtl_phy_work(struct rtl8169_private *tp)
3248 {
3249         struct timer_list *timer = &tp->timer;
3250         void __iomem *ioaddr = tp->mmio_addr;
3251         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3252
3253         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3254
3255         if (tp->phy_reset_pending(tp)) {
3256                 /*
3257                  * A busy loop could burn quite a few cycles on nowadays CPU.
3258                  * Let's delay the execution of the timer for a few ticks.
3259                  */
3260                 timeout = HZ/10;
3261                 goto out_mod_timer;
3262         }
3263
3264         if (tp->link_ok(ioaddr))
3265                 return;
3266
3267         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3268
3269         tp->phy_reset_enable(tp);
3270
3271 out_mod_timer:
3272         mod_timer(timer, jiffies + timeout);
3273 }
3274
3275 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3276 {
3277         if (!test_and_set_bit(flag, tp->wk.flags))
3278                 schedule_work(&tp->wk.work);
3279 }
3280
3281 static void rtl8169_phy_timer(unsigned long __opaque)
3282 {
3283         struct net_device *dev = (struct net_device *)__opaque;
3284         struct rtl8169_private *tp = netdev_priv(dev);
3285
3286         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3287 }
3288
3289 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3290                                   void __iomem *ioaddr)
3291 {
3292         iounmap(ioaddr);
3293         pci_release_regions(pdev);
3294         pci_clear_mwi(pdev);
3295         pci_disable_device(pdev);
3296         free_netdev(dev);
3297 }
3298
3299 static void rtl8169_phy_reset(struct net_device *dev,
3300                               struct rtl8169_private *tp)
3301 {
3302         unsigned int i;
3303
3304         tp->phy_reset_enable(tp);
3305         for (i = 0; i < 100; i++) {
3306                 if (!tp->phy_reset_pending(tp))
3307                         return;
3308                 msleep(1);
3309         }
3310         netif_err(tp, link, dev, "PHY reset failed\n");
3311 }
3312
3313 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3314 {
3315         void __iomem *ioaddr = tp->mmio_addr;
3316
3317         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3318             (RTL_R8(PHYstatus) & TBI_Enable);
3319 }
3320
3321 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3322 {
3323         void __iomem *ioaddr = tp->mmio_addr;
3324
3325         rtl_hw_phy_config(dev);
3326
3327         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3328                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3329                 RTL_W8(0x82, 0x01);
3330         }
3331
3332         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3333
3334         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3335                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3336
3337         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3338                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3339                 RTL_W8(0x82, 0x01);
3340                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3341                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3342         }
3343
3344         rtl8169_phy_reset(dev, tp);
3345
3346         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3347                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3348                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3349                           (tp->mii.supports_gmii ?
3350                            ADVERTISED_1000baseT_Half |
3351                            ADVERTISED_1000baseT_Full : 0));
3352
3353         if (rtl_tbi_enabled(tp))
3354                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3355 }
3356
3357 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3358 {
3359         void __iomem *ioaddr = tp->mmio_addr;
3360         u32 high;
3361         u32 low;
3362
3363         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3364         high = addr[4] | (addr[5] << 8);
3365
3366         rtl_lock_work(tp);
3367
3368         RTL_W8(Cfg9346, Cfg9346_Unlock);
3369
3370         RTL_W32(MAC4, high);
3371         RTL_R32(MAC4);
3372
3373         RTL_W32(MAC0, low);
3374         RTL_R32(MAC0);
3375
3376         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3377                 const struct exgmac_reg e[] = {
3378                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3379                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3380                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3381                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3382                                                                 low  >> 16 },
3383                 };
3384
3385                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3386         }
3387
3388         RTL_W8(Cfg9346, Cfg9346_Lock);
3389
3390         rtl_unlock_work(tp);
3391 }
3392
3393 static int rtl_set_mac_address(struct net_device *dev, void *p)
3394 {
3395         struct rtl8169_private *tp = netdev_priv(dev);
3396         struct sockaddr *addr = p;
3397
3398         if (!is_valid_ether_addr(addr->sa_data))
3399                 return -EADDRNOTAVAIL;
3400
3401         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3402
3403         rtl_rar_set(tp, dev->dev_addr);
3404
3405         return 0;
3406 }
3407
3408 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3409 {
3410         struct rtl8169_private *tp = netdev_priv(dev);
3411         struct mii_ioctl_data *data = if_mii(ifr);
3412
3413         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3414 }
3415
3416 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3417                           struct mii_ioctl_data *data, int cmd)
3418 {
3419         switch (cmd) {
3420         case SIOCGMIIPHY:
3421                 data->phy_id = 32; /* Internal PHY */
3422                 return 0;
3423
3424         case SIOCGMIIREG:
3425                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3426                 return 0;
3427
3428         case SIOCSMIIREG:
3429                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3430                 return 0;
3431         }
3432         return -EOPNOTSUPP;
3433 }
3434
3435 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3436 {
3437         return -EOPNOTSUPP;
3438 }
3439
3440 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3441 {
3442         if (tp->features & RTL_FEATURE_MSI) {
3443                 pci_disable_msi(pdev);
3444                 tp->features &= ~RTL_FEATURE_MSI;
3445         }
3446 }
3447
3448 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3449 {
3450         struct mdio_ops *ops = &tp->mdio_ops;
3451
3452         switch (tp->mac_version) {
3453         case RTL_GIGA_MAC_VER_27:
3454                 ops->write      = r8168dp_1_mdio_write;
3455                 ops->read       = r8168dp_1_mdio_read;
3456                 break;
3457         case RTL_GIGA_MAC_VER_28:
3458         case RTL_GIGA_MAC_VER_31:
3459                 ops->write      = r8168dp_2_mdio_write;
3460                 ops->read       = r8168dp_2_mdio_read;
3461                 break;
3462         default:
3463                 ops->write      = r8169_mdio_write;
3464                 ops->read       = r8169_mdio_read;
3465                 break;
3466         }
3467 }
3468
3469 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3470 {
3471         void __iomem *ioaddr = tp->mmio_addr;
3472
3473         switch (tp->mac_version) {
3474         case RTL_GIGA_MAC_VER_29:
3475         case RTL_GIGA_MAC_VER_30:
3476         case RTL_GIGA_MAC_VER_32:
3477         case RTL_GIGA_MAC_VER_33:
3478         case RTL_GIGA_MAC_VER_34:
3479                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3480                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3481                 break;
3482         default:
3483                 break;
3484         }
3485 }
3486
3487 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3488 {
3489         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3490                 return false;
3491
3492         rtl_writephy(tp, 0x1f, 0x0000);
3493         rtl_writephy(tp, MII_BMCR, 0x0000);
3494
3495         rtl_wol_suspend_quirk(tp);
3496
3497         return true;
3498 }
3499
3500 static void r810x_phy_power_down(struct rtl8169_private *tp)
3501 {
3502         rtl_writephy(tp, 0x1f, 0x0000);
3503         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3504 }
3505
3506 static void r810x_phy_power_up(struct rtl8169_private *tp)
3507 {
3508         rtl_writephy(tp, 0x1f, 0x0000);
3509         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3510 }
3511
3512 static void r810x_pll_power_down(struct rtl8169_private *tp)
3513 {
3514         if (rtl_wol_pll_power_down(tp))
3515                 return;
3516
3517         r810x_phy_power_down(tp);
3518 }
3519
3520 static void r810x_pll_power_up(struct rtl8169_private *tp)
3521 {
3522         r810x_phy_power_up(tp);
3523 }
3524
3525 static void r8168_phy_power_up(struct rtl8169_private *tp)
3526 {
3527         rtl_writephy(tp, 0x1f, 0x0000);
3528         switch (tp->mac_version) {
3529         case RTL_GIGA_MAC_VER_11:
3530         case RTL_GIGA_MAC_VER_12:
3531         case RTL_GIGA_MAC_VER_17:
3532         case RTL_GIGA_MAC_VER_18:
3533         case RTL_GIGA_MAC_VER_19:
3534         case RTL_GIGA_MAC_VER_20:
3535         case RTL_GIGA_MAC_VER_21:
3536         case RTL_GIGA_MAC_VER_22:
3537         case RTL_GIGA_MAC_VER_23:
3538         case RTL_GIGA_MAC_VER_24:
3539         case RTL_GIGA_MAC_VER_25:
3540         case RTL_GIGA_MAC_VER_26:
3541         case RTL_GIGA_MAC_VER_27:
3542         case RTL_GIGA_MAC_VER_28:
3543         case RTL_GIGA_MAC_VER_31:
3544                 rtl_writephy(tp, 0x0e, 0x0000);
3545                 break;
3546         default:
3547                 break;
3548         }
3549         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3550 }
3551
3552 static void r8168_phy_power_down(struct rtl8169_private *tp)
3553 {
3554         rtl_writephy(tp, 0x1f, 0x0000);
3555         switch (tp->mac_version) {
3556         case RTL_GIGA_MAC_VER_32:
3557         case RTL_GIGA_MAC_VER_33:
3558                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3559                 break;
3560
3561         case RTL_GIGA_MAC_VER_11:
3562         case RTL_GIGA_MAC_VER_12:
3563         case RTL_GIGA_MAC_VER_17:
3564         case RTL_GIGA_MAC_VER_18:
3565         case RTL_GIGA_MAC_VER_19:
3566         case RTL_GIGA_MAC_VER_20:
3567         case RTL_GIGA_MAC_VER_21:
3568         case RTL_GIGA_MAC_VER_22:
3569         case RTL_GIGA_MAC_VER_23:
3570         case RTL_GIGA_MAC_VER_24:
3571         case RTL_GIGA_MAC_VER_25:
3572         case RTL_GIGA_MAC_VER_26:
3573         case RTL_GIGA_MAC_VER_27:
3574         case RTL_GIGA_MAC_VER_28:
3575         case RTL_GIGA_MAC_VER_31:
3576                 rtl_writephy(tp, 0x0e, 0x0200);
3577         default:
3578                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3579                 break;
3580         }
3581 }
3582
3583 static void r8168_pll_power_down(struct rtl8169_private *tp)
3584 {
3585         void __iomem *ioaddr = tp->mmio_addr;
3586
3587         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3588              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3589              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3590             r8168dp_check_dash(tp)) {
3591                 return;
3592         }
3593
3594         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3595              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3596             (RTL_R16(CPlusCmd) & ASF)) {
3597                 return;
3598         }
3599
3600         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3601             tp->mac_version == RTL_GIGA_MAC_VER_33)
3602                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3603
3604         if (rtl_wol_pll_power_down(tp))
3605                 return;
3606
3607         r8168_phy_power_down(tp);
3608
3609         switch (tp->mac_version) {
3610         case RTL_GIGA_MAC_VER_25:
3611         case RTL_GIGA_MAC_VER_26:
3612         case RTL_GIGA_MAC_VER_27:
3613         case RTL_GIGA_MAC_VER_28:
3614         case RTL_GIGA_MAC_VER_31:
3615         case RTL_GIGA_MAC_VER_32:
3616         case RTL_GIGA_MAC_VER_33:
3617                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3618                 break;
3619         }
3620 }
3621
3622 static void r8168_pll_power_up(struct rtl8169_private *tp)
3623 {
3624         void __iomem *ioaddr = tp->mmio_addr;
3625
3626         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3627              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3628              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3629             r8168dp_check_dash(tp)) {
3630                 return;
3631         }
3632
3633         switch (tp->mac_version) {
3634         case RTL_GIGA_MAC_VER_25:
3635         case RTL_GIGA_MAC_VER_26:
3636         case RTL_GIGA_MAC_VER_27:
3637         case RTL_GIGA_MAC_VER_28:
3638         case RTL_GIGA_MAC_VER_31:
3639         case RTL_GIGA_MAC_VER_32:
3640         case RTL_GIGA_MAC_VER_33:
3641                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3642                 break;
3643         }
3644
3645         r8168_phy_power_up(tp);
3646 }
3647
3648 static void rtl_generic_op(struct rtl8169_private *tp,
3649                            void (*op)(struct rtl8169_private *))
3650 {
3651         if (op)
3652                 op(tp);
3653 }
3654
3655 static void rtl_pll_power_down(struct rtl8169_private *tp)
3656 {
3657         rtl_generic_op(tp, tp->pll_power_ops.down);
3658 }
3659
3660 static void rtl_pll_power_up(struct rtl8169_private *tp)
3661 {
3662         rtl_generic_op(tp, tp->pll_power_ops.up);
3663 }
3664
3665 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3666 {
3667         struct pll_power_ops *ops = &tp->pll_power_ops;
3668
3669         switch (tp->mac_version) {
3670         case RTL_GIGA_MAC_VER_07:
3671         case RTL_GIGA_MAC_VER_08:
3672         case RTL_GIGA_MAC_VER_09:
3673         case RTL_GIGA_MAC_VER_10:
3674         case RTL_GIGA_MAC_VER_16:
3675         case RTL_GIGA_MAC_VER_29:
3676         case RTL_GIGA_MAC_VER_30:
3677                 ops->down       = r810x_pll_power_down;
3678                 ops->up         = r810x_pll_power_up;
3679                 break;
3680
3681         case RTL_GIGA_MAC_VER_11:
3682         case RTL_GIGA_MAC_VER_12:
3683         case RTL_GIGA_MAC_VER_17:
3684         case RTL_GIGA_MAC_VER_18:
3685         case RTL_GIGA_MAC_VER_19:
3686         case RTL_GIGA_MAC_VER_20:
3687         case RTL_GIGA_MAC_VER_21:
3688         case RTL_GIGA_MAC_VER_22:
3689         case RTL_GIGA_MAC_VER_23:
3690         case RTL_GIGA_MAC_VER_24:
3691         case RTL_GIGA_MAC_VER_25:
3692         case RTL_GIGA_MAC_VER_26:
3693         case RTL_GIGA_MAC_VER_27:
3694         case RTL_GIGA_MAC_VER_28:
3695         case RTL_GIGA_MAC_VER_31:
3696         case RTL_GIGA_MAC_VER_32:
3697         case RTL_GIGA_MAC_VER_33:
3698         case RTL_GIGA_MAC_VER_34:
3699         case RTL_GIGA_MAC_VER_35:
3700         case RTL_GIGA_MAC_VER_36:
3701                 ops->down       = r8168_pll_power_down;
3702                 ops->up         = r8168_pll_power_up;
3703                 break;
3704
3705         default:
3706                 ops->down       = NULL;
3707                 ops->up         = NULL;
3708                 break;
3709         }
3710 }
3711
3712 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3713 {
3714         void __iomem *ioaddr = tp->mmio_addr;
3715
3716         switch (tp->mac_version) {
3717         case RTL_GIGA_MAC_VER_01:
3718         case RTL_GIGA_MAC_VER_02:
3719         case RTL_GIGA_MAC_VER_03:
3720         case RTL_GIGA_MAC_VER_04:
3721         case RTL_GIGA_MAC_VER_05:
3722         case RTL_GIGA_MAC_VER_06:
3723         case RTL_GIGA_MAC_VER_10:
3724         case RTL_GIGA_MAC_VER_11:
3725         case RTL_GIGA_MAC_VER_12:
3726         case RTL_GIGA_MAC_VER_13:
3727         case RTL_GIGA_MAC_VER_14:
3728         case RTL_GIGA_MAC_VER_15:
3729         case RTL_GIGA_MAC_VER_16:
3730         case RTL_GIGA_MAC_VER_17:
3731                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3732                 break;
3733         case RTL_GIGA_MAC_VER_18:
3734         case RTL_GIGA_MAC_VER_19:
3735         case RTL_GIGA_MAC_VER_20:
3736         case RTL_GIGA_MAC_VER_21:
3737         case RTL_GIGA_MAC_VER_22:
3738         case RTL_GIGA_MAC_VER_23:
3739         case RTL_GIGA_MAC_VER_24:
3740                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3741                 break;
3742         default:
3743                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3744                 break;
3745         }
3746 }
3747
3748 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3749 {
3750         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3751 }
3752
3753 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3754 {
3755         void __iomem *ioaddr = tp->mmio_addr;
3756
3757         RTL_W8(Cfg9346, Cfg9346_Unlock);
3758         rtl_generic_op(tp, tp->jumbo_ops.enable);
3759         RTL_W8(Cfg9346, Cfg9346_Lock);
3760 }
3761
3762 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3763 {
3764         void __iomem *ioaddr = tp->mmio_addr;
3765
3766         RTL_W8(Cfg9346, Cfg9346_Unlock);
3767         rtl_generic_op(tp, tp->jumbo_ops.disable);
3768         RTL_W8(Cfg9346, Cfg9346_Lock);
3769 }
3770
3771 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3772 {
3773         void __iomem *ioaddr = tp->mmio_addr;
3774
3775         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3776         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3777         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3778 }
3779
3780 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3781 {
3782         void __iomem *ioaddr = tp->mmio_addr;
3783
3784         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3785         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3786         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3787 }
3788
3789 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3790 {
3791         void __iomem *ioaddr = tp->mmio_addr;
3792
3793         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3794 }
3795
3796 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3797 {
3798         void __iomem *ioaddr = tp->mmio_addr;
3799
3800         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3801 }
3802
3803 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3804 {
3805         void __iomem *ioaddr = tp->mmio_addr;
3806
3807         RTL_W8(MaxTxPacketSize, 0x3f);
3808         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3809         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3810         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3811 }
3812
3813 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3814 {
3815         void __iomem *ioaddr = tp->mmio_addr;
3816
3817         RTL_W8(MaxTxPacketSize, 0x0c);
3818         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3819         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3820         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3821 }
3822
3823 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3824 {
3825         rtl_tx_performance_tweak(tp->pci_dev,
3826                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3827 }
3828
3829 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3830 {
3831         rtl_tx_performance_tweak(tp->pci_dev,
3832                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3833 }
3834
3835 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3836 {
3837         void __iomem *ioaddr = tp->mmio_addr;
3838
3839         r8168b_0_hw_jumbo_enable(tp);
3840
3841         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3842 }
3843
3844 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3845 {
3846         void __iomem *ioaddr = tp->mmio_addr;
3847
3848         r8168b_0_hw_jumbo_disable(tp);
3849
3850         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3851 }
3852
3853 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3854 {
3855         struct jumbo_ops *ops = &tp->jumbo_ops;
3856
3857         switch (tp->mac_version) {
3858         case RTL_GIGA_MAC_VER_11:
3859                 ops->disable    = r8168b_0_hw_jumbo_disable;
3860                 ops->enable     = r8168b_0_hw_jumbo_enable;
3861                 break;
3862         case RTL_GIGA_MAC_VER_12:
3863         case RTL_GIGA_MAC_VER_17:
3864                 ops->disable    = r8168b_1_hw_jumbo_disable;
3865                 ops->enable     = r8168b_1_hw_jumbo_enable;
3866                 break;
3867         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3868         case RTL_GIGA_MAC_VER_19:
3869         case RTL_GIGA_MAC_VER_20:
3870         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3871         case RTL_GIGA_MAC_VER_22:
3872         case RTL_GIGA_MAC_VER_23:
3873         case RTL_GIGA_MAC_VER_24:
3874         case RTL_GIGA_MAC_VER_25:
3875         case RTL_GIGA_MAC_VER_26:
3876                 ops->disable    = r8168c_hw_jumbo_disable;
3877                 ops->enable     = r8168c_hw_jumbo_enable;
3878                 break;
3879         case RTL_GIGA_MAC_VER_27:
3880         case RTL_GIGA_MAC_VER_28:
3881                 ops->disable    = r8168dp_hw_jumbo_disable;
3882                 ops->enable     = r8168dp_hw_jumbo_enable;
3883                 break;
3884         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3885         case RTL_GIGA_MAC_VER_32:
3886         case RTL_GIGA_MAC_VER_33:
3887         case RTL_GIGA_MAC_VER_34:
3888                 ops->disable    = r8168e_hw_jumbo_disable;
3889                 ops->enable     = r8168e_hw_jumbo_enable;
3890                 break;
3891
3892         /*
3893          * No action needed for jumbo frames with 8169.
3894          * No jumbo for 810x at all.
3895          */
3896         default:
3897                 ops->disable    = NULL;
3898                 ops->enable     = NULL;
3899                 break;
3900         }
3901 }
3902
3903 static void rtl_hw_reset(struct rtl8169_private *tp)
3904 {
3905         void __iomem *ioaddr = tp->mmio_addr;
3906         int i;
3907
3908         /* Soft reset the chip. */
3909         RTL_W8(ChipCmd, CmdReset);
3910
3911         /* Check that the chip has finished the reset. */
3912         for (i = 0; i < 100; i++) {
3913                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3914                         break;
3915                 udelay(100);
3916         }
3917 }
3918
3919 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3920 {
3921         struct rtl_fw *rtl_fw;
3922         const char *name;
3923         int rc = -ENOMEM;
3924
3925         name = rtl_lookup_firmware_name(tp);
3926         if (!name)
3927                 goto out_no_firmware;
3928
3929         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3930         if (!rtl_fw)
3931                 goto err_warn;
3932
3933         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3934         if (rc < 0)
3935                 goto err_free;
3936
3937         rc = rtl_check_firmware(tp, rtl_fw);
3938         if (rc < 0)
3939                 goto err_release_firmware;
3940
3941         tp->rtl_fw = rtl_fw;
3942 out:
3943         return;
3944
3945 err_release_firmware:
3946         release_firmware(rtl_fw->fw);
3947 err_free:
3948         kfree(rtl_fw);
3949 err_warn:
3950         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3951                    name, rc);
3952 out_no_firmware:
3953         tp->rtl_fw = NULL;
3954         goto out;
3955 }
3956
3957 static void rtl_request_firmware(struct rtl8169_private *tp)
3958 {
3959         if (IS_ERR(tp->rtl_fw))
3960                 rtl_request_uncached_firmware(tp);
3961 }
3962
3963 static void rtl_rx_close(struct rtl8169_private *tp)
3964 {
3965         void __iomem *ioaddr = tp->mmio_addr;
3966
3967         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3968 }
3969
3970 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3971 {
3972         void __iomem *ioaddr = tp->mmio_addr;
3973
3974         /* Disable interrupts */
3975         rtl8169_irq_mask_and_ack(tp);
3976
3977         rtl_rx_close(tp);
3978
3979         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3980             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3981             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3982                 while (RTL_R8(TxPoll) & NPQ)
3983                         udelay(20);
3984         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
3985                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
3986                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
3987                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3988                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3989                         udelay(100);
3990         } else {
3991                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3992                 udelay(100);
3993         }
3994
3995         rtl_hw_reset(tp);
3996 }
3997
3998 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3999 {
4000         void __iomem *ioaddr = tp->mmio_addr;
4001
4002         /* Set DMA burst size and Interframe Gap Time */
4003         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4004                 (InterFrameGap << TxInterFrameGapShift));
4005 }
4006
4007 static void rtl_hw_start(struct net_device *dev)
4008 {
4009         struct rtl8169_private *tp = netdev_priv(dev);
4010
4011         tp->hw_start(dev);
4012
4013         rtl_irq_enable_all(tp);
4014 }
4015
4016 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4017                                          void __iomem *ioaddr)
4018 {
4019         /*
4020          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4021          * register to be written before TxDescAddrLow to work.
4022          * Switching from MMIO to I/O access fixes the issue as well.
4023          */
4024         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4025         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4026         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4027         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4028 }
4029
4030 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4031 {
4032         u16 cmd;
4033
4034         cmd = RTL_R16(CPlusCmd);
4035         RTL_W16(CPlusCmd, cmd);
4036         return cmd;
4037 }
4038
4039 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4040 {
4041         /* Low hurts. Let's disable the filtering. */
4042         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4043 }
4044
4045 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4046 {
4047         static const struct rtl_cfg2_info {
4048                 u32 mac_version;
4049                 u32 clk;
4050                 u32 val;
4051         } cfg2_info [] = {
4052                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4053                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4054                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4055                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4056         };
4057         const struct rtl_cfg2_info *p = cfg2_info;
4058         unsigned int i;
4059         u32 clk;
4060
4061         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4062         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4063                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4064                         RTL_W32(0x7c, p->val);
4065                         break;
4066                 }
4067         }
4068 }
4069
4070 static void rtl_set_rx_mode(struct net_device *dev)
4071 {
4072         struct rtl8169_private *tp = netdev_priv(dev);
4073         void __iomem *ioaddr = tp->mmio_addr;
4074         u32 mc_filter[2];       /* Multicast hash filter */
4075         int rx_mode;
4076         u32 tmp = 0;
4077
4078         if (dev->flags & IFF_PROMISC) {
4079                 /* Unconditionally log net taps. */
4080                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4081                 rx_mode =
4082                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4083                     AcceptAllPhys;
4084                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4085         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4086                    (dev->flags & IFF_ALLMULTI)) {
4087                 /* Too many to filter perfectly -- accept all multicasts. */
4088                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4089                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4090         } else {
4091                 struct netdev_hw_addr *ha;
4092
4093                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4094                 mc_filter[1] = mc_filter[0] = 0;
4095                 netdev_for_each_mc_addr(ha, dev) {
4096                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4097                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4098                         rx_mode |= AcceptMulticast;
4099                 }
4100         }
4101
4102         if (dev->features & NETIF_F_RXALL)
4103                 rx_mode |= (AcceptErr | AcceptRunt);
4104
4105         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4106
4107         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4108                 u32 data = mc_filter[0];
4109
4110                 mc_filter[0] = swab32(mc_filter[1]);
4111                 mc_filter[1] = swab32(data);
4112         }
4113
4114         RTL_W32(MAR0 + 4, mc_filter[1]);
4115         RTL_W32(MAR0 + 0, mc_filter[0]);
4116
4117         RTL_W32(RxConfig, tmp);
4118 }
4119
4120 static void rtl_hw_start_8169(struct net_device *dev)
4121 {
4122         struct rtl8169_private *tp = netdev_priv(dev);
4123         void __iomem *ioaddr = tp->mmio_addr;
4124         struct pci_dev *pdev = tp->pci_dev;
4125
4126         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4127                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4128                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4129         }
4130
4131         RTL_W8(Cfg9346, Cfg9346_Unlock);
4132         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4133             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4134             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4135             tp->mac_version == RTL_GIGA_MAC_VER_04)
4136                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4137
4138         rtl_init_rxcfg(tp);
4139
4140         RTL_W8(EarlyTxThres, NoEarlyTx);
4141
4142         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4143
4144         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4145             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4146             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4147             tp->mac_version == RTL_GIGA_MAC_VER_04)
4148                 rtl_set_rx_tx_config_registers(tp);
4149
4150         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4151
4152         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4153             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4154                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4155                         "Bit-3 and bit-14 MUST be 1\n");
4156                 tp->cp_cmd |= (1 << 14);
4157         }
4158
4159         RTL_W16(CPlusCmd, tp->cp_cmd);
4160
4161         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4162
4163         /*
4164          * Undocumented corner. Supposedly:
4165          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4166          */
4167         RTL_W16(IntrMitigate, 0x0000);
4168
4169         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4170
4171         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4172             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4173             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4174             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4175                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4176                 rtl_set_rx_tx_config_registers(tp);
4177         }
4178
4179         RTL_W8(Cfg9346, Cfg9346_Lock);
4180
4181         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4182         RTL_R8(IntrMask);
4183
4184         RTL_W32(RxMissed, 0);
4185
4186         rtl_set_rx_mode(dev);
4187
4188         /* no early-rx interrupts */
4189         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4190 }
4191
4192 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4193 {
4194         u32 csi;
4195
4196         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4197         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4198 }
4199
4200 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4201 {
4202         rtl_csi_access_enable(ioaddr, 0x17000000);
4203 }
4204
4205 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4206 {
4207         rtl_csi_access_enable(ioaddr, 0x27000000);
4208 }
4209
4210 struct ephy_info {
4211         unsigned int offset;
4212         u16 mask;
4213         u16 bits;
4214 };
4215
4216 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4217 {
4218         u16 w;
4219
4220         while (len-- > 0) {
4221                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4222                 rtl_ephy_write(ioaddr, e->offset, w);
4223                 e++;
4224         }
4225 }
4226
4227 static void rtl_disable_clock_request(struct pci_dev *pdev)
4228 {
4229         int cap = pci_pcie_cap(pdev);
4230
4231         if (cap) {
4232                 u16 ctl;
4233
4234                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4235                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4236                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4237         }
4238 }
4239
4240 static void rtl_enable_clock_request(struct pci_dev *pdev)
4241 {
4242         int cap = pci_pcie_cap(pdev);
4243
4244         if (cap) {
4245                 u16 ctl;
4246
4247                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4248                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4249                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4250         }
4251 }
4252
4253 #define R8168_CPCMD_QUIRK_MASK (\
4254         EnableBist | \
4255         Mac_dbgo_oe | \
4256         Force_half_dup | \
4257         Force_rxflow_en | \
4258         Force_txflow_en | \
4259         Cxpl_dbg_sel | \
4260         ASF | \
4261         PktCntrDisable | \
4262         Mac_dbgo_sel)
4263
4264 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4265 {
4266         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4267
4268         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4269
4270         rtl_tx_performance_tweak(pdev,
4271                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4272 }
4273
4274 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4275 {
4276         rtl_hw_start_8168bb(ioaddr, pdev);
4277
4278         RTL_W8(MaxTxPacketSize, TxPacketMax);
4279
4280         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4281 }
4282
4283 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4284 {
4285         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4286
4287         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4288
4289         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4290
4291         rtl_disable_clock_request(pdev);
4292
4293         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4294 }
4295
4296 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4297 {
4298         static const struct ephy_info e_info_8168cp[] = {
4299                 { 0x01, 0,      0x0001 },
4300                 { 0x02, 0x0800, 0x1000 },
4301                 { 0x03, 0,      0x0042 },
4302                 { 0x06, 0x0080, 0x0000 },
4303                 { 0x07, 0,      0x2000 }
4304         };
4305
4306         rtl_csi_access_enable_2(ioaddr);
4307
4308         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4309
4310         __rtl_hw_start_8168cp(ioaddr, pdev);
4311 }
4312
4313 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4314 {
4315         rtl_csi_access_enable_2(ioaddr);
4316
4317         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4318
4319         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4320
4321         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4322 }
4323
4324 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4325 {
4326         rtl_csi_access_enable_2(ioaddr);
4327
4328         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4329
4330         /* Magic. */
4331         RTL_W8(DBG_REG, 0x20);
4332
4333         RTL_W8(MaxTxPacketSize, TxPacketMax);
4334
4335         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4336
4337         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4338 }
4339
4340 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4341 {
4342         static const struct ephy_info e_info_8168c_1[] = {
4343                 { 0x02, 0x0800, 0x1000 },
4344                 { 0x03, 0,      0x0002 },
4345                 { 0x06, 0x0080, 0x0000 }
4346         };
4347
4348         rtl_csi_access_enable_2(ioaddr);
4349
4350         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4351
4352         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4353
4354         __rtl_hw_start_8168cp(ioaddr, pdev);
4355 }
4356
4357 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4358 {
4359         static const struct ephy_info e_info_8168c_2[] = {
4360                 { 0x01, 0,      0x0001 },
4361                 { 0x03, 0x0400, 0x0220 }
4362         };
4363
4364         rtl_csi_access_enable_2(ioaddr);
4365
4366         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4367
4368         __rtl_hw_start_8168cp(ioaddr, pdev);
4369 }
4370
4371 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4372 {
4373         rtl_hw_start_8168c_2(ioaddr, pdev);
4374 }
4375
4376 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4377 {
4378         rtl_csi_access_enable_2(ioaddr);
4379
4380         __rtl_hw_start_8168cp(ioaddr, pdev);
4381 }
4382
4383 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4384 {
4385         rtl_csi_access_enable_2(ioaddr);
4386
4387         rtl_disable_clock_request(pdev);
4388
4389         RTL_W8(MaxTxPacketSize, TxPacketMax);
4390
4391         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4392
4393         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4394 }
4395
4396 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4397 {
4398         rtl_csi_access_enable_1(ioaddr);
4399
4400         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4401
4402         RTL_W8(MaxTxPacketSize, TxPacketMax);
4403
4404         rtl_disable_clock_request(pdev);
4405 }
4406
4407 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4408 {
4409         static const struct ephy_info e_info_8168d_4[] = {
4410                 { 0x0b, ~0,     0x48 },
4411                 { 0x19, 0x20,   0x50 },
4412                 { 0x0c, ~0,     0x20 }
4413         };
4414         int i;
4415
4416         rtl_csi_access_enable_1(ioaddr);
4417
4418         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4419
4420         RTL_W8(MaxTxPacketSize, TxPacketMax);
4421
4422         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4423                 const struct ephy_info *e = e_info_8168d_4 + i;
4424                 u16 w;
4425
4426                 w = rtl_ephy_read(ioaddr, e->offset);
4427                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4428         }
4429
4430         rtl_enable_clock_request(pdev);
4431 }
4432
4433 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4434 {
4435         static const struct ephy_info e_info_8168e_1[] = {
4436                 { 0x00, 0x0200, 0x0100 },
4437                 { 0x00, 0x0000, 0x0004 },
4438                 { 0x06, 0x0002, 0x0001 },
4439                 { 0x06, 0x0000, 0x0030 },
4440                 { 0x07, 0x0000, 0x2000 },
4441                 { 0x00, 0x0000, 0x0020 },
4442                 { 0x03, 0x5800, 0x2000 },
4443                 { 0x03, 0x0000, 0x0001 },
4444                 { 0x01, 0x0800, 0x1000 },
4445                 { 0x07, 0x0000, 0x4000 },
4446                 { 0x1e, 0x0000, 0x2000 },
4447                 { 0x19, 0xffff, 0xfe6c },
4448                 { 0x0a, 0x0000, 0x0040 }
4449         };
4450
4451         rtl_csi_access_enable_2(ioaddr);
4452
4453         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4454
4455         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4456
4457         RTL_W8(MaxTxPacketSize, TxPacketMax);
4458
4459         rtl_disable_clock_request(pdev);
4460
4461         /* Reset tx FIFO pointer */
4462         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4463         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4464
4465         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4466 }
4467
4468 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4469 {
4470         static const struct ephy_info e_info_8168e_2[] = {
4471                 { 0x09, 0x0000, 0x0080 },
4472                 { 0x19, 0x0000, 0x0224 }
4473         };
4474
4475         rtl_csi_access_enable_1(ioaddr);
4476
4477         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4478
4479         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4480
4481         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4482         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4483         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4484         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4485         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4486         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4487         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4488         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4489                      ERIAR_EXGMAC);
4490
4491         RTL_W8(MaxTxPacketSize, EarlySize);
4492
4493         rtl_disable_clock_request(pdev);
4494
4495         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4496         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4497
4498         /* Adjust EEE LED frequency */
4499         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4500
4501         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4502         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4503         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4504 }
4505
4506 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4507 {
4508         static const struct ephy_info e_info_8168f_1[] = {
4509                 { 0x06, 0x00c0, 0x0020 },
4510                 { 0x08, 0x0001, 0x0002 },
4511                 { 0x09, 0x0000, 0x0080 },
4512                 { 0x19, 0x0000, 0x0224 }
4513         };
4514
4515         rtl_csi_access_enable_1(ioaddr);
4516
4517         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4518
4519         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4520
4521         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4522         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4523         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4524         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4525         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4526         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4527         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4528         rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4529         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4530         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4531         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4532                      ERIAR_EXGMAC);
4533
4534         RTL_W8(MaxTxPacketSize, EarlySize);
4535
4536         rtl_disable_clock_request(pdev);
4537
4538         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4539         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4540
4541         /* Adjust EEE LED frequency */
4542         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4543
4544         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4545         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4546         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4547 }
4548
4549 static void rtl_hw_start_8168(struct net_device *dev)
4550 {
4551         struct rtl8169_private *tp = netdev_priv(dev);
4552         void __iomem *ioaddr = tp->mmio_addr;
4553         struct pci_dev *pdev = tp->pci_dev;
4554
4555         RTL_W8(Cfg9346, Cfg9346_Unlock);
4556
4557         RTL_W8(MaxTxPacketSize, TxPacketMax);
4558
4559         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4560
4561         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4562
4563         RTL_W16(CPlusCmd, tp->cp_cmd);
4564
4565         RTL_W16(IntrMitigate, 0x5151);
4566
4567         /* Work around for RxFIFO overflow. */
4568         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4569                 tp->event_slow |= RxFIFOOver | PCSTimeout;
4570                 tp->event_slow &= ~RxOverflow;
4571         }
4572
4573         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4574
4575         rtl_set_rx_mode(dev);
4576
4577         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4578                 (InterFrameGap << TxInterFrameGapShift));
4579
4580         RTL_R8(IntrMask);
4581
4582         switch (tp->mac_version) {
4583         case RTL_GIGA_MAC_VER_11:
4584                 rtl_hw_start_8168bb(ioaddr, pdev);
4585                 break;
4586
4587         case RTL_GIGA_MAC_VER_12:
4588         case RTL_GIGA_MAC_VER_17:
4589                 rtl_hw_start_8168bef(ioaddr, pdev);
4590                 break;
4591
4592         case RTL_GIGA_MAC_VER_18:
4593                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4594                 break;
4595
4596         case RTL_GIGA_MAC_VER_19:
4597                 rtl_hw_start_8168c_1(ioaddr, pdev);
4598                 break;
4599
4600         case RTL_GIGA_MAC_VER_20:
4601                 rtl_hw_start_8168c_2(ioaddr, pdev);
4602                 break;
4603
4604         case RTL_GIGA_MAC_VER_21:
4605                 rtl_hw_start_8168c_3(ioaddr, pdev);
4606                 break;
4607
4608         case RTL_GIGA_MAC_VER_22:
4609                 rtl_hw_start_8168c_4(ioaddr, pdev);
4610                 break;
4611
4612         case RTL_GIGA_MAC_VER_23:
4613                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4614                 break;
4615
4616         case RTL_GIGA_MAC_VER_24:
4617                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4618                 break;
4619
4620         case RTL_GIGA_MAC_VER_25:
4621         case RTL_GIGA_MAC_VER_26:
4622         case RTL_GIGA_MAC_VER_27:
4623                 rtl_hw_start_8168d(ioaddr, pdev);
4624                 break;
4625
4626         case RTL_GIGA_MAC_VER_28:
4627                 rtl_hw_start_8168d_4(ioaddr, pdev);
4628                 break;
4629
4630         case RTL_GIGA_MAC_VER_31:
4631                 rtl_hw_start_8168dp(ioaddr, pdev);
4632                 break;
4633
4634         case RTL_GIGA_MAC_VER_32:
4635         case RTL_GIGA_MAC_VER_33:
4636                 rtl_hw_start_8168e_1(ioaddr, pdev);
4637                 break;
4638         case RTL_GIGA_MAC_VER_34:
4639                 rtl_hw_start_8168e_2(ioaddr, pdev);
4640                 break;
4641
4642         case RTL_GIGA_MAC_VER_35:
4643         case RTL_GIGA_MAC_VER_36:
4644                 rtl_hw_start_8168f_1(ioaddr, pdev);
4645                 break;
4646
4647         default:
4648                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4649                         dev->name, tp->mac_version);
4650                 break;
4651         }
4652
4653         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4654
4655         RTL_W8(Cfg9346, Cfg9346_Lock);
4656
4657         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4658 }
4659
4660 #define R810X_CPCMD_QUIRK_MASK (\
4661         EnableBist | \
4662         Mac_dbgo_oe | \
4663         Force_half_dup | \
4664         Force_rxflow_en | \
4665         Force_txflow_en | \
4666         Cxpl_dbg_sel | \
4667         ASF | \
4668         PktCntrDisable | \
4669         Mac_dbgo_sel)
4670
4671 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4672 {
4673         static const struct ephy_info e_info_8102e_1[] = {
4674                 { 0x01, 0, 0x6e65 },
4675                 { 0x02, 0, 0x091f },
4676                 { 0x03, 0, 0xc2f9 },
4677                 { 0x06, 0, 0xafb5 },
4678                 { 0x07, 0, 0x0e00 },
4679                 { 0x19, 0, 0xec80 },
4680                 { 0x01, 0, 0x2e65 },
4681                 { 0x01, 0, 0x6e65 }
4682         };
4683         u8 cfg1;
4684
4685         rtl_csi_access_enable_2(ioaddr);
4686
4687         RTL_W8(DBG_REG, FIX_NAK_1);
4688
4689         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4690
4691         RTL_W8(Config1,
4692                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4693         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4694
4695         cfg1 = RTL_R8(Config1);
4696         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4697                 RTL_W8(Config1, cfg1 & ~LEDS0);
4698
4699         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4700 }
4701
4702 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4703 {
4704         rtl_csi_access_enable_2(ioaddr);
4705
4706         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4707
4708         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4709         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4710 }
4711
4712 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4713 {
4714         rtl_hw_start_8102e_2(ioaddr, pdev);
4715
4716         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4717 }
4718
4719 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4720 {
4721         static const struct ephy_info e_info_8105e_1[] = {
4722                 { 0x07, 0, 0x4000 },
4723                 { 0x19, 0, 0x0200 },
4724                 { 0x19, 0, 0x0020 },
4725                 { 0x1e, 0, 0x2000 },
4726                 { 0x03, 0, 0x0001 },
4727                 { 0x19, 0, 0x0100 },
4728                 { 0x19, 0, 0x0004 },
4729                 { 0x0a, 0, 0x0020 }
4730         };
4731
4732         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4733         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4734
4735         /* Disable Early Tally Counter */
4736         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4737
4738         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4739         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4740
4741         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4742 }
4743
4744 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4745 {
4746         rtl_hw_start_8105e_1(ioaddr, pdev);
4747         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4748 }
4749
4750 static void rtl_hw_start_8101(struct net_device *dev)
4751 {
4752         struct rtl8169_private *tp = netdev_priv(dev);
4753         void __iomem *ioaddr = tp->mmio_addr;
4754         struct pci_dev *pdev = tp->pci_dev;
4755
4756         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
4757                 tp->event_slow &= ~RxFIFOOver;
4758
4759         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4760             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4761                 int cap = pci_pcie_cap(pdev);
4762
4763                 if (cap) {
4764                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4765                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4766                 }
4767         }
4768
4769         RTL_W8(Cfg9346, Cfg9346_Unlock);
4770
4771         switch (tp->mac_version) {
4772         case RTL_GIGA_MAC_VER_07:
4773                 rtl_hw_start_8102e_1(ioaddr, pdev);
4774                 break;
4775
4776         case RTL_GIGA_MAC_VER_08:
4777                 rtl_hw_start_8102e_3(ioaddr, pdev);
4778                 break;
4779
4780         case RTL_GIGA_MAC_VER_09:
4781                 rtl_hw_start_8102e_2(ioaddr, pdev);
4782                 break;
4783
4784         case RTL_GIGA_MAC_VER_29:
4785                 rtl_hw_start_8105e_1(ioaddr, pdev);
4786                 break;
4787         case RTL_GIGA_MAC_VER_30:
4788                 rtl_hw_start_8105e_2(ioaddr, pdev);
4789                 break;
4790         }
4791
4792         RTL_W8(Cfg9346, Cfg9346_Lock);
4793
4794         RTL_W8(MaxTxPacketSize, TxPacketMax);
4795
4796         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4797
4798         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4799         RTL_W16(CPlusCmd, tp->cp_cmd);
4800
4801         RTL_W16(IntrMitigate, 0x0000);
4802
4803         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4804
4805         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4806         rtl_set_rx_tx_config_registers(tp);
4807
4808         RTL_R8(IntrMask);
4809
4810         rtl_set_rx_mode(dev);
4811
4812         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4813 }
4814
4815 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4816 {
4817         struct rtl8169_private *tp = netdev_priv(dev);
4818
4819         if (new_mtu < ETH_ZLEN ||
4820             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4821                 return -EINVAL;
4822
4823         if (new_mtu > ETH_DATA_LEN)
4824                 rtl_hw_jumbo_enable(tp);
4825         else
4826                 rtl_hw_jumbo_disable(tp);
4827
4828         dev->mtu = new_mtu;
4829         netdev_update_features(dev);
4830
4831         return 0;
4832 }
4833
4834 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4835 {
4836         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4837         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4838 }
4839
4840 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4841                                      void **data_buff, struct RxDesc *desc)
4842 {
4843         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4844                          DMA_FROM_DEVICE);
4845
4846         kfree(*data_buff);
4847         *data_buff = NULL;
4848         rtl8169_make_unusable_by_asic(desc);
4849 }
4850
4851 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4852 {
4853         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4854
4855         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4856 }
4857
4858 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4859                                        u32 rx_buf_sz)
4860 {
4861         desc->addr = cpu_to_le64(mapping);
4862         wmb();
4863         rtl8169_mark_to_asic(desc, rx_buf_sz);
4864 }
4865
4866 static inline void *rtl8169_align(void *data)
4867 {
4868         return (void *)ALIGN((long)data, 16);
4869 }
4870
4871 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4872                                              struct RxDesc *desc)
4873 {
4874         void *data;
4875         dma_addr_t mapping;
4876         struct device *d = &tp->pci_dev->dev;
4877         struct net_device *dev = tp->dev;
4878         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4879
4880         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4881         if (!data)
4882                 return NULL;
4883
4884         if (rtl8169_align(data) != data) {
4885                 kfree(data);
4886                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4887                 if (!data)
4888                         return NULL;
4889         }
4890
4891         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4892                                  DMA_FROM_DEVICE);
4893         if (unlikely(dma_mapping_error(d, mapping))) {
4894                 if (net_ratelimit())
4895                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4896                 goto err_out;
4897         }
4898
4899         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4900         return data;
4901
4902 err_out:
4903         kfree(data);
4904         return NULL;
4905 }
4906
4907 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4908 {
4909         unsigned int i;
4910
4911         for (i = 0; i < NUM_RX_DESC; i++) {
4912                 if (tp->Rx_databuff[i]) {
4913                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4914                                             tp->RxDescArray + i);
4915                 }
4916         }
4917 }
4918
4919 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4920 {
4921         desc->opts1 |= cpu_to_le32(RingEnd);
4922 }
4923
4924 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4925 {
4926         unsigned int i;
4927
4928         for (i = 0; i < NUM_RX_DESC; i++) {
4929                 void *data;
4930
4931                 if (tp->Rx_databuff[i])
4932                         continue;
4933
4934                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4935                 if (!data) {
4936                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4937                         goto err_out;
4938                 }
4939                 tp->Rx_databuff[i] = data;
4940         }
4941
4942         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4943         return 0;
4944
4945 err_out:
4946         rtl8169_rx_clear(tp);
4947         return -ENOMEM;
4948 }
4949
4950 static int rtl8169_init_ring(struct net_device *dev)
4951 {
4952         struct rtl8169_private *tp = netdev_priv(dev);
4953
4954         rtl8169_init_ring_indexes(tp);
4955
4956         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4957         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4958
4959         return rtl8169_rx_fill(tp);
4960 }
4961
4962 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4963                                  struct TxDesc *desc)
4964 {
4965         unsigned int len = tx_skb->len;
4966
4967         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4968
4969         desc->opts1 = 0x00;
4970         desc->opts2 = 0x00;
4971         desc->addr = 0x00;
4972         tx_skb->len = 0;
4973 }
4974
4975 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4976                                    unsigned int n)
4977 {
4978         unsigned int i;
4979
4980         for (i = 0; i < n; i++) {
4981                 unsigned int entry = (start + i) % NUM_TX_DESC;
4982                 struct ring_info *tx_skb = tp->tx_skb + entry;
4983                 unsigned int len = tx_skb->len;
4984
4985                 if (len) {
4986                         struct sk_buff *skb = tx_skb->skb;
4987
4988                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4989                                              tp->TxDescArray + entry);
4990                         if (skb) {
4991                                 tp->dev->stats.tx_dropped++;
4992                                 dev_kfree_skb(skb);
4993                                 tx_skb->skb = NULL;
4994                         }
4995                 }
4996         }
4997 }
4998
4999 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5000 {
5001         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5002         tp->cur_tx = tp->dirty_tx = 0;
5003         netdev_reset_queue(tp->dev);
5004 }
5005
5006 static void rtl_reset_work(struct rtl8169_private *tp)
5007 {
5008         struct net_device *dev = tp->dev;
5009         int i;
5010
5011         napi_disable(&tp->napi);
5012         netif_stop_queue(dev);
5013         synchronize_sched();
5014
5015         rtl8169_hw_reset(tp);
5016
5017         for (i = 0; i < NUM_RX_DESC; i++)
5018                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5019
5020         rtl8169_tx_clear(tp);
5021         rtl8169_init_ring_indexes(tp);
5022
5023         napi_enable(&tp->napi);
5024         rtl_hw_start(dev);
5025         netif_wake_queue(dev);
5026         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5027 }
5028
5029 static void rtl8169_tx_timeout(struct net_device *dev)
5030 {
5031         struct rtl8169_private *tp = netdev_priv(dev);
5032
5033         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5034 }
5035
5036 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5037                               u32 *opts)
5038 {
5039         struct skb_shared_info *info = skb_shinfo(skb);
5040         unsigned int cur_frag, entry;
5041         struct TxDesc * uninitialized_var(txd);
5042         struct device *d = &tp->pci_dev->dev;
5043
5044         entry = tp->cur_tx;
5045         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5046                 const skb_frag_t *frag = info->frags + cur_frag;
5047                 dma_addr_t mapping;
5048                 u32 status, len;
5049                 void *addr;
5050
5051                 entry = (entry + 1) % NUM_TX_DESC;
5052
5053                 txd = tp->TxDescArray + entry;
5054                 len = skb_frag_size(frag);
5055                 addr = skb_frag_address(frag);
5056                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5057                 if (unlikely(dma_mapping_error(d, mapping))) {
5058                         if (net_ratelimit())
5059                                 netif_err(tp, drv, tp->dev,
5060                                           "Failed to map TX fragments DMA!\n");
5061                         goto err_out;
5062                 }
5063
5064                 /* Anti gcc 2.95.3 bugware (sic) */
5065                 status = opts[0] | len |
5066                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5067
5068                 txd->opts1 = cpu_to_le32(status);
5069                 txd->opts2 = cpu_to_le32(opts[1]);
5070                 txd->addr = cpu_to_le64(mapping);
5071
5072                 tp->tx_skb[entry].len = len;
5073         }
5074
5075         if (cur_frag) {
5076                 tp->tx_skb[entry].skb = skb;
5077                 txd->opts1 |= cpu_to_le32(LastFrag);
5078         }
5079
5080         return cur_frag;
5081
5082 err_out:
5083         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5084         return -EIO;
5085 }
5086
5087 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5088                                     struct sk_buff *skb, u32 *opts)
5089 {
5090         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5091         u32 mss = skb_shinfo(skb)->gso_size;
5092         int offset = info->opts_offset;
5093
5094         if (mss) {
5095                 opts[0] |= TD_LSO;
5096                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5097         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5098                 const struct iphdr *ip = ip_hdr(skb);
5099
5100                 if (ip->protocol == IPPROTO_TCP)
5101                         opts[offset] |= info->checksum.tcp;
5102                 else if (ip->protocol == IPPROTO_UDP)
5103                         opts[offset] |= info->checksum.udp;
5104                 else
5105                         WARN_ON_ONCE(1);
5106         }
5107 }
5108
5109 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5110                                       struct net_device *dev)
5111 {
5112         struct rtl8169_private *tp = netdev_priv(dev);
5113         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5114         struct TxDesc *txd = tp->TxDescArray + entry;
5115         void __iomem *ioaddr = tp->mmio_addr;
5116         struct device *d = &tp->pci_dev->dev;
5117         dma_addr_t mapping;
5118         u32 status, len;
5119         u32 opts[2];
5120         int frags;
5121
5122         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5123                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5124                 goto err_stop_0;
5125         }
5126
5127         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5128                 goto err_stop_0;
5129
5130         len = skb_headlen(skb);
5131         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5132         if (unlikely(dma_mapping_error(d, mapping))) {
5133                 if (net_ratelimit())
5134                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5135                 goto err_dma_0;
5136         }
5137
5138         tp->tx_skb[entry].len = len;
5139         txd->addr = cpu_to_le64(mapping);
5140
5141         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5142         opts[0] = DescOwn;
5143
5144         rtl8169_tso_csum(tp, skb, opts);
5145
5146         frags = rtl8169_xmit_frags(tp, skb, opts);
5147         if (frags < 0)
5148                 goto err_dma_1;
5149         else if (frags)
5150                 opts[0] |= FirstFrag;
5151         else {
5152                 opts[0] |= FirstFrag | LastFrag;
5153                 tp->tx_skb[entry].skb = skb;
5154         }
5155
5156         txd->opts2 = cpu_to_le32(opts[1]);
5157
5158         netdev_sent_queue(dev, skb->len);
5159
5160         skb_tx_timestamp(skb);
5161
5162         wmb();
5163
5164         /* Anti gcc 2.95.3 bugware (sic) */
5165         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5166         txd->opts1 = cpu_to_le32(status);
5167
5168         tp->cur_tx += frags + 1;
5169
5170         wmb();
5171
5172         RTL_W8(TxPoll, NPQ);
5173
5174         mmiowb();
5175
5176         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5177                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5178                  * not miss a ring update when it notices a stopped queue.
5179                  */
5180                 smp_wmb();
5181                 netif_stop_queue(dev);
5182                 /* Sync with rtl_tx:
5183                  * - publish queue status and cur_tx ring index (write barrier)
5184                  * - refresh dirty_tx ring index (read barrier).
5185                  * May the current thread have a pessimistic view of the ring
5186                  * status and forget to wake up queue, a racing rtl_tx thread
5187                  * can't.
5188                  */
5189                 smp_mb();
5190                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5191                         netif_wake_queue(dev);
5192         }
5193
5194         return NETDEV_TX_OK;
5195
5196 err_dma_1:
5197         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5198 err_dma_0:
5199         dev_kfree_skb(skb);
5200         dev->stats.tx_dropped++;
5201         return NETDEV_TX_OK;
5202
5203 err_stop_0:
5204         netif_stop_queue(dev);
5205         dev->stats.tx_dropped++;
5206         return NETDEV_TX_BUSY;
5207 }
5208
5209 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5210 {
5211         struct rtl8169_private *tp = netdev_priv(dev);
5212         struct pci_dev *pdev = tp->pci_dev;
5213         u16 pci_status, pci_cmd;
5214
5215         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5216         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5217
5218         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5219                   pci_cmd, pci_status);
5220
5221         /*
5222          * The recovery sequence below admits a very elaborated explanation:
5223          * - it seems to work;
5224          * - I did not see what else could be done;
5225          * - it makes iop3xx happy.
5226          *
5227          * Feel free to adjust to your needs.
5228          */
5229         if (pdev->broken_parity_status)
5230                 pci_cmd &= ~PCI_COMMAND_PARITY;
5231         else
5232                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5233
5234         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5235
5236         pci_write_config_word(pdev, PCI_STATUS,
5237                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5238                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5239                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5240
5241         /* The infamous DAC f*ckup only happens at boot time */
5242         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5243                 void __iomem *ioaddr = tp->mmio_addr;
5244
5245                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5246                 tp->cp_cmd &= ~PCIDAC;
5247                 RTL_W16(CPlusCmd, tp->cp_cmd);
5248                 dev->features &= ~NETIF_F_HIGHDMA;
5249         }
5250
5251         rtl8169_hw_reset(tp);
5252
5253         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5254 }
5255
5256 struct rtl_txc {
5257         int packets;
5258         int bytes;
5259 };
5260
5261 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5262 {
5263         struct rtl8169_stats *tx_stats = &tp->tx_stats;
5264         unsigned int dirty_tx, tx_left;
5265         struct rtl_txc txc = { 0, 0 };
5266
5267         dirty_tx = tp->dirty_tx;
5268         smp_rmb();
5269         tx_left = tp->cur_tx - dirty_tx;
5270
5271         while (tx_left > 0) {
5272                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5273                 struct ring_info *tx_skb = tp->tx_skb + entry;
5274                 u32 status;
5275
5276                 rmb();
5277                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5278                 if (status & DescOwn)
5279                         break;
5280
5281                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5282                                      tp->TxDescArray + entry);
5283                 if (status & LastFrag) {
5284                         struct sk_buff *skb = tx_skb->skb;
5285
5286                         txc.packets++;
5287                         txc.bytes += skb->len;
5288                         dev_kfree_skb(skb);
5289                         tx_skb->skb = NULL;
5290                 }
5291                 dirty_tx++;
5292                 tx_left--;
5293         }
5294
5295         u64_stats_update_begin(&tx_stats->syncp);
5296         tx_stats->packets += txc.packets;
5297         tx_stats->bytes += txc.bytes;
5298         u64_stats_update_end(&tx_stats->syncp);
5299
5300         netdev_completed_queue(dev, txc.packets, txc.bytes);
5301
5302         if (tp->dirty_tx != dirty_tx) {
5303                 tp->dirty_tx = dirty_tx;
5304                 /* Sync with rtl8169_start_xmit:
5305                  * - publish dirty_tx ring index (write barrier)
5306                  * - refresh cur_tx ring index and queue status (read barrier)
5307                  * May the current thread miss the stopped queue condition,
5308                  * a racing xmit thread can only have a right view of the
5309                  * ring status.
5310                  */
5311                 smp_mb();
5312                 if (netif_queue_stopped(dev) &&
5313                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5314                         netif_wake_queue(dev);
5315                 }
5316                 /*
5317                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5318                  * too close. Let's kick an extra TxPoll request when a burst
5319                  * of start_xmit activity is detected (if it is not detected,
5320                  * it is slow enough). -- FR
5321                  */
5322                 if (tp->cur_tx != dirty_tx) {
5323                         void __iomem *ioaddr = tp->mmio_addr;
5324
5325                         RTL_W8(TxPoll, NPQ);
5326                 }
5327         }
5328 }
5329
5330 static inline int rtl8169_fragmented_frame(u32 status)
5331 {
5332         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5333 }
5334
5335 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5336 {
5337         u32 status = opts1 & RxProtoMask;
5338
5339         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5340             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5341                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5342         else
5343                 skb_checksum_none_assert(skb);
5344 }
5345
5346 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5347                                            struct rtl8169_private *tp,
5348                                            int pkt_size,
5349                                            dma_addr_t addr)
5350 {
5351         struct sk_buff *skb;
5352         struct device *d = &tp->pci_dev->dev;
5353
5354         data = rtl8169_align(data);
5355         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5356         prefetch(data);
5357         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5358         if (skb)
5359                 memcpy(skb->data, data, pkt_size);
5360         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5361
5362         return skb;
5363 }
5364
5365 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5366 {
5367         unsigned int cur_rx, rx_left;
5368         unsigned int count;
5369
5370         cur_rx = tp->cur_rx;
5371         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5372         rx_left = min(rx_left, budget);
5373
5374         for (; rx_left > 0; rx_left--, cur_rx++) {
5375                 unsigned int entry = cur_rx % NUM_RX_DESC;
5376                 struct RxDesc *desc = tp->RxDescArray + entry;
5377                 u32 status;
5378
5379                 rmb();
5380                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5381
5382                 if (status & DescOwn)
5383                         break;
5384                 if (unlikely(status & RxRES)) {
5385                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5386                                    status);
5387                         dev->stats.rx_errors++;
5388                         if (status & (RxRWT | RxRUNT))
5389                                 dev->stats.rx_length_errors++;
5390                         if (status & RxCRC)
5391                                 dev->stats.rx_crc_errors++;
5392                         if (status & RxFOVF) {
5393                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5394                                 dev->stats.rx_fifo_errors++;
5395                         }
5396                         if ((status & (RxRUNT | RxCRC)) &&
5397                             !(status & (RxRWT | RxFOVF)) &&
5398                             (dev->features & NETIF_F_RXALL))
5399                                 goto process_pkt;
5400
5401                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5402                 } else {
5403                         struct sk_buff *skb;
5404                         dma_addr_t addr;
5405                         int pkt_size;
5406
5407 process_pkt:
5408                         addr = le64_to_cpu(desc->addr);
5409                         if (likely(!(dev->features & NETIF_F_RXFCS)))
5410                                 pkt_size = (status & 0x00003fff) - 4;
5411                         else
5412                                 pkt_size = status & 0x00003fff;
5413
5414                         /*
5415                          * The driver does not support incoming fragmented
5416                          * frames. They are seen as a symptom of over-mtu
5417                          * sized frames.
5418                          */
5419                         if (unlikely(rtl8169_fragmented_frame(status))) {
5420                                 dev->stats.rx_dropped++;
5421                                 dev->stats.rx_length_errors++;
5422                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5423                                 continue;
5424                         }
5425
5426                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5427                                                   tp, pkt_size, addr);
5428                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5429                         if (!skb) {
5430                                 dev->stats.rx_dropped++;
5431                                 continue;
5432                         }
5433
5434                         rtl8169_rx_csum(skb, status);
5435                         skb_put(skb, pkt_size);
5436                         skb->protocol = eth_type_trans(skb, dev);
5437
5438                         rtl8169_rx_vlan_tag(desc, skb);
5439
5440                         napi_gro_receive(&tp->napi, skb);
5441
5442                         u64_stats_update_begin(&tp->rx_stats.syncp);
5443                         tp->rx_stats.packets++;
5444                         tp->rx_stats.bytes += pkt_size;
5445                         u64_stats_update_end(&tp->rx_stats.syncp);
5446                 }
5447
5448                 /* Work around for AMD plateform. */
5449                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5450                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5451                         desc->opts2 = 0;
5452                         cur_rx++;
5453                 }
5454         }
5455
5456         count = cur_rx - tp->cur_rx;
5457         tp->cur_rx = cur_rx;
5458
5459         tp->dirty_rx += count;
5460
5461         return count;
5462 }
5463
5464 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5465 {
5466         struct net_device *dev = dev_instance;
5467         struct rtl8169_private *tp = netdev_priv(dev);
5468         int handled = 0;
5469         u16 status;
5470
5471         status = rtl_get_events(tp);
5472         if (status && status != 0xffff) {
5473                 status &= RTL_EVENT_NAPI | tp->event_slow;
5474                 if (status) {
5475                         handled = 1;
5476
5477                         rtl_irq_disable(tp);
5478                         napi_schedule(&tp->napi);
5479                 }
5480         }
5481         return IRQ_RETVAL(handled);
5482 }
5483
5484 /*
5485  * Workqueue context.
5486  */
5487 static void rtl_slow_event_work(struct rtl8169_private *tp)
5488 {
5489         struct net_device *dev = tp->dev;
5490         u16 status;
5491
5492         status = rtl_get_events(tp) & tp->event_slow;
5493         rtl_ack_events(tp, status);
5494
5495         if (unlikely(status & RxFIFOOver)) {
5496                 switch (tp->mac_version) {
5497                 /* Work around for rx fifo overflow */
5498                 case RTL_GIGA_MAC_VER_11:
5499                         netif_stop_queue(dev);
5500                         /* XXX - Hack alert. See rtl_task(). */
5501                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5502                 default:
5503                         break;
5504                 }
5505         }
5506
5507         if (unlikely(status & SYSErr))
5508                 rtl8169_pcierr_interrupt(dev);
5509
5510         if (status & LinkChg)
5511                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5512
5513         napi_disable(&tp->napi);
5514         rtl_irq_disable(tp);
5515
5516         napi_enable(&tp->napi);
5517         napi_schedule(&tp->napi);
5518 }
5519
5520 static void rtl_task(struct work_struct *work)
5521 {
5522         static const struct {
5523                 int bitnr;
5524                 void (*action)(struct rtl8169_private *);
5525         } rtl_work[] = {
5526                 /* XXX - keep rtl_slow_event_work() as first element. */
5527                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
5528                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
5529                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
5530         };
5531         struct rtl8169_private *tp =
5532                 container_of(work, struct rtl8169_private, wk.work);
5533         struct net_device *dev = tp->dev;
5534         int i;
5535
5536         rtl_lock_work(tp);
5537
5538         if (!netif_running(dev) ||
5539             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5540                 goto out_unlock;
5541
5542         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5543                 bool pending;
5544
5545                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5546                 if (pending)
5547                         rtl_work[i].action(tp);
5548         }
5549
5550 out_unlock:
5551         rtl_unlock_work(tp);
5552 }
5553
5554 static int rtl8169_poll(struct napi_struct *napi, int budget)
5555 {
5556         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5557         struct net_device *dev = tp->dev;
5558         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5559         int work_done= 0;
5560         u16 status;
5561
5562         status = rtl_get_events(tp);
5563         rtl_ack_events(tp, status & ~tp->event_slow);
5564
5565         if (status & RTL_EVENT_NAPI_RX)
5566                 work_done = rtl_rx(dev, tp, (u32) budget);
5567
5568         if (status & RTL_EVENT_NAPI_TX)
5569                 rtl_tx(dev, tp);
5570
5571         if (status & tp->event_slow) {
5572                 enable_mask &= ~tp->event_slow;
5573
5574                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5575         }
5576
5577         if (work_done < budget) {
5578                 napi_complete(napi);
5579
5580                 rtl_irq_enable(tp, enable_mask);
5581                 mmiowb();
5582         }
5583
5584         return work_done;
5585 }
5586
5587 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5588 {
5589         struct rtl8169_private *tp = netdev_priv(dev);
5590
5591         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5592                 return;
5593
5594         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5595         RTL_W32(RxMissed, 0);
5596 }
5597
5598 static void rtl8169_down(struct net_device *dev)
5599 {
5600         struct rtl8169_private *tp = netdev_priv(dev);
5601         void __iomem *ioaddr = tp->mmio_addr;
5602
5603         del_timer_sync(&tp->timer);
5604
5605         napi_disable(&tp->napi);
5606         netif_stop_queue(dev);
5607
5608         rtl8169_hw_reset(tp);
5609         /*
5610          * At this point device interrupts can not be enabled in any function,
5611          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5612          * and napi is disabled (rtl8169_poll).
5613          */
5614         rtl8169_rx_missed(dev, ioaddr);
5615
5616         /* Give a racing hard_start_xmit a few cycles to complete. */
5617         synchronize_sched();
5618
5619         rtl8169_tx_clear(tp);
5620
5621         rtl8169_rx_clear(tp);
5622
5623         rtl_pll_power_down(tp);
5624 }
5625
5626 static int rtl8169_close(struct net_device *dev)
5627 {
5628         struct rtl8169_private *tp = netdev_priv(dev);
5629         struct pci_dev *pdev = tp->pci_dev;
5630
5631         pm_runtime_get_sync(&pdev->dev);
5632
5633         /* Update counters before going down */
5634         rtl8169_update_counters(dev);
5635
5636         rtl_lock_work(tp);
5637         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5638
5639         rtl8169_down(dev);
5640         rtl_unlock_work(tp);
5641
5642         free_irq(pdev->irq, dev);
5643
5644         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5645                           tp->RxPhyAddr);
5646         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5647                           tp->TxPhyAddr);
5648         tp->TxDescArray = NULL;
5649         tp->RxDescArray = NULL;
5650
5651         pm_runtime_put_sync(&pdev->dev);
5652
5653         return 0;
5654 }
5655
5656 #ifdef CONFIG_NET_POLL_CONTROLLER
5657 static void rtl8169_netpoll(struct net_device *dev)
5658 {
5659         struct rtl8169_private *tp = netdev_priv(dev);
5660
5661         rtl8169_interrupt(tp->pci_dev->irq, dev);
5662 }
5663 #endif
5664
5665 static int rtl_open(struct net_device *dev)
5666 {
5667         struct rtl8169_private *tp = netdev_priv(dev);
5668         void __iomem *ioaddr = tp->mmio_addr;
5669         struct pci_dev *pdev = tp->pci_dev;
5670         int retval = -ENOMEM;
5671
5672         pm_runtime_get_sync(&pdev->dev);
5673
5674         /*
5675          * Rx and Tx desscriptors needs 256 bytes alignment.
5676          * dma_alloc_coherent provides more.
5677          */
5678         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
5679                                              &tp->TxPhyAddr, GFP_KERNEL);
5680         if (!tp->TxDescArray)
5681                 goto err_pm_runtime_put;
5682
5683         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
5684                                              &tp->RxPhyAddr, GFP_KERNEL);
5685         if (!tp->RxDescArray)
5686                 goto err_free_tx_0;
5687
5688         retval = rtl8169_init_ring(dev);
5689         if (retval < 0)
5690                 goto err_free_rx_1;
5691
5692         INIT_WORK(&tp->wk.work, rtl_task);
5693
5694         smp_mb();
5695
5696         rtl_request_firmware(tp);
5697
5698         retval = request_irq(pdev->irq, rtl8169_interrupt,
5699                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
5700                              dev->name, dev);
5701         if (retval < 0)
5702                 goto err_release_fw_2;
5703
5704         rtl_lock_work(tp);
5705
5706         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5707
5708         napi_enable(&tp->napi);
5709
5710         rtl8169_init_phy(dev, tp);
5711
5712         __rtl8169_set_features(dev, dev->features);
5713
5714         rtl_pll_power_up(tp);
5715
5716         rtl_hw_start(dev);
5717
5718         netif_start_queue(dev);
5719
5720         rtl_unlock_work(tp);
5721
5722         tp->saved_wolopts = 0;
5723         pm_runtime_put_noidle(&pdev->dev);
5724
5725         rtl8169_check_link_status(dev, tp, ioaddr);
5726 out:
5727         return retval;
5728
5729 err_release_fw_2:
5730         rtl_release_firmware(tp);
5731         rtl8169_rx_clear(tp);
5732 err_free_rx_1:
5733         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5734                           tp->RxPhyAddr);
5735         tp->RxDescArray = NULL;
5736 err_free_tx_0:
5737         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5738                           tp->TxPhyAddr);
5739         tp->TxDescArray = NULL;
5740 err_pm_runtime_put:
5741         pm_runtime_put_noidle(&pdev->dev);
5742         goto out;
5743 }
5744
5745 static struct rtnl_link_stats64 *
5746 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5747 {
5748         struct rtl8169_private *tp = netdev_priv(dev);
5749         void __iomem *ioaddr = tp->mmio_addr;
5750         unsigned int start;
5751
5752         if (netif_running(dev))
5753                 rtl8169_rx_missed(dev, ioaddr);
5754
5755         do {
5756                 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
5757                 stats->rx_packets = tp->rx_stats.packets;
5758                 stats->rx_bytes = tp->rx_stats.bytes;
5759         } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
5760
5761
5762         do {
5763                 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
5764                 stats->tx_packets = tp->tx_stats.packets;
5765                 stats->tx_bytes = tp->tx_stats.bytes;
5766         } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
5767
5768         stats->rx_dropped       = dev->stats.rx_dropped;
5769         stats->tx_dropped       = dev->stats.tx_dropped;
5770         stats->rx_length_errors = dev->stats.rx_length_errors;
5771         stats->rx_errors        = dev->stats.rx_errors;
5772         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
5773         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
5774         stats->rx_missed_errors = dev->stats.rx_missed_errors;
5775
5776         return stats;
5777 }
5778
5779 static void rtl8169_net_suspend(struct net_device *dev)
5780 {
5781         struct rtl8169_private *tp = netdev_priv(dev);
5782
5783         if (!netif_running(dev))
5784                 return;
5785
5786         netif_device_detach(dev);
5787         netif_stop_queue(dev);
5788
5789         rtl_lock_work(tp);
5790         napi_disable(&tp->napi);
5791         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5792         rtl_unlock_work(tp);
5793
5794         rtl_pll_power_down(tp);
5795 }
5796
5797 #ifdef CONFIG_PM
5798
5799 static int rtl8169_suspend(struct device *device)
5800 {
5801         struct pci_dev *pdev = to_pci_dev(device);
5802         struct net_device *dev = pci_get_drvdata(pdev);
5803
5804         rtl8169_net_suspend(dev);
5805
5806         return 0;
5807 }
5808
5809 static void __rtl8169_resume(struct net_device *dev)
5810 {
5811         struct rtl8169_private *tp = netdev_priv(dev);
5812
5813         netif_device_attach(dev);
5814
5815         rtl_pll_power_up(tp);
5816
5817         rtl_lock_work(tp);
5818         napi_enable(&tp->napi);
5819         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5820         rtl_unlock_work(tp);
5821
5822         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5823 }
5824
5825 static int rtl8169_resume(struct device *device)
5826 {
5827         struct pci_dev *pdev = to_pci_dev(device);
5828         struct net_device *dev = pci_get_drvdata(pdev);
5829         struct rtl8169_private *tp = netdev_priv(dev);
5830
5831         rtl8169_init_phy(dev, tp);
5832
5833         if (netif_running(dev))
5834                 __rtl8169_resume(dev);
5835
5836         return 0;
5837 }
5838
5839 static int rtl8169_runtime_suspend(struct device *device)
5840 {
5841         struct pci_dev *pdev = to_pci_dev(device);
5842         struct net_device *dev = pci_get_drvdata(pdev);
5843         struct rtl8169_private *tp = netdev_priv(dev);
5844
5845         if (!tp->TxDescArray)
5846                 return 0;
5847
5848         rtl_lock_work(tp);
5849         tp->saved_wolopts = __rtl8169_get_wol(tp);
5850         __rtl8169_set_wol(tp, WAKE_ANY);
5851         rtl_unlock_work(tp);
5852
5853         rtl8169_net_suspend(dev);
5854
5855         return 0;
5856 }
5857
5858 static int rtl8169_runtime_resume(struct device *device)
5859 {
5860         struct pci_dev *pdev = to_pci_dev(device);
5861         struct net_device *dev = pci_get_drvdata(pdev);
5862         struct rtl8169_private *tp = netdev_priv(dev);
5863
5864         if (!tp->TxDescArray)
5865                 return 0;
5866
5867         rtl_lock_work(tp);
5868         __rtl8169_set_wol(tp, tp->saved_wolopts);
5869         tp->saved_wolopts = 0;
5870         rtl_unlock_work(tp);
5871
5872         rtl8169_init_phy(dev, tp);
5873
5874         __rtl8169_resume(dev);
5875
5876         return 0;
5877 }
5878
5879 static int rtl8169_runtime_idle(struct device *device)
5880 {
5881         struct pci_dev *pdev = to_pci_dev(device);
5882         struct net_device *dev = pci_get_drvdata(pdev);
5883         struct rtl8169_private *tp = netdev_priv(dev);
5884
5885         return tp->TxDescArray ? -EBUSY : 0;
5886 }
5887
5888 static const struct dev_pm_ops rtl8169_pm_ops = {
5889         .suspend                = rtl8169_suspend,
5890         .resume                 = rtl8169_resume,
5891         .freeze                 = rtl8169_suspend,
5892         .thaw                   = rtl8169_resume,
5893         .poweroff               = rtl8169_suspend,
5894         .restore                = rtl8169_resume,
5895         .runtime_suspend        = rtl8169_runtime_suspend,
5896         .runtime_resume         = rtl8169_runtime_resume,
5897         .runtime_idle           = rtl8169_runtime_idle,
5898 };
5899
5900 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5901
5902 #else /* !CONFIG_PM */
5903
5904 #define RTL8169_PM_OPS  NULL
5905
5906 #endif /* !CONFIG_PM */
5907
5908 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5909 {
5910         void __iomem *ioaddr = tp->mmio_addr;
5911
5912         /* WoL fails with 8168b when the receiver is disabled. */
5913         switch (tp->mac_version) {
5914         case RTL_GIGA_MAC_VER_11:
5915         case RTL_GIGA_MAC_VER_12:
5916         case RTL_GIGA_MAC_VER_17:
5917                 pci_clear_master(tp->pci_dev);
5918
5919                 RTL_W8(ChipCmd, CmdRxEnb);
5920                 /* PCI commit */
5921                 RTL_R8(ChipCmd);
5922                 break;
5923         default:
5924                 break;
5925         }
5926 }
5927
5928 static void rtl_shutdown(struct pci_dev *pdev)
5929 {
5930         struct net_device *dev = pci_get_drvdata(pdev);
5931         struct rtl8169_private *tp = netdev_priv(dev);
5932         struct device *d = &pdev->dev;
5933
5934         pm_runtime_get_sync(d);
5935
5936         rtl8169_net_suspend(dev);
5937
5938         /* Restore original MAC address */
5939         rtl_rar_set(tp, dev->perm_addr);
5940
5941         rtl8169_hw_reset(tp);
5942
5943         if (system_state == SYSTEM_POWER_OFF) {
5944                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
5945                         rtl_wol_suspend_quirk(tp);
5946                         rtl_wol_shutdown_quirk(tp);
5947                 }
5948
5949                 pci_wake_from_d3(pdev, true);
5950                 pci_set_power_state(pdev, PCI_D3hot);
5951         }
5952
5953         pm_runtime_put_noidle(d);
5954 }
5955
5956 static void __devexit rtl_remove_one(struct pci_dev *pdev)
5957 {
5958         struct net_device *dev = pci_get_drvdata(pdev);
5959         struct rtl8169_private *tp = netdev_priv(dev);
5960
5961         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5962             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5963             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5964                 rtl8168_driver_stop(tp);
5965         }
5966
5967         cancel_work_sync(&tp->wk.work);
5968
5969         unregister_netdev(dev);
5970
5971         rtl_release_firmware(tp);
5972
5973         if (pci_dev_run_wake(pdev))
5974                 pm_runtime_get_noresume(&pdev->dev);
5975
5976         /* restore original MAC address */
5977         rtl_rar_set(tp, dev->perm_addr);
5978
5979         rtl_disable_msi(pdev, tp);
5980         rtl8169_release_board(pdev, dev, tp->mmio_addr);
5981         pci_set_drvdata(pdev, NULL);
5982 }
5983
5984 static const struct net_device_ops rtl_netdev_ops = {
5985         .ndo_open               = rtl_open,
5986         .ndo_stop               = rtl8169_close,
5987         .ndo_get_stats64        = rtl8169_get_stats64,
5988         .ndo_start_xmit         = rtl8169_start_xmit,
5989         .ndo_tx_timeout         = rtl8169_tx_timeout,
5990         .ndo_validate_addr      = eth_validate_addr,
5991         .ndo_change_mtu         = rtl8169_change_mtu,
5992         .ndo_fix_features       = rtl8169_fix_features,
5993         .ndo_set_features       = rtl8169_set_features,
5994         .ndo_set_mac_address    = rtl_set_mac_address,
5995         .ndo_do_ioctl           = rtl8169_ioctl,
5996         .ndo_set_rx_mode        = rtl_set_rx_mode,
5997 #ifdef CONFIG_NET_POLL_CONTROLLER
5998         .ndo_poll_controller    = rtl8169_netpoll,
5999 #endif
6000
6001 };
6002
6003 static const struct rtl_cfg_info {
6004         void (*hw_start)(struct net_device *);
6005         unsigned int region;
6006         unsigned int align;
6007         u16 event_slow;
6008         unsigned features;
6009         u8 default_ver;
6010 } rtl_cfg_infos [] = {
6011         [RTL_CFG_0] = {
6012                 .hw_start       = rtl_hw_start_8169,
6013                 .region         = 1,
6014                 .align          = 0,
6015                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6016                 .features       = RTL_FEATURE_GMII,
6017                 .default_ver    = RTL_GIGA_MAC_VER_01,
6018         },
6019         [RTL_CFG_1] = {
6020                 .hw_start       = rtl_hw_start_8168,
6021                 .region         = 2,
6022                 .align          = 8,
6023                 .event_slow     = SYSErr | LinkChg | RxOverflow,
6024                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6025                 .default_ver    = RTL_GIGA_MAC_VER_11,
6026         },
6027         [RTL_CFG_2] = {
6028                 .hw_start       = rtl_hw_start_8101,
6029                 .region         = 2,
6030                 .align          = 8,
6031                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6032                                   PCSTimeout,
6033                 .features       = RTL_FEATURE_MSI,
6034                 .default_ver    = RTL_GIGA_MAC_VER_13,
6035         }
6036 };
6037
6038 /* Cfg9346_Unlock assumed. */
6039 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6040                             const struct rtl_cfg_info *cfg)
6041 {
6042         void __iomem *ioaddr = tp->mmio_addr;
6043         unsigned msi = 0;
6044         u8 cfg2;
6045
6046         cfg2 = RTL_R8(Config2) & ~MSIEnable;
6047         if (cfg->features & RTL_FEATURE_MSI) {
6048                 if (pci_enable_msi(tp->pci_dev)) {
6049                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6050                 } else {
6051                         cfg2 |= MSIEnable;
6052                         msi = RTL_FEATURE_MSI;
6053                 }
6054         }
6055         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6056                 RTL_W8(Config2, cfg2);
6057         return msi;
6058 }
6059
6060 static int __devinit
6061 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6062 {
6063         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6064         const unsigned int region = cfg->region;
6065         struct rtl8169_private *tp;
6066         struct mii_if_info *mii;
6067         struct net_device *dev;
6068         void __iomem *ioaddr;
6069         int chipset, i;
6070         int rc;
6071
6072         if (netif_msg_drv(&debug)) {
6073                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6074                        MODULENAME, RTL8169_VERSION);
6075         }
6076
6077         dev = alloc_etherdev(sizeof (*tp));
6078         if (!dev) {
6079                 rc = -ENOMEM;
6080                 goto out;
6081         }
6082
6083         SET_NETDEV_DEV(dev, &pdev->dev);
6084         dev->netdev_ops = &rtl_netdev_ops;
6085         tp = netdev_priv(dev);
6086         tp->dev = dev;
6087         tp->pci_dev = pdev;
6088         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6089
6090         mii = &tp->mii;
6091         mii->dev = dev;
6092         mii->mdio_read = rtl_mdio_read;
6093         mii->mdio_write = rtl_mdio_write;
6094         mii->phy_id_mask = 0x1f;
6095         mii->reg_num_mask = 0x1f;
6096         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6097
6098         /* disable ASPM completely as that cause random device stop working
6099          * problems as well as full system hangs for some PCIe devices users */
6100         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6101                                      PCIE_LINK_STATE_CLKPM);
6102
6103         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6104         rc = pci_enable_device(pdev);
6105         if (rc < 0) {
6106                 netif_err(tp, probe, dev, "enable failure\n");
6107                 goto err_out_free_dev_1;
6108         }
6109
6110         if (pci_set_mwi(pdev) < 0)
6111                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6112
6113         /* make sure PCI base addr 1 is MMIO */
6114         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6115                 netif_err(tp, probe, dev,
6116                           "region #%d not an MMIO resource, aborting\n",
6117                           region);
6118                 rc = -ENODEV;
6119                 goto err_out_mwi_2;
6120         }
6121
6122         /* check for weird/broken PCI region reporting */
6123         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6124                 netif_err(tp, probe, dev,
6125                           "Invalid PCI region size(s), aborting\n");
6126                 rc = -ENODEV;
6127                 goto err_out_mwi_2;
6128         }
6129
6130         rc = pci_request_regions(pdev, MODULENAME);
6131         if (rc < 0) {
6132                 netif_err(tp, probe, dev, "could not request regions\n");
6133                 goto err_out_mwi_2;
6134         }
6135
6136         tp->cp_cmd = RxChkSum;
6137
6138         if ((sizeof(dma_addr_t) > 4) &&
6139             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6140                 tp->cp_cmd |= PCIDAC;
6141                 dev->features |= NETIF_F_HIGHDMA;
6142         } else {
6143                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6144                 if (rc < 0) {
6145                         netif_err(tp, probe, dev, "DMA configuration failed\n");
6146                         goto err_out_free_res_3;
6147                 }
6148         }
6149
6150         /* ioremap MMIO region */
6151         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6152         if (!ioaddr) {
6153                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6154                 rc = -EIO;
6155                 goto err_out_free_res_3;
6156         }
6157         tp->mmio_addr = ioaddr;
6158
6159         if (!pci_is_pcie(pdev))
6160                 netif_info(tp, probe, dev, "not PCI Express\n");
6161
6162         /* Identify chip attached to board */
6163         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6164
6165         rtl_init_rxcfg(tp);
6166
6167         rtl_irq_disable(tp);
6168
6169         rtl_hw_reset(tp);
6170
6171         rtl_ack_events(tp, 0xffff);
6172
6173         pci_set_master(pdev);
6174
6175         /*
6176          * Pretend we are using VLANs; This bypasses a nasty bug where
6177          * Interrupts stop flowing on high load on 8110SCd controllers.
6178          */
6179         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6180                 tp->cp_cmd |= RxVlan;
6181
6182         rtl_init_mdio_ops(tp);
6183         rtl_init_pll_power_ops(tp);
6184         rtl_init_jumbo_ops(tp);
6185
6186         rtl8169_print_mac_version(tp);
6187
6188         chipset = tp->mac_version;
6189         tp->txd_version = rtl_chip_infos[chipset].txd_version;
6190
6191         RTL_W8(Cfg9346, Cfg9346_Unlock);
6192         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6193         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6194         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6195                 tp->features |= RTL_FEATURE_WOL;
6196         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6197                 tp->features |= RTL_FEATURE_WOL;
6198         tp->features |= rtl_try_msi(tp, cfg);
6199         RTL_W8(Cfg9346, Cfg9346_Lock);
6200
6201         if (rtl_tbi_enabled(tp)) {
6202                 tp->set_speed = rtl8169_set_speed_tbi;
6203                 tp->get_settings = rtl8169_gset_tbi;
6204                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6205                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6206                 tp->link_ok = rtl8169_tbi_link_ok;
6207                 tp->do_ioctl = rtl_tbi_ioctl;
6208         } else {
6209                 tp->set_speed = rtl8169_set_speed_xmii;
6210                 tp->get_settings = rtl8169_gset_xmii;
6211                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6212                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6213                 tp->link_ok = rtl8169_xmii_link_ok;
6214                 tp->do_ioctl = rtl_xmii_ioctl;
6215         }
6216
6217         mutex_init(&tp->wk.mutex);
6218
6219         /* Get MAC address */
6220         for (i = 0; i < ETH_ALEN; i++)
6221                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6222         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6223
6224         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6225         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6226
6227         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6228
6229         /* don't enable SG, IP_CSUM and TSO by default - it might not work
6230          * properly for all devices */
6231         dev->features |= NETIF_F_RXCSUM |
6232                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6233
6234         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6235                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6236         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6237                 NETIF_F_HIGHDMA;
6238
6239         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6240                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6241                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6242
6243         dev->hw_features |= NETIF_F_RXALL;
6244         dev->hw_features |= NETIF_F_RXFCS;
6245
6246         tp->hw_start = cfg->hw_start;
6247         tp->event_slow = cfg->event_slow;
6248
6249         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6250                 ~(RxBOVF | RxFOVF) : ~0;
6251
6252         init_timer(&tp->timer);
6253         tp->timer.data = (unsigned long) dev;
6254         tp->timer.function = rtl8169_phy_timer;
6255
6256         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6257
6258         rc = register_netdev(dev);
6259         if (rc < 0)
6260                 goto err_out_msi_4;
6261
6262         pci_set_drvdata(pdev, dev);
6263
6264         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6265                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6266                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
6267         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6268                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6269                            "tx checksumming: %s]\n",
6270                            rtl_chip_infos[chipset].jumbo_max,
6271                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6272         }
6273
6274         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6275             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6276             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6277                 rtl8168_driver_start(tp);
6278         }
6279
6280         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6281
6282         if (pci_dev_run_wake(pdev))
6283                 pm_runtime_put_noidle(&pdev->dev);
6284
6285         netif_carrier_off(dev);
6286
6287 out:
6288         return rc;
6289
6290 err_out_msi_4:
6291         rtl_disable_msi(pdev, tp);
6292         iounmap(ioaddr);
6293 err_out_free_res_3:
6294         pci_release_regions(pdev);
6295 err_out_mwi_2:
6296         pci_clear_mwi(pdev);
6297         pci_disable_device(pdev);
6298 err_out_free_dev_1:
6299         free_netdev(dev);
6300         goto out;
6301 }
6302
6303 static struct pci_driver rtl8169_pci_driver = {
6304         .name           = MODULENAME,
6305         .id_table       = rtl8169_pci_tbl,
6306         .probe          = rtl_init_one,
6307         .remove         = __devexit_p(rtl_remove_one),
6308         .shutdown       = rtl_shutdown,
6309         .driver.pm      = RTL8169_PM_OPS,
6310 };
6311
6312 static int __init rtl8169_init_module(void)
6313 {
6314         return pci_register_driver(&rtl8169_pci_driver);
6315 }
6316
6317 static void __exit rtl8169_cleanup_module(void)
6318 {
6319         pci_unregister_driver(&rtl8169_pci_driver);
6320 }
6321
6322 module_init(rtl8169_init_module);
6323 module_exit(rtl8169_cleanup_module);