2 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
4 * kernel entry points (interruptions, system call wrappers)
5 * Copyright (C) 1999,2000 Philipp Rumpf
6 * Copyright (C) 1999 SuSE GmbH Nuernberg
7 * Copyright (C) 2000 Hewlett-Packard (John Marvin)
8 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <asm/asm-offsets.h>
27 /* we have the following possibilities to act on an interruption:
28 * - handle in assembly and use shadowed registers only
29 * - save registers to kernel stack and handle in assembly or C */
33 #include <asm/cache.h> /* for L1_CACHE_SHIFT */
34 #include <asm/assembly.h> /* for LDREG/STREG defines */
35 #include <asm/pgtable.h>
36 #include <asm/signal.h>
37 #include <asm/unistd.h>
38 #include <asm/thread_info.h>
54 .import pa_dbit_lock,data
56 /* space_to_prot macro creates a prot id from a space id */
58 #if (SPACEID_SHIFT) == 0
59 .macro space_to_prot spc prot
60 depd,z \spc,62,31,\prot
63 .macro space_to_prot spc prot
64 extrd,u \spc,(64 - (SPACEID_SHIFT)),32,\prot
68 /* Switch to virtual mapping, trashing only %r1 */
71 rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */
75 or,= %r0,%r1,%r0 /* Only save sr7 in sr3 if sr7 != 0 */
78 load32 KERNEL_PSW, %r1
80 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */
83 mtctl %r0, %cr17 /* Clear IIASQ tail */
84 mtctl %r0, %cr17 /* Clear IIASQ head */
87 mtctl %r1, %cr18 /* Set IIAOQ tail */
89 mtctl %r1, %cr18 /* Set IIAOQ head */
96 * The "get_stack" macros are responsible for determining the
101 * Already using a kernel stack, so call the
102 * get_stack_use_r30 macro to push a pt_regs structure
103 * on the stack, and store registers there.
105 * Need to set up a kernel stack, so call the
106 * get_stack_use_cr30 macro to set up a pointer
107 * to the pt_regs structure contained within the
108 * task pointer pointed to by cr30. Set the stack
109 * pointer to point to the end of the task structure.
113 * Already using a kernel stack, check to see if r30
114 * is already pointing to the per processor interrupt
115 * stack. If it is, call the get_stack_use_r30 macro
116 * to push a pt_regs structure on the stack, and store
117 * registers there. Otherwise, call get_stack_use_cr31
118 * to get a pointer to the base of the interrupt stack
119 * and push a pt_regs structure on that stack.
121 * Need to set up a kernel stack, so call the
122 * get_stack_use_cr30 macro to set up a pointer
123 * to the pt_regs structure contained within the
124 * task pointer pointed to by cr30. Set the stack
125 * pointer to point to the end of the task structure.
126 * N.B: We don't use the interrupt stack for the
127 * first interrupt from userland, because signals/
128 * resched's are processed when returning to userland,
129 * and we can sleep in those cases.
131 * Note that we use shadowed registers for temps until
132 * we can save %r26 and %r29. %r26 is used to preserve
133 * %r8 (a shadowed register) which temporarily contained
134 * either the fault type ("code") or the eirr. We need
135 * to use a non-shadowed register to carry the value over
136 * the rfir in virt_map. We use %r26 since this value winds
137 * up being passed as the argument to either do_cpu_irq_mask
138 * or handle_interruption. %r29 is used to hold a pointer
139 * the register save area, and once again, it needs to
140 * be a non-shadowed register so that it survives the rfir.
142 * N.B. TASK_SZ_ALGN and PT_SZ_ALGN include space for a stack frame.
145 .macro get_stack_use_cr30
147 /* we save the registers in the task struct */
151 LDREG TI_TASK(%r9), %r1 /* thread_info -> task_struct */
153 ldo TASK_REGS(%r9),%r9
154 STREG %r30, PT_GR30(%r9)
155 STREG %r29,PT_GR29(%r9)
156 STREG %r26,PT_GR26(%r9)
159 ldo THREAD_SZ_ALGN(%r1), %r30
162 .macro get_stack_use_r30
164 /* we put a struct pt_regs on the stack and save the registers there */
167 STREG %r30,PT_GR30(%r9)
168 ldo PT_SZ_ALGN(%r30),%r30
169 STREG %r29,PT_GR29(%r9)
170 STREG %r26,PT_GR26(%r9)
175 LDREG PT_GR1(%r29), %r1
176 LDREG PT_GR30(%r29),%r30
177 LDREG PT_GR29(%r29),%r29
180 /* default interruption handler
181 * (calls traps.c:handle_interruption) */
188 /* Interrupt interruption handler
189 * (calls irq.c:do_cpu_irq_mask) */
196 .import os_hpmc, code
200 nop /* must be a NOP, will be patched later */
201 load32 PA(os_hpmc), %r3
204 .word 0 /* checksum (will be patched) */
205 .word PA(os_hpmc) /* address of handler */
206 .word 0 /* length of handler */
210 * Performance Note: Instructions will be moved up into
211 * this part of the code later on, once we are sure
212 * that the tlb miss handlers are close to final form.
215 /* Register definitions for tlb miss handler macros */
217 va = r8 /* virtual address for which the trap occured */
218 spc = r24 /* space for which the trap occured */
223 * itlb miss interruption handler (parisc 1.1 - 32 bit)
237 * itlb miss interruption handler (parisc 2.0)
254 * naitlb miss interruption handler (parisc 1.1 - 32 bit)
256 * Note: naitlb misses will be treated
257 * as an ordinary itlb miss for now.
258 * However, note that naitlb misses
259 * have the faulting address in the
263 .macro naitlb_11 code
268 /* FIXME: If user causes a naitlb miss, the priv level may not be in
269 * lower bits of va, where the itlb miss handler is expecting them
277 * naitlb miss interruption handler (parisc 2.0)
279 * Note: naitlb misses will be treated
280 * as an ordinary itlb miss for now.
281 * However, note that naitlb misses
282 * have the faulting address in the
286 .macro naitlb_20 code
295 /* FIXME: If user causes a naitlb miss, the priv level may not be in
296 * lower bits of va, where the itlb miss handler is expecting them
304 * dtlb miss interruption handler (parisc 1.1 - 32 bit)
318 * dtlb miss interruption handler (parisc 2.0)
335 /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
337 .macro nadtlb_11 code
347 /* nadtlb miss interruption handler (parisc 2.0) */
349 .macro nadtlb_20 code
364 * dirty bit trap interruption handler (parisc 1.1 - 32 bit)
378 * dirty bit trap interruption handler (parisc 2.0)
394 /* The following are simple 32 vs 64 bit instruction
395 * abstractions for the macros */
396 .macro EXTR reg1,start,length,reg2
398 extrd,u \reg1,32+\start,\length,\reg2
400 extrw,u \reg1,\start,\length,\reg2
404 .macro DEP reg1,start,length,reg2
406 depd \reg1,32+\start,\length,\reg2
408 depw \reg1,\start,\length,\reg2
412 .macro DEPI val,start,length,reg
414 depdi \val,32+\start,\length,\reg
416 depwi \val,\start,\length,\reg
420 /* In LP64, the space contains part of the upper 32 bits of the
421 * fault. We have to extract this and place it in the va,
422 * zeroing the corresponding bits in the space register */
423 .macro space_adjust spc,va,tmp
425 extrd,u \spc,63,SPACEID_SHIFT,\tmp
426 depd %r0,63,SPACEID_SHIFT,\spc
427 depd \tmp,31,SPACEID_SHIFT,\va
431 .import swapper_pg_dir,code
433 /* Get the pgd. For faults on space zero (kernel space), this
434 * is simply swapper_pg_dir. For user space faults, the
435 * pgd is stored in %cr25 */
436 .macro get_pgd spc,reg
437 ldil L%PA(swapper_pg_dir),\reg
438 ldo R%PA(swapper_pg_dir)(\reg),\reg
439 or,COND(=) %r0,\spc,%r0
444 space_check(spc,tmp,fault)
446 spc - The space we saw the fault with.
447 tmp - The place to store the current space.
448 fault - Function to call on failure.
450 Only allow faults on different spaces from the
451 currently active one if we're the kernel
454 .macro space_check spc,tmp,fault
456 or,COND(<>) %r0,\spc,%r0 /* user may execute gateway page
457 * as kernel, so defeat the space
460 or,COND(=) %r0,\tmp,%r0 /* nullify if executing as kernel */
461 cmpb,COND(<>),n \tmp,\spc,\fault
464 /* Look up a PTE in a 2-Level scheme (faulting at each
465 * level if the entry isn't present
467 * NOTE: we use ldw even for LP64, since the short pointers
468 * can address up to 1TB
470 .macro L2_ptep pmd,pte,index,va,fault
472 EXTR \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
474 EXTR \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
476 DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */
478 ldw,s \index(\pmd),\pmd
479 bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault
480 DEP %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
482 SHLREG %r9,PxD_VALUE_SHIFT,\pmd
483 EXTR \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
484 DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */
485 shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd
486 LDREG %r0(\pmd),\pte /* pmd is now pte */
487 bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault
490 /* Look up PTE in a 3-Level scheme.
492 * Here we implement a Hybrid L2/L3 scheme: we allocate the
493 * first pmd adjacent to the pgd. This means that we can
494 * subtract a constant offset to get to it. The pmd and pgd
495 * sizes are arranged so that a single pmd covers 4GB (giving
496 * a full LP64 process access to 8TB) so our lookups are
497 * effectively L2 for the first 4GB of the kernel (i.e. for
498 * all ILP32 processes and all the kernel for machines with
499 * under 4GB of memory) */
500 .macro L3_ptep pgd,pte,index,va,fault
501 #if PT_NLEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */
502 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
504 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
505 ldw,s \index(\pgd),\pgd
506 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
507 bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault
508 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
509 shld \pgd,PxD_VALUE_SHIFT,\index
510 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
512 extrd,u,*<> \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
513 ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd
515 L2_ptep \pgd,\pte,\index,\va,\fault
518 /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
519 * don't needlessly dirty the cache line if it was already set */
520 .macro update_ptep ptep,pte,tmp,tmp1
521 ldi _PAGE_ACCESSED,\tmp1
523 and,COND(<>) \tmp1,\pte,%r0
527 /* Set the dirty bit (and accessed bit). No need to be
528 * clever, this is only used from the dirty fault */
529 .macro update_dirty ptep,pte,tmp
530 ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp
535 /* Convert the pte and prot to tlb insertion values. How
536 * this happens is quite subtle, read below */
537 .macro make_insert_tlb spc,pte,prot
538 space_to_prot \spc \prot /* create prot id from space */
539 /* The following is the real subtlety. This is depositing
540 * T <-> _PAGE_REFTRAP
542 * B <-> _PAGE_DMB (memory break)
544 * Then incredible subtlety: The access rights are
545 * _PAGE_GATEWAY _PAGE_EXEC _PAGE_READ
546 * See 3-14 of the parisc 2.0 manual
548 * Finally, _PAGE_READ goes in the top bit of PL1 (so we
549 * trigger an access rights trap in user space if the user
550 * tries to read an unreadable page */
553 /* PAGE_USER indicates the page can be read with user privileges,
554 * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1
555 * contains _PAGE_READ */
556 extrd,u,*= \pte,_PAGE_USER_BIT+32,1,%r0
558 /* If we're a gateway page, drop PL2 back to zero for promotion
559 * to kernel privilege (so we can execute the page as kernel).
560 * Any privilege promotion page always denys read and write */
561 extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0
562 depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */
564 /* Enforce uncacheable pages.
565 * This should ONLY be use for MMIO on PA 2.0 machines.
566 * Memory/DMA is cache coherent on all PA2.0 machines we support
567 * (that means T-class is NOT supported) and the memory controllers
568 * on most of those machines only handles cache transactions.
570 extrd,u,*= \pte,_PAGE_NO_CACHE_BIT+32,1,%r0
573 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
574 extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58),64-PAGE_SHIFT,\pte
575 depdi _PAGE_SIZE_ENCODING_DEFAULT,63,63-58,\pte
578 /* Identical macro to make_insert_tlb above, except it
579 * makes the tlb entry for the differently formatted pa11
580 * insertion instructions */
581 .macro make_insert_tlb_11 spc,pte,prot
582 zdep \spc,30,15,\prot
584 extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0
586 extru,= \pte,_PAGE_USER_BIT,1,%r0
587 depi 7,11,3,\prot /* Set for user space (1 rsvd for read) */
588 extru,= \pte,_PAGE_GATEWAY_BIT,1,%r0
589 depi 0,11,2,\prot /* If Gateway, Set PL2 to 0 */
591 /* Get rid of prot bits and convert to page addr for iitlba */
593 depi _PAGE_SIZE_ENCODING_DEFAULT,31,ASM_PFN_PTE_SHIFT,\pte
594 extru \pte,24,25,\pte
597 /* This is for ILP32 PA2.0 only. The TLB insertion needs
598 * to extend into I/O space if the address is 0xfXXXXXXX
599 * so we extend the f's into the top word of the pte in
601 .macro f_extend pte,tmp
602 extrd,s \pte,42,4,\tmp
604 extrd,s \pte,63,25,\pte
607 /* The alias region is an 8MB aligned 16MB to do clear and
608 * copy user pages at addresses congruent with the user
611 * To use the alias page, you set %r26 up with the to TLB
612 * entry (identifying the physical page) and %r23 up with
613 * the from tlb entry (or nothing if only a to entry---for
614 * clear_user_page_asm) */
615 .macro do_alias spc,tmp,tmp1,va,pte,prot,fault
616 cmpib,COND(<>),n 0,\spc,\fault
617 ldil L%(TMPALIAS_MAP_START),\tmp
618 #if defined(CONFIG_64BIT) && (TMPALIAS_MAP_START >= 0x80000000)
619 /* on LP64, ldi will sign extend into the upper 32 bits,
620 * which is behaviour we don't want */
625 cmpb,COND(<>),n \tmp,\tmp1,\fault
626 ldi (_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),\prot
627 depd,z \prot,8,7,\prot
629 * OK, it is in the temp alias region, check whether "from" or "to".
630 * Check "subtle" note in pacache.S re: r23/r26.
633 extrd,u,*= \va,41,1,%r0
635 extrw,u,= \va,9,1,%r0
637 or,COND(tr) %r23,%r0,\pte
643 * Align fault_vector_20 on 4K boundary so that both
644 * fault_vector_11 and fault_vector_20 are on the
645 * same page. This is only necessary as long as we
646 * write protect the kernel text, which we may stop
647 * doing once we use large page translations to cover
648 * the static part of the kernel address space.
651 .export fault_vector_20
658 /* First vector is invalid (0) */
659 .ascii "cows can fly"
701 .export fault_vector_11
706 /* First vector is invalid (0) */
707 .ascii "cows can fly"
749 .import handle_interruption,code
750 .import do_cpu_irq_mask,code
753 * r26 = function to be called
754 * r25 = argument to pass in
755 * r24 = flags for do_fork()
757 * Kernel threads don't ever return, so they don't need
758 * a true register context. We just save away the arguments
759 * for copy_thread/ret_ to properly set up the child.
762 #define CLONE_VM 0x100 /* Must agree with <linux/sched.h> */
763 #define CLONE_UNTRACED 0x00800000
765 .export __kernel_thread, code
768 STREG %r2, -RP_OFFSET(%r30)
771 ldo PT_SZ_ALGN(%r30),%r30
773 /* Yo, function pointers in wide mode are little structs... -PB */
775 STREG %r2, PT_GR27(%r1) /* Store childs %dp */
778 STREG %r22, PT_GR22(%r1) /* save r22 (arg5) */
779 copy %r0, %r22 /* user_tid */
781 STREG %r26, PT_GR26(%r1) /* Store function & argument for child */
782 STREG %r25, PT_GR25(%r1)
783 ldil L%CLONE_UNTRACED, %r26
784 ldo CLONE_VM(%r26), %r26 /* Force CLONE_VM since only init_mm */
785 or %r26, %r24, %r26 /* will have kernel mappings. */
786 ldi 1, %r25 /* stack_start, signals kernel thread */
787 stw %r0, -52(%r30) /* user_tid */
789 ldo -16(%r30),%r29 /* Reference param save area */
792 copy %r1, %r24 /* pt_regs */
794 /* Parent Returns here */
796 LDREG -PT_SZ_ALGN-RP_OFFSET(%r30), %r2
797 ldo -PT_SZ_ALGN(%r30), %r30
804 * copy_thread moved args from temp save area set up above
805 * into task save area.
808 .export ret_from_kernel_thread
809 ret_from_kernel_thread:
811 /* Call schedule_tail first though */
812 BL schedule_tail, %r2
815 LDREG TI_TASK-THREAD_SZ_ALGN(%r30), %r1
816 LDREG TASK_PT_GR25(%r1), %r26
818 LDREG TASK_PT_GR27(%r1), %r27
819 LDREG TASK_PT_GR22(%r1), %r22
821 LDREG TASK_PT_GR26(%r1), %r1
826 ldo -16(%r30),%r29 /* Reference param save area */
827 loadgp /* Thread could have been in a module */
837 .import sys_execve, code
838 .export __execve, code
842 ldo PT_SZ_ALGN(%r30), %r30
843 STREG %r26, PT_GR26(%r16)
844 STREG %r25, PT_GR25(%r16)
845 STREG %r24, PT_GR24(%r16)
847 ldo -16(%r30),%r29 /* Reference param save area */
852 cmpib,=,n 0,%r28,intr_return /* forward */
854 /* yes, this will trap and die. */
863 * struct task_struct *_switch_to(struct task_struct *prev,
864 * struct task_struct *next)
866 * switch kernel stacks and return prev */
867 .export _switch_to, code
869 STREG %r2, -RP_OFFSET(%r30)
874 load32 _switch_to_ret, %r2
876 STREG %r2, TASK_PT_KPC(%r26)
877 LDREG TASK_PT_KPC(%r25), %r2
879 STREG %r30, TASK_PT_KSP(%r26)
880 LDREG TASK_PT_KSP(%r25), %r30
881 LDREG TASK_THREAD_INFO(%r25), %r25
886 mtctl %r0, %cr0 /* Needed for single stepping */
890 LDREG -RP_OFFSET(%r30), %r2
895 * Common rfi return path for interruptions, kernel execve, and
896 * sys_rt_sigreturn (sometimes). The sys_rt_sigreturn syscall will
897 * return via this path if the signal was received when the process
898 * was running; if the process was blocked on a syscall then the
899 * normal syscall_exit path is used. All syscalls for traced
900 * proceses exit via intr_restore.
902 * XXX If any syscalls that change a processes space id ever exit
903 * this way, then we will need to copy %sr3 in to PT_SR[3..7], and
910 .export syscall_exit_rfi
913 LDREG TI_TASK(%r16), %r16 /* thread_info -> task_struct */
914 ldo TASK_REGS(%r16),%r16
915 /* Force iaoq to userspace, as the user has had access to our current
916 * context via sigcontext. Also Filter the PSW for the same reason.
918 LDREG PT_IAOQ0(%r16),%r19
920 STREG %r19,PT_IAOQ0(%r16)
921 LDREG PT_IAOQ1(%r16),%r19
923 STREG %r19,PT_IAOQ1(%r16)
924 LDREG PT_PSW(%r16),%r19
925 load32 USER_PSW_MASK,%r1
927 load32 USER_PSW_HI_MASK,%r20
930 and %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */
932 or %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */
933 STREG %r19,PT_PSW(%r16)
936 * If we aren't being traced, we never saved space registers
937 * (we don't store them in the sigcontext), so set them
938 * to "proper" values now (otherwise we'll wind up restoring
939 * whatever was last stored in the task structure, which might
940 * be inconsistent if an interrupt occured while on the gateway
941 * page). Note that we may be "trashing" values the user put in
942 * them, but we don't support the user changing them.
945 STREG %r0,PT_SR2(%r16)
947 STREG %r19,PT_SR0(%r16)
948 STREG %r19,PT_SR1(%r16)
949 STREG %r19,PT_SR3(%r16)
950 STREG %r19,PT_SR4(%r16)
951 STREG %r19,PT_SR5(%r16)
952 STREG %r19,PT_SR6(%r16)
953 STREG %r19,PT_SR7(%r16)
956 /* NOTE: Need to enable interrupts incase we schedule. */
959 /* Check for software interrupts */
961 .import irq_stat,data
966 ldw TI_CPU(%r1),%r1 /* get cpu # - int */
967 /* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) amount
968 ** irq_stat[] is defined using ____cacheline_aligned.
970 SHLREG %r1,L1_CACHE_SHIFT,%r20
971 add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */
972 #endif /* CONFIG_SMP */
976 /* check for reschedule */
978 LDREG TI_FLAGS(%r1),%r19 /* sched.h: TIF_NEED_RESCHED */
979 bb,<,n %r19,31-TIF_NEED_RESCHED,intr_do_resched /* forward */
981 .import do_notify_resume,code
985 LDREG TI_FLAGS(%r1),%r19
986 load32 (_TIF_SIGPENDING|_TIF_RESTORE_SIGMASK), %r20
987 and,COND(<>) %r19, %r20, %r0
988 b,n intr_restore /* skip past if we've nothing to do */
990 /* This check is critical to having LWS
991 * working. The IASQ is zero on the gateway
992 * page and we cannot deliver any signals until
993 * we get off the gateway page.
995 * Only do signals if we are returning to user space
997 LDREG PT_IASQ0(%r16), %r20
998 CMPIB= 0,%r20,intr_restore /* backward */
1000 LDREG PT_IASQ1(%r16), %r20
1001 CMPIB= 0,%r20,intr_restore /* backward */
1004 copy %r0, %r25 /* long in_syscall = 0 */
1006 ldo -16(%r30),%r29 /* Reference param save area */
1009 BL do_notify_resume,%r2
1010 copy %r16, %r26 /* struct pt_regs *regs */
1017 ldo PT_FR31(%r29),%r1
1021 /* inverse of virt_map */
1023 rsm PSW_SM_QUIET,%r0 /* prepare for rfi */
1026 /* Restore space id's and special cr's from PT_REGS
1027 * structure pointed to by r29
1031 /* IMPORTANT: rest_stack restores r29 last (we are using it)!
1032 * It also restores r1 and r30.
1046 #ifndef CONFIG_PREEMPT
1047 # define intr_do_preempt intr_restore
1048 #endif /* !CONFIG_PREEMPT */
1050 .import schedule,code
1052 /* Only call schedule on return to userspace. If we're returning
1053 * to kernel space, we may schedule if CONFIG_PREEMPT, otherwise
1054 * we jump back to intr_restore.
1056 LDREG PT_IASQ0(%r16), %r20
1057 CMPIB= 0, %r20, intr_do_preempt
1059 LDREG PT_IASQ1(%r16), %r20
1060 CMPIB= 0, %r20, intr_do_preempt
1064 ldo -16(%r30),%r29 /* Reference param save area */
1067 ldil L%intr_check_sig, %r2
1068 #ifndef CONFIG_64BIT
1071 load32 schedule, %r20
1074 ldo R%intr_check_sig(%r2), %r2
1076 /* preempt the current task on returning to kernel
1077 * mode from an interrupt, iff need_resched is set,
1078 * and preempt_count is 0. otherwise, we continue on
1079 * our merry way back to the current running task.
1081 #ifdef CONFIG_PREEMPT
1082 .import preempt_schedule_irq,code
1084 rsm PSW_SM_I, %r0 /* disable interrupts */
1086 /* current_thread_info()->preempt_count */
1088 LDREG TI_PRE_COUNT(%r1), %r19
1089 CMPIB<> 0, %r19, intr_restore /* if preempt_count > 0 */
1090 nop /* prev insn branched backwards */
1092 /* check if we interrupted a critical path */
1093 LDREG PT_PSW(%r16), %r20
1094 bb,<,n %r20, 31 - PSW_SM_I, intr_restore
1097 BL preempt_schedule_irq, %r2
1100 b,n intr_restore /* ssm PSW_SM_I done by intr_restore */
1101 #endif /* CONFIG_PREEMPT */
1104 * External interrupts.
1113 #if 0 /* Interrupt Stack support not working yet! */
1116 /* FIXME! depi below has hardcoded idea of interrupt stack size (32k)*/
1130 ldo PT_FR0(%r29), %r24
1135 copy %r29, %r26 /* arg0 is pt_regs */
1136 copy %r29, %r16 /* save pt_regs */
1138 ldil L%intr_return, %r2
1141 ldo -16(%r30),%r29 /* Reference param save area */
1145 ldo R%intr_return(%r2), %r2 /* return to intr_return, not here */
1148 /* Generic interruptions (illegal insn, unaligned, page fault, etc) */
1150 .export intr_save, code /* for os_hpmc */
1166 /* If this trap is a itlb miss, skip saving/adjusting isr/ior */
1169 * FIXME: 1) Use a #define for the hardwired "6" below (and in
1171 * 2) Once we start executing code above 4 Gb, we need
1172 * to adjust iasq/iaoq here in the same way we
1173 * adjust isr/ior below.
1176 CMPIB=,n 6,%r26,skip_save_ior
1179 mfctl %cr20, %r16 /* isr */
1180 nop /* serialize mfctl on PA 2.0 to avoid 4 cycle penalty */
1181 mfctl %cr21, %r17 /* ior */
1186 * If the interrupted code was running with W bit off (32 bit),
1187 * clear the b bits (bits 0 & 1) in the ior.
1188 * save_specials left ipsw value in r8 for us to test.
1190 extrd,u,*<> %r8,PSW_W_BIT,1,%r0
1194 * FIXME: This code has hardwired assumptions about the split
1195 * between space bits and offset bits. This will change
1196 * when we allow alternate page sizes.
1199 /* adjust isr/ior. */
1200 extrd,u %r16,63,SPACEID_SHIFT,%r1 /* get high bits from isr for ior */
1201 depd %r1,31,SPACEID_SHIFT,%r17 /* deposit them into ior */
1202 depdi 0,63,SPACEID_SHIFT,%r16 /* clear them from isr */
1204 STREG %r16, PT_ISR(%r29)
1205 STREG %r17, PT_IOR(%r29)
1212 ldo PT_FR0(%r29), %r25
1217 copy %r29, %r25 /* arg1 is pt_regs */
1219 ldo -16(%r30),%r29 /* Reference param save area */
1222 ldil L%intr_check_sig, %r2
1223 copy %r25, %r16 /* save pt_regs */
1225 b handle_interruption
1226 ldo R%intr_check_sig(%r2), %r2
1230 * Note for all tlb miss handlers:
1232 * cr24 contains a pointer to the kernel address space
1235 * cr25 contains a pointer to the current user address
1236 * space page directory.
1238 * sr3 will contain the space id of the user address space
1239 * of the current running thread while that thread is
1240 * running in the kernel.
1244 * register number allocations. Note that these are all
1245 * in the shadowed registers
1248 t0 = r1 /* temporary register 0 */
1249 va = r8 /* virtual address for which the trap occured */
1250 t1 = r9 /* temporary register 1 */
1251 pte = r16 /* pte/phys page # */
1252 prot = r17 /* prot bits */
1253 spc = r24 /* space for which the trap occured */
1254 ptp = r25 /* page directory/page table pointer */
1259 space_adjust spc,va,t0
1261 space_check spc,t0,dtlb_fault
1263 L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w
1265 update_ptep ptp,pte,t0,t1
1267 make_insert_tlb spc,pte,prot
1274 dtlb_check_alias_20w:
1275 do_alias spc,t0,t1,va,pte,prot,dtlb_fault
1283 space_adjust spc,va,t0
1285 space_check spc,t0,nadtlb_fault
1287 L3_ptep ptp,pte,t0,va,nadtlb_check_flush_20w
1289 update_ptep ptp,pte,t0,t1
1291 make_insert_tlb spc,pte,prot
1298 nadtlb_check_flush_20w:
1299 bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate
1301 /* Insert a "flush only" translation */
1306 /* Get rid of prot bits and convert to page addr for idtlbt */
1309 extrd,u pte,56,52,pte
1320 space_check spc,t0,dtlb_fault
1322 L2_ptep ptp,pte,t0,va,dtlb_check_alias_11
1324 update_ptep ptp,pte,t0,t1
1326 make_insert_tlb_11 spc,pte,prot
1328 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1331 idtlba pte,(%sr1,va)
1332 idtlbp prot,(%sr1,va)
1334 mtsp t0, %sr1 /* Restore sr1 */
1339 dtlb_check_alias_11:
1341 /* Check to see if fault is in the temporary alias region */
1343 cmpib,<>,n 0,spc,dtlb_fault /* forward */
1344 ldil L%(TMPALIAS_MAP_START),t0
1347 cmpb,<>,n t0,t1,dtlb_fault /* forward */
1348 ldi (_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),prot
1349 depw,z prot,8,7,prot
1352 * OK, it is in the temp alias region, check whether "from" or "to".
1353 * Check "subtle" note in pacache.S re: r23/r26.
1357 or,tr %r23,%r0,pte /* If "from" use "from" page */
1358 or %r26,%r0,pte /* else "to", use "to" page */
1369 space_check spc,t0,nadtlb_fault
1371 L2_ptep ptp,pte,t0,va,nadtlb_check_flush_11
1373 update_ptep ptp,pte,t0,t1
1375 make_insert_tlb_11 spc,pte,prot
1378 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1381 idtlba pte,(%sr1,va)
1382 idtlbp prot,(%sr1,va)
1384 mtsp t0, %sr1 /* Restore sr1 */
1389 nadtlb_check_flush_11:
1390 bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate
1392 /* Insert a "flush only" translation */
1397 /* Get rid of prot bits and convert to page addr for idtlba */
1402 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1405 idtlba pte,(%sr1,va)
1406 idtlbp prot,(%sr1,va)
1408 mtsp t0, %sr1 /* Restore sr1 */
1414 space_adjust spc,va,t0
1416 space_check spc,t0,dtlb_fault
1418 L2_ptep ptp,pte,t0,va,dtlb_check_alias_20
1420 update_ptep ptp,pte,t0,t1
1422 make_insert_tlb spc,pte,prot
1431 dtlb_check_alias_20:
1432 do_alias spc,t0,t1,va,pte,prot,dtlb_fault
1442 space_check spc,t0,nadtlb_fault
1444 L2_ptep ptp,pte,t0,va,nadtlb_check_flush_20
1446 update_ptep ptp,pte,t0,t1
1448 make_insert_tlb spc,pte,prot
1457 nadtlb_check_flush_20:
1458 bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate
1460 /* Insert a "flush only" translation */
1465 /* Get rid of prot bits and convert to page addr for idtlbt */
1468 extrd,u pte,56,32,pte
1478 * Non access misses can be caused by fdc,fic,pdc,lpa,probe and
1479 * probei instructions. We don't want to fault for these
1480 * instructions (not only does it not make sense, it can cause
1481 * deadlocks, since some flushes are done with the mmap
1482 * semaphore held). If the translation doesn't exist, we can't
1483 * insert a translation, so have to emulate the side effects
1484 * of the instruction. Since we don't insert a translation
1485 * we can get a lot of faults during a flush loop, so it makes
1486 * sense to try to do it here with minimum overhead. We only
1487 * emulate fdc,fic,pdc,probew,prober instructions whose base
1488 * and index registers are not shadowed. We defer everything
1489 * else to the "slow" path.
1492 mfctl %cr19,%r9 /* Get iir */
1494 /* PA 2.0 Arch Ref. Book pg 382 has a good description of the insn bits.
1495 Checks for fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw */
1497 /* Checks for fdc,fdce,pdc,"fic,4f" only */
1500 cmpb,<>,n %r16,%r17,nadtlb_probe_check
1501 bb,>=,n %r9,26,nadtlb_nullify /* m bit not set, just nullify */
1502 BL get_register,%r25
1503 extrw,u %r9,15,5,%r8 /* Get index register # */
1504 CMPIB=,n -1,%r1,nadtlb_fault /* have to use slow path */
1506 BL get_register,%r25
1507 extrw,u %r9,10,5,%r8 /* Get base register # */
1508 CMPIB=,n -1,%r1,nadtlb_fault /* have to use slow path */
1509 BL set_register,%r25
1510 add,l %r1,%r24,%r1 /* doesn't affect c/b bits */
1515 or %r8,%r9,%r8 /* Set PSW_N */
1522 When there is no translation for the probe address then we
1523 must nullify the insn and return zero in the target regsiter.
1524 This will indicate to the calling code that it does not have
1525 write/read privileges to this address.
1527 This should technically work for prober and probew in PA 1.1,
1528 and also probe,r and probe,w in PA 2.0
1530 WARNING: USE ONLY NON-SHADOW REGISTERS WITH PROBE INSN!
1531 THE SLOW-PATH EMULATION HAS NOT BEEN WRITTEN YET.
1537 cmpb,<>,n %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/
1538 BL get_register,%r25 /* Find the target register */
1539 extrw,u %r9,31,5,%r8 /* Get target register */
1540 CMPIB=,n -1,%r1,nadtlb_fault /* have to use slow path */
1541 BL set_register,%r25
1542 copy %r0,%r1 /* Write zero to target register */
1543 b nadtlb_nullify /* Nullify return insn */
1551 * I miss is a little different, since we allow users to fault
1552 * on the gateway page which is in the kernel address space.
1555 space_adjust spc,va,t0
1557 space_check spc,t0,itlb_fault
1559 L3_ptep ptp,pte,t0,va,itlb_fault
1561 update_ptep ptp,pte,t0,t1
1563 make_insert_tlb spc,pte,prot
1575 space_check spc,t0,itlb_fault
1577 L2_ptep ptp,pte,t0,va,itlb_fault
1579 update_ptep ptp,pte,t0,t1
1581 make_insert_tlb_11 spc,pte,prot
1583 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1586 iitlba pte,(%sr1,va)
1587 iitlbp prot,(%sr1,va)
1589 mtsp t0, %sr1 /* Restore sr1 */
1597 space_check spc,t0,itlb_fault
1599 L2_ptep ptp,pte,t0,va,itlb_fault
1601 update_ptep ptp,pte,t0,t1
1603 make_insert_tlb spc,pte,prot
1617 space_adjust spc,va,t0
1619 space_check spc,t0,dbit_fault
1621 L3_ptep ptp,pte,t0,va,dbit_fault
1624 CMPIB=,n 0,spc,dbit_nolock_20w
1625 load32 PA(pa_dbit_lock),t0
1629 cmpib,= 0,t1,dbit_spin_20w
1634 update_dirty ptp,pte,t1
1636 make_insert_tlb spc,pte,prot
1640 CMPIB=,n 0,spc,dbit_nounlock_20w
1655 space_check spc,t0,dbit_fault
1657 L2_ptep ptp,pte,t0,va,dbit_fault
1660 CMPIB=,n 0,spc,dbit_nolock_11
1661 load32 PA(pa_dbit_lock),t0
1665 cmpib,= 0,t1,dbit_spin_11
1670 update_dirty ptp,pte,t1
1672 make_insert_tlb_11 spc,pte,prot
1674 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1677 idtlba pte,(%sr1,va)
1678 idtlbp prot,(%sr1,va)
1680 mtsp t1, %sr1 /* Restore sr1 */
1682 CMPIB=,n 0,spc,dbit_nounlock_11
1695 space_check spc,t0,dbit_fault
1697 L2_ptep ptp,pte,t0,va,dbit_fault
1700 CMPIB=,n 0,spc,dbit_nolock_20
1701 load32 PA(pa_dbit_lock),t0
1705 cmpib,= 0,t1,dbit_spin_20
1710 update_dirty ptp,pte,t1
1712 make_insert_tlb spc,pte,prot
1719 CMPIB=,n 0,spc,dbit_nounlock_20
1730 .import handle_interruption,code
1734 ldi 31,%r8 /* Use an unused code */
1752 /* Register saving semantics for system calls:
1754 %r1 clobbered by system call macro in userspace
1755 %r2 saved in PT_REGS by gateway page
1756 %r3 - %r18 preserved by C code (saved by signal code)
1757 %r19 - %r20 saved in PT_REGS by gateway page
1758 %r21 - %r22 non-standard syscall args
1759 stored in kernel stack by gateway page
1760 %r23 - %r26 arg3-arg0, saved in PT_REGS by gateway page
1761 %r27 - %r30 saved in PT_REGS by gateway page
1762 %r31 syscall return pointer
1765 /* Floating point registers (FIXME: what do we do with these?)
1767 %fr0 - %fr3 status/exception, not preserved
1768 %fr4 - %fr7 arguments
1769 %fr8 - %fr11 not preserved by C code
1770 %fr12 - %fr21 preserved by C code
1771 %fr22 - %fr31 not preserved by C code
1774 .macro reg_save regs
1775 STREG %r3, PT_GR3(\regs)
1776 STREG %r4, PT_GR4(\regs)
1777 STREG %r5, PT_GR5(\regs)
1778 STREG %r6, PT_GR6(\regs)
1779 STREG %r7, PT_GR7(\regs)
1780 STREG %r8, PT_GR8(\regs)
1781 STREG %r9, PT_GR9(\regs)
1782 STREG %r10,PT_GR10(\regs)
1783 STREG %r11,PT_GR11(\regs)
1784 STREG %r12,PT_GR12(\regs)
1785 STREG %r13,PT_GR13(\regs)
1786 STREG %r14,PT_GR14(\regs)
1787 STREG %r15,PT_GR15(\regs)
1788 STREG %r16,PT_GR16(\regs)
1789 STREG %r17,PT_GR17(\regs)
1790 STREG %r18,PT_GR18(\regs)
1793 .macro reg_restore regs
1794 LDREG PT_GR3(\regs), %r3
1795 LDREG PT_GR4(\regs), %r4
1796 LDREG PT_GR5(\regs), %r5
1797 LDREG PT_GR6(\regs), %r6
1798 LDREG PT_GR7(\regs), %r7
1799 LDREG PT_GR8(\regs), %r8
1800 LDREG PT_GR9(\regs), %r9
1801 LDREG PT_GR10(\regs),%r10
1802 LDREG PT_GR11(\regs),%r11
1803 LDREG PT_GR12(\regs),%r12
1804 LDREG PT_GR13(\regs),%r13
1805 LDREG PT_GR14(\regs),%r14
1806 LDREG PT_GR15(\regs),%r15
1807 LDREG PT_GR16(\regs),%r16
1808 LDREG PT_GR17(\regs),%r17
1809 LDREG PT_GR18(\regs),%r18
1812 .export sys_fork_wrapper
1813 .export child_return
1815 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1816 ldo TASK_REGS(%r1),%r1
1819 STREG %r3, PT_CR27(%r1)
1821 STREG %r2,-RP_OFFSET(%r30)
1822 ldo FRAME_SIZE(%r30),%r30
1824 ldo -16(%r30),%r29 /* Reference param save area */
1827 /* These are call-clobbered registers and therefore
1828 also syscall-clobbered (we hope). */
1829 STREG %r2,PT_GR19(%r1) /* save for child */
1830 STREG %r30,PT_GR21(%r1)
1832 LDREG PT_GR30(%r1),%r25
1837 LDREG -RP_OFFSET-FRAME_SIZE(%r30),%r2
1839 ldo -FRAME_SIZE(%r30),%r30 /* get the stackframe */
1840 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1841 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1843 LDREG PT_CR27(%r1), %r3
1847 /* strace expects syscall # to be preserved in r20 */
1850 STREG %r20,PT_GR20(%r1)
1852 /* Set the return value for the child */
1854 BL schedule_tail, %r2
1857 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE-FRAME_SIZE(%r30), %r1
1858 LDREG TASK_PT_GR19(%r1),%r2
1863 .export sys_clone_wrapper
1865 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1866 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1869 STREG %r3, PT_CR27(%r1)
1871 STREG %r2,-RP_OFFSET(%r30)
1872 ldo FRAME_SIZE(%r30),%r30
1874 ldo -16(%r30),%r29 /* Reference param save area */
1877 /* WARNING - Clobbers r19 and r21, userspace must save these! */
1878 STREG %r2,PT_GR19(%r1) /* save for child */
1879 STREG %r30,PT_GR21(%r1)
1884 LDREG -RP_OFFSET-FRAME_SIZE(%r30),%r2
1886 .export sys_vfork_wrapper
1888 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1889 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1892 STREG %r3, PT_CR27(%r1)
1894 STREG %r2,-RP_OFFSET(%r30)
1895 ldo FRAME_SIZE(%r30),%r30
1897 ldo -16(%r30),%r29 /* Reference param save area */
1900 STREG %r2,PT_GR19(%r1) /* save for child */
1901 STREG %r30,PT_GR21(%r1)
1907 LDREG -RP_OFFSET-FRAME_SIZE(%r30),%r2
1910 .macro execve_wrapper execve
1911 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1912 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1915 * Do we need to save/restore r3-r18 here?
1916 * I don't think so. why would new thread need old
1917 * threads registers?
1920 /* %arg0 - %arg3 are already saved for us. */
1922 STREG %r2,-RP_OFFSET(%r30)
1923 ldo FRAME_SIZE(%r30),%r30
1925 ldo -16(%r30),%r29 /* Reference param save area */
1930 ldo -FRAME_SIZE(%r30),%r30
1931 LDREG -RP_OFFSET(%r30),%r2
1933 /* If exec succeeded we need to load the args */
1936 cmpb,>>= %r28,%r1,error_\execve
1944 .export sys_execve_wrapper
1948 execve_wrapper sys_execve
1951 .export sys32_execve_wrapper
1952 .import sys32_execve
1954 sys32_execve_wrapper:
1955 execve_wrapper sys32_execve
1958 .export sys_rt_sigreturn_wrapper
1959 sys_rt_sigreturn_wrapper:
1960 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26
1961 ldo TASK_REGS(%r26),%r26 /* get pt regs */
1962 /* Don't save regs, we are going to restore them from sigcontext. */
1963 STREG %r2, -RP_OFFSET(%r30)
1965 ldo FRAME_SIZE(%r30), %r30
1966 BL sys_rt_sigreturn,%r2
1967 ldo -16(%r30),%r29 /* Reference param save area */
1969 BL sys_rt_sigreturn,%r2
1970 ldo FRAME_SIZE(%r30), %r30
1973 ldo -FRAME_SIZE(%r30), %r30
1974 LDREG -RP_OFFSET(%r30), %r2
1976 /* FIXME: I think we need to restore a few more things here. */
1977 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1978 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1981 /* If the signal was received while the process was blocked on a
1982 * syscall, then r2 will take us to syscall_exit; otherwise r2 will
1983 * take us to syscall_exit_rfi and on to intr_return.
1986 LDREG PT_GR28(%r1),%r28 /* reload original r28 for syscall_exit */
1988 .export sys_sigaltstack_wrapper
1989 sys_sigaltstack_wrapper:
1990 /* Get the user stack pointer */
1991 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1992 ldo TASK_REGS(%r1),%r24 /* get pt regs */
1993 LDREG TASK_PT_GR30(%r24),%r24
1994 STREG %r2, -RP_OFFSET(%r30)
1996 ldo FRAME_SIZE(%r30), %r30
1997 BL do_sigaltstack,%r2
1998 ldo -16(%r30),%r29 /* Reference param save area */
2000 BL do_sigaltstack,%r2
2001 ldo FRAME_SIZE(%r30), %r30
2004 ldo -FRAME_SIZE(%r30), %r30
2005 LDREG -RP_OFFSET(%r30), %r2
2010 .export sys32_sigaltstack_wrapper
2011 sys32_sigaltstack_wrapper:
2012 /* Get the user stack pointer */
2013 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r24
2014 LDREG TASK_PT_GR30(%r24),%r24
2015 STREG %r2, -RP_OFFSET(%r30)
2016 ldo FRAME_SIZE(%r30), %r30
2017 BL do_sigaltstack32,%r2
2018 ldo -16(%r30),%r29 /* Reference param save area */
2020 ldo -FRAME_SIZE(%r30), %r30
2021 LDREG -RP_OFFSET(%r30), %r2
2026 .export syscall_exit
2029 /* NOTE: HP-UX syscalls also come through here
2030 * after hpux_syscall_exit fixes up return
2033 /* NOTE: Not all syscalls exit this way. rt_sigreturn will exit
2034 * via syscall_exit_rfi if the signal was received while the process
2038 /* save return value now */
2041 LDREG TI_TASK(%r1),%r1
2042 STREG %r28,TASK_PT_GR28(%r1)
2046 /* <linux/personality.h> cannot be easily included */
2047 #define PER_HPUX 0x10
2048 LDREG TASK_PERSONALITY(%r1),%r19
2050 /* We can't use "CMPIB<> PER_HPUX" since "im5" field is sign extended */
2051 ldo -PER_HPUX(%r19), %r19
2054 /* Save other hpux returns if personality is PER_HPUX */
2055 STREG %r22,TASK_PT_GR22(%r1)
2056 STREG %r29,TASK_PT_GR29(%r1)
2059 #endif /* CONFIG_HPUX */
2061 /* Seems to me that dp could be wrong here, if the syscall involved
2062 * calling a module, and nothing got round to restoring dp on return.
2068 /* Check for software interrupts */
2070 .import irq_stat,data
2072 load32 irq_stat,%r19
2075 /* sched.h: int processor */
2076 /* %r26 is used as scratch register to index into irq_stat[] */
2077 ldw TI_CPU-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26 /* cpu # */
2079 /* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) bits */
2080 SHLREG %r26,L1_CACHE_SHIFT,%r20
2081 add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */
2082 #endif /* CONFIG_SMP */
2084 syscall_check_resched:
2086 /* check for reschedule */
2088 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19 /* long */
2089 bb,<,n %r19, 31-TIF_NEED_RESCHED, syscall_do_resched /* forward */
2091 .import do_signal,code
2093 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19
2094 load32 (_TIF_SIGPENDING|_TIF_RESTORE_SIGMASK), %r26
2095 and,COND(<>) %r19, %r26, %r0
2096 b,n syscall_restore /* skip past if we've nothing to do */
2099 /* Save callee-save registers (for sigcontext).
2100 * FIXME: After this point the process structure should be
2101 * consistent with all the relevant state of the process
2102 * before the syscall. We need to verify this.
2104 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
2105 ldo TASK_REGS(%r1), %r26 /* struct pt_regs *regs */
2109 ldo -16(%r30),%r29 /* Reference param save area */
2112 BL do_notify_resume,%r2
2113 ldi 1, %r25 /* long in_syscall = 1 */
2115 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
2116 ldo TASK_REGS(%r1), %r20 /* reload pt_regs */
2119 b,n syscall_check_sig
2122 /* Are we being ptraced? */
2123 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
2125 LDREG TASK_PTRACE(%r1), %r19
2126 bb,< %r19,31,syscall_restore_rfi
2129 ldo TASK_PT_FR31(%r1),%r19 /* reload fpregs */
2132 LDREG TASK_PT_SAR(%r1),%r19 /* restore SAR */
2135 LDREG TASK_PT_GR2(%r1),%r2 /* restore user rp */
2136 LDREG TASK_PT_GR19(%r1),%r19
2137 LDREG TASK_PT_GR20(%r1),%r20
2138 LDREG TASK_PT_GR21(%r1),%r21
2139 LDREG TASK_PT_GR22(%r1),%r22
2140 LDREG TASK_PT_GR23(%r1),%r23
2141 LDREG TASK_PT_GR24(%r1),%r24
2142 LDREG TASK_PT_GR25(%r1),%r25
2143 LDREG TASK_PT_GR26(%r1),%r26
2144 LDREG TASK_PT_GR27(%r1),%r27 /* restore user dp */
2145 LDREG TASK_PT_GR28(%r1),%r28 /* syscall return value */
2146 LDREG TASK_PT_GR29(%r1),%r29
2147 LDREG TASK_PT_GR31(%r1),%r31 /* restore syscall rp */
2149 /* NOTE: We use rsm/ssm pair to make this operation atomic */
2151 LDREG TASK_PT_GR30(%r1),%r30 /* restore user sp */
2152 mfsp %sr3,%r1 /* Get users space id */
2153 mtsp %r1,%sr7 /* Restore sr7 */
2156 /* Set sr2 to zero for userspace syscalls to work. */
2158 mtsp %r1,%sr4 /* Restore sr4 */
2159 mtsp %r1,%sr5 /* Restore sr5 */
2160 mtsp %r1,%sr6 /* Restore sr6 */
2162 depi 3,31,2,%r31 /* ensure return to user mode. */
2165 /* decide whether to reset the wide mode bit
2167 * For a syscall, the W bit is stored in the lowest bit
2168 * of sp. Extract it and reset W if it is zero */
2169 extrd,u,*<> %r30,63,1,%r1
2171 /* now reset the lowest bit of sp if it was set */
2174 be,n 0(%sr3,%r31) /* return to user space */
2176 /* We have to return via an RFI, so that PSW T and R bits can be set
2178 * This sets up pt_regs so we can return via intr_restore, which is not
2179 * the most efficient way of doing things, but it works.
2181 syscall_restore_rfi:
2182 ldo -1(%r0),%r2 /* Set recovery cntr to -1 */
2183 mtctl %r2,%cr0 /* for immediate trap */
2184 LDREG TASK_PT_PSW(%r1),%r2 /* Get old PSW */
2185 ldi 0x0b,%r20 /* Create new PSW */
2186 depi -1,13,1,%r20 /* C, Q, D, and I bits */
2188 /* The values of PA_SINGLESTEP_BIT and PA_BLOCKSTEP_BIT are
2189 * set in include/linux/ptrace.h and converted to PA bitmap
2190 * numbers in asm-offsets.c */
2192 /* if ((%r19.PA_SINGLESTEP_BIT)) { %r20.27=1} */
2193 extru,= %r19,PA_SINGLESTEP_BIT,1,%r0
2194 depi -1,27,1,%r20 /* R bit */
2196 /* if ((%r19.PA_BLOCKSTEP_BIT)) { %r20.7=1} */
2197 extru,= %r19,PA_BLOCKSTEP_BIT,1,%r0
2198 depi -1,7,1,%r20 /* T bit */
2200 STREG %r20,TASK_PT_PSW(%r1)
2202 /* Always store space registers, since sr3 can be changed (e.g. fork) */
2205 STREG %r25,TASK_PT_SR3(%r1)
2206 STREG %r25,TASK_PT_SR4(%r1)
2207 STREG %r25,TASK_PT_SR5(%r1)
2208 STREG %r25,TASK_PT_SR6(%r1)
2209 STREG %r25,TASK_PT_SR7(%r1)
2210 STREG %r25,TASK_PT_IASQ0(%r1)
2211 STREG %r25,TASK_PT_IASQ1(%r1)
2214 /* Now if old D bit is clear, it means we didn't save all registers
2215 * on syscall entry, so do that now. This only happens on TRACEME
2216 * calls, or if someone attached to us while we were on a syscall.
2217 * We could make this more efficient by not saving r3-r18, but
2218 * then we wouldn't be able to use the common intr_restore path.
2219 * It is only for traced processes anyway, so performance is not
2222 bb,< %r2,30,pt_regs_ok /* Branch if D set */
2223 ldo TASK_REGS(%r1),%r25
2224 reg_save %r25 /* Save r3 to r18 */
2226 /* Save the current sr */
2228 STREG %r2,TASK_PT_SR0(%r1)
2230 /* Save the scratch sr */
2232 STREG %r2,TASK_PT_SR1(%r1)
2234 /* sr2 should be set to zero for userspace syscalls */
2235 STREG %r0,TASK_PT_SR2(%r1)
2238 LDREG TASK_PT_GR31(%r1),%r2
2239 depi 3,31,2,%r2 /* ensure return to user mode. */
2240 STREG %r2,TASK_PT_IAOQ0(%r1)
2242 STREG %r2,TASK_PT_IAOQ1(%r1)
2247 .import schedule,code
2251 ldo -16(%r30),%r29 /* Reference param save area */
2255 b syscall_check_bh /* if resched, we start over again */
2259 * get_register is used by the non access tlb miss handlers to
2260 * copy the value of the general register specified in r8 into
2261 * r1. This routine can't be used for shadowed registers, since
2262 * the rfir will restore the original value. So, for the shadowed
2263 * registers we put a -1 into r1 to indicate that the register
2264 * should not be used (the register being copied could also have
2265 * a -1 in it, but that is OK, it just means that we will have
2266 * to use the slow path instead).
2272 bv %r0(%r25) /* r0 */
2274 bv %r0(%r25) /* r1 - shadowed */
2276 bv %r0(%r25) /* r2 */
2278 bv %r0(%r25) /* r3 */
2280 bv %r0(%r25) /* r4 */
2282 bv %r0(%r25) /* r5 */
2284 bv %r0(%r25) /* r6 */
2286 bv %r0(%r25) /* r7 */
2288 bv %r0(%r25) /* r8 - shadowed */
2290 bv %r0(%r25) /* r9 - shadowed */
2292 bv %r0(%r25) /* r10 */
2294 bv %r0(%r25) /* r11 */
2296 bv %r0(%r25) /* r12 */
2298 bv %r0(%r25) /* r13 */
2300 bv %r0(%r25) /* r14 */
2302 bv %r0(%r25) /* r15 */
2304 bv %r0(%r25) /* r16 - shadowed */
2306 bv %r0(%r25) /* r17 - shadowed */
2308 bv %r0(%r25) /* r18 */
2310 bv %r0(%r25) /* r19 */
2312 bv %r0(%r25) /* r20 */
2314 bv %r0(%r25) /* r21 */
2316 bv %r0(%r25) /* r22 */
2318 bv %r0(%r25) /* r23 */
2320 bv %r0(%r25) /* r24 - shadowed */
2322 bv %r0(%r25) /* r25 - shadowed */
2324 bv %r0(%r25) /* r26 */
2326 bv %r0(%r25) /* r27 */
2328 bv %r0(%r25) /* r28 */
2330 bv %r0(%r25) /* r29 */
2332 bv %r0(%r25) /* r30 */
2334 bv %r0(%r25) /* r31 */
2338 * set_register is used by the non access tlb miss handlers to
2339 * copy the value of r1 into the general register specified in
2346 bv %r0(%r25) /* r0 (silly, but it is a place holder) */
2348 bv %r0(%r25) /* r1 */
2350 bv %r0(%r25) /* r2 */
2352 bv %r0(%r25) /* r3 */
2354 bv %r0(%r25) /* r4 */
2356 bv %r0(%r25) /* r5 */
2358 bv %r0(%r25) /* r6 */
2360 bv %r0(%r25) /* r7 */
2362 bv %r0(%r25) /* r8 */
2364 bv %r0(%r25) /* r9 */
2366 bv %r0(%r25) /* r10 */
2368 bv %r0(%r25) /* r11 */
2370 bv %r0(%r25) /* r12 */
2372 bv %r0(%r25) /* r13 */
2374 bv %r0(%r25) /* r14 */
2376 bv %r0(%r25) /* r15 */
2378 bv %r0(%r25) /* r16 */
2380 bv %r0(%r25) /* r17 */
2382 bv %r0(%r25) /* r18 */
2384 bv %r0(%r25) /* r19 */
2386 bv %r0(%r25) /* r20 */
2388 bv %r0(%r25) /* r21 */
2390 bv %r0(%r25) /* r22 */
2392 bv %r0(%r25) /* r23 */
2394 bv %r0(%r25) /* r24 */
2396 bv %r0(%r25) /* r25 */
2398 bv %r0(%r25) /* r26 */
2400 bv %r0(%r25) /* r27 */
2402 bv %r0(%r25) /* r28 */
2404 bv %r0(%r25) /* r29 */
2406 bv %r0(%r25) /* r30 */
2408 bv %r0(%r25) /* r31 */