drivers/dma/coh901318.c

   1 /*
   2  * driver/dma/coh901318.c
   3  *
   4  * Copyright (C) 2007-2009 ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  * DMA driver for COH 901 318
   7  * Author: Per Friden <per.friden@stericsson.com>
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/module.h>
  12 #include <linux/kernel.h> /* printk() */
  13 #include <linux/fs.h> /* everything... */
  14 #include <linux/scatterlist.h>
  15 #include <linux/slab.h> /* kmalloc() */
  16 #include <linux/dmaengine.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/device.h>
  19 #include <linux/irqreturn.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/uaccess.h>
  23 #include <linux/debugfs.h>
  24 #include <mach/coh901318.h>
  25
  26 #include "coh901318_lli.h"
  27 #include "dmaengine.h"
  28
  29 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
  30
  31 #ifdef VERBOSE_DEBUG
  32 #define COH_DBG(x) ({ if (1) x; 0; })
  33 #else
  34 #define COH_DBG(x) ({ if (0) x; 0; })
  35 #endif
  36
  37 struct coh901318_desc {
  38         struct dma_async_tx_descriptor desc;
  39         struct list_head node;
  40         struct scatterlist *sg;
  41         unsigned int sg_len;
  42         struct coh901318_lli *lli;
  43         enum dma_transfer_direction dir;
  44         unsigned long flags;
  45         u32 head_config;
  46         u32 head_ctrl;
  47 };
  48
  49 struct coh901318_base {
  50         struct device *dev;
  51         void __iomem *virtbase;
  52         struct coh901318_pool pool;
  53         struct powersave pm;
  54         struct dma_device dma_slave;
  55         struct dma_device dma_memcpy;
  56         struct coh901318_chan *chans;
  57         struct coh901318_platform *platform;
  58 };
  59
  60 struct coh901318_chan {
  61         spinlock_t lock;
  62         int allocated;
  63         int id;
  64         int stopped;
  65
  66         struct work_struct free_work;
  67         struct dma_chan chan;
  68
  69         struct tasklet_struct tasklet;
  70
  71         struct list_head active;
  72         struct list_head queue;
  73         struct list_head free;
  74
  75         unsigned long nbr_active_done;
  76         unsigned long busy;
  77
  78         u32 runtime_addr;
  79         u32 runtime_ctrl;
  80
  81         struct coh901318_base *base;
  82 };
  83
  84 static void coh901318_list_print(struct coh901318_chan *cohc,
  85                                  struct coh901318_lli *lli)
  86 {
  87         struct coh901318_lli *l = lli;
  88         int i = 0;
  89
  90         while (l) {
  91                 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
  92                          ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
  93                          i, l, l->control, l->src_addr, l->dst_addr,
  94                          l->link_addr, l->virt_link_addr);
  95                 i++;
  96                 l = l->virt_link_addr;
  97         }
  98 }
  99
 100 #ifdef CONFIG_DEBUG_FS
 101
 102 #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
 103
 104 static struct coh901318_base *debugfs_dma_base;
 105 static struct dentry *dma_dentry;
 106
 107 static int coh901318_debugfs_read(struct file *file, char __user *buf,
 108                                   size_t count, loff_t *f_pos)
 109 {
 110         u64 started_channels = debugfs_dma_base->pm.started_channels;
 111         int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
 112         int i;
 113         int ret = 0;
 114         char *dev_buf;
 115         char *tmp;
 116         int dev_size;
 117
 118         dev_buf = kmalloc(4*1024, GFP_KERNEL);
 119         if (dev_buf == NULL)
 120                 goto err_kmalloc;
 121         tmp = dev_buf;
 122
 123         tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
 124
 125         for (i = 0; i < debugfs_dma_base->platform->max_channels; i++)
 126                 if (started_channels & (1 << i))
 127                         tmp += sprintf(tmp, "channel %d\n", i);
 128
 129         tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
 130         dev_size = tmp  - dev_buf;
 131
 132         /* No more to read if offset != 0 */
 133         if (*f_pos > dev_size)
 134                 goto out;
 135
 136         if (count > dev_size - *f_pos)
 137                 count = dev_size - *f_pos;
 138
 139         if (copy_to_user(buf, dev_buf + *f_pos, count))
 140                 ret = -EINVAL;
 141         ret = count;
 142         *f_pos += count;
 143
 144  out:
 145         kfree(dev_buf);
 146         return ret;
 147
 148  err_kmalloc:
 149         return 0;
 150 }
 151
 152 static const struct file_operations coh901318_debugfs_status_operations = {
 153         .owner          = THIS_MODULE,
 154         .open           = simple_open,
 155         .read           = coh901318_debugfs_read,
 156         .llseek         = default_llseek,
 157 };
 158
 159
 160 static int __init init_coh901318_debugfs(void)
 161 {
 162
 163         dma_dentry = debugfs_create_dir("dma", NULL);
 164
 165         (void) debugfs_create_file("status",
 166                                    S_IFREG | S_IRUGO,
 167                                    dma_dentry, NULL,
 168                                    &coh901318_debugfs_status_operations);
 169         return 0;
 170 }
 171
 172 static void __exit exit_coh901318_debugfs(void)
 173 {
 174         debugfs_remove_recursive(dma_dentry);
 175 }
 176
 177 module_init(init_coh901318_debugfs);
 178 module_exit(exit_coh901318_debugfs);
 179 #else
 180
 181 #define COH901318_DEBUGFS_ASSIGN(x, y)
 182
 183 #endif /* CONFIG_DEBUG_FS */
 184
 185 static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
 186 {
 187         return container_of(chan, struct coh901318_chan, chan);
 188 }
 189
 190 static inline dma_addr_t
 191 cohc_dev_addr(struct coh901318_chan *cohc)
 192 {
 193         /* Runtime supplied address will take precedence */
 194         if (cohc->runtime_addr)
 195                 return cohc->runtime_addr;
 196         return cohc->base->platform->chan_conf[cohc->id].dev_addr;
 197 }
 198
 199 static inline const struct coh901318_params *
 200 cohc_chan_param(struct coh901318_chan *cohc)
 201 {
 202         return &cohc->base->platform->chan_conf[cohc->id].param;
 203 }
 204
 205 static inline const struct coh_dma_channel *
 206 cohc_chan_conf(struct coh901318_chan *cohc)
 207 {
 208         return &cohc->base->platform->chan_conf[cohc->id];
 209 }
 210
 211 static void enable_powersave(struct coh901318_chan *cohc)
 212 {
 213         unsigned long flags;
 214         struct powersave *pm = &cohc->base->pm;
 215
 216         spin_lock_irqsave(&pm->lock, flags);
 217
 218         pm->started_channels &= ~(1ULL << cohc->id);
 219
 220         if (!pm->started_channels) {
 221                 /* DMA no longer intends to access memory */
 222                 cohc->base->platform->access_memory_state(cohc->base->dev,
 223                                                           false);
 224         }
 225
 226         spin_unlock_irqrestore(&pm->lock, flags);
 227 }
 228 static void disable_powersave(struct coh901318_chan *cohc)
 229 {
 230         unsigned long flags;
 231         struct powersave *pm = &cohc->base->pm;
 232
 233         spin_lock_irqsave(&pm->lock, flags);
 234
 235         if (!pm->started_channels) {
 236                 /* DMA intends to access memory */
 237                 cohc->base->platform->access_memory_state(cohc->base->dev,
 238                                                           true);
 239         }
 240
 241         pm->started_channels |= (1ULL << cohc->id);
 242
 243         spin_unlock_irqrestore(&pm->lock, flags);
 244 }
 245
 246 static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
 247 {
 248         int channel = cohc->id;
 249         void __iomem *virtbase = cohc->base->virtbase;
 250
 251         writel(control,
 252                virtbase + COH901318_CX_CTRL +
 253                COH901318_CX_CTRL_SPACING * channel);
 254         return 0;
 255 }
 256
 257 static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
 258 {
 259         int channel = cohc->id;
 260         void __iomem *virtbase = cohc->base->virtbase;
 261
 262         writel(conf,
 263                virtbase + COH901318_CX_CFG +
 264                COH901318_CX_CFG_SPACING*channel);
 265         return 0;
 266 }
 267
 268
 269 static int coh901318_start(struct coh901318_chan *cohc)
 270 {
 271         u32 val;
 272         int channel = cohc->id;
 273         void __iomem *virtbase = cohc->base->virtbase;
 274
 275         disable_powersave(cohc);
 276
 277         val = readl(virtbase + COH901318_CX_CFG +
 278                     COH901318_CX_CFG_SPACING * channel);
 279
 280         /* Enable channel */
 281         val |= COH901318_CX_CFG_CH_ENABLE;
 282         writel(val, virtbase + COH901318_CX_CFG +
 283                COH901318_CX_CFG_SPACING * channel);
 284
 285         return 0;
 286 }
 287
 288 static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
 289                                       struct coh901318_lli *lli)
 290 {
 291         int channel = cohc->id;
 292         void __iomem *virtbase = cohc->base->virtbase;
 293
 294         BUG_ON(readl(virtbase + COH901318_CX_STAT +
 295                      COH901318_CX_STAT_SPACING*channel) &
 296                COH901318_CX_STAT_ACTIVE);
 297
 298         writel(lli->src_addr,
 299                virtbase + COH901318_CX_SRC_ADDR +
 300                COH901318_CX_SRC_ADDR_SPACING * channel);
 301
 302         writel(lli->dst_addr, virtbase +
 303                COH901318_CX_DST_ADDR +
 304                COH901318_CX_DST_ADDR_SPACING * channel);
 305
 306         writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
 307                COH901318_CX_LNK_ADDR_SPACING * channel);
 308
 309         writel(lli->control, virtbase + COH901318_CX_CTRL +
 310                COH901318_CX_CTRL_SPACING * channel);
 311
 312         return 0;
 313 }
 314
 315 static struct coh901318_desc *
 316 coh901318_desc_get(struct coh901318_chan *cohc)
 317 {
 318         struct coh901318_desc *desc;
 319
 320         if (list_empty(&cohc->free)) {
 321                 /* alloc new desc because we're out of used ones
 322                  * TODO: alloc a pile of descs instead of just one,
 323                  * avoid many small allocations.
 324                  */
 325                 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
 326                 if (desc == NULL)
 327                         goto out;
 328                 INIT_LIST_HEAD(&desc->node);
 329                 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
 330         } else {
 331                 /* Reuse an old desc. */
 332                 desc = list_first_entry(&cohc->free,
 333                                         struct coh901318_desc,
 334                                         node);
 335                 list_del(&desc->node);
 336                 /* Initialize it a bit so it's not insane */
 337                 desc->sg = NULL;
 338                 desc->sg_len = 0;
 339                 desc->desc.callback = NULL;
 340                 desc->desc.callback_param = NULL;
 341         }
 342
 343  out:
 344         return desc;
 345 }
 346
 347 static void
 348 coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
 349 {
 350         list_add_tail(&cohd->node, &cohc->free);
 351 }
 352
 353 /* call with irq lock held */
 354 static void
 355 coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
 356 {
 357         list_add_tail(&desc->node, &cohc->active);
 358 }
 359
 360 static struct coh901318_desc *
 361 coh901318_first_active_get(struct coh901318_chan *cohc)
 362 {
 363         struct coh901318_desc *d;
 364
 365         if (list_empty(&cohc->active))
 366                 return NULL;
 367
 368         d = list_first_entry(&cohc->active,
 369                              struct coh901318_desc,
 370                              node);
 371         return d;
 372 }
 373
 374 static void
 375 coh901318_desc_remove(struct coh901318_desc *cohd)
 376 {
 377         list_del(&cohd->node);
 378 }
 379
 380 static void
 381 coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
 382 {
 383         list_add_tail(&desc->node, &cohc->queue);
 384 }
 385
 386 static struct coh901318_desc *
 387 coh901318_first_queued(struct coh901318_chan *cohc)
 388 {
 389         struct coh901318_desc *d;
 390
 391         if (list_empty(&cohc->queue))
 392                 return NULL;
 393
 394         d = list_first_entry(&cohc->queue,
 395                              struct coh901318_desc,
 396                              node);
 397         return d;
 398 }
 399
 400 static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
 401 {
 402         struct coh901318_lli *lli = in_lli;
 403         u32 bytes = 0;
 404
 405         while (lli) {
 406                 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
 407                 lli = lli->virt_link_addr;
 408         }
 409         return bytes;
 410 }
 411
 412 /*
 413  * Get the number of bytes left to transfer on this channel,
 414  * it is unwise to call this before stopping the channel for
 415  * absolute measures, but for a rough guess you can still call
 416  * it.
 417  */
 418 static u32 coh901318_get_bytes_left(struct dma_chan *chan)
 419 {
 420         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 421         struct coh901318_desc *cohd;
 422         struct list_head *pos;
 423         unsigned long flags;
 424         u32 left = 0;
 425         int i = 0;
 426
 427         spin_lock_irqsave(&cohc->lock, flags);
 428
 429         /*
 430          * If there are many queued jobs, we iterate and add the
 431          * size of them all. We take a special look on the first
 432          * job though, since it is probably active.
 433          */
 434         list_for_each(pos, &cohc->active) {
 435                 /*
 436                  * The first job in the list will be working on the
 437                  * hardware. The job can be stopped but still active,
 438                  * so that the transfer counter is somewhere inside
 439                  * the buffer.
 440                  */
 441                 cohd = list_entry(pos, struct coh901318_desc, node);
 442
 443                 if (i == 0) {
 444                         struct coh901318_lli *lli;
 445                         dma_addr_t ladd;
 446
 447                         /* Read current transfer count value */
 448                         left = readl(cohc->base->virtbase +
 449                                      COH901318_CX_CTRL +
 450                                      COH901318_CX_CTRL_SPACING * cohc->id) &
 451                                 COH901318_CX_CTRL_TC_VALUE_MASK;
 452
 453                         /* See if the transfer is linked... */
 454                         ladd = readl(cohc->base->virtbase +
 455                                      COH901318_CX_LNK_ADDR +
 456                                      COH901318_CX_LNK_ADDR_SPACING *
 457                                      cohc->id) &
 458                                 ~COH901318_CX_LNK_LINK_IMMEDIATE;
 459                         /* Single transaction */
 460                         if (!ladd)
 461                                 continue;
 462
 463                         /*
 464                          * Linked transaction, follow the lli, find the
 465                          * currently processing lli, and proceed to the next
 466                          */
 467                         lli = cohd->lli;
 468                         while (lli && lli->link_addr != ladd)
 469                                 lli = lli->virt_link_addr;
 470
 471                         if (lli)
 472                                 lli = lli->virt_link_addr;
 473
 474                         /*
 475                          * Follow remaining lli links around to count the total
 476                          * number of bytes left
 477                          */
 478                         left += coh901318_get_bytes_in_lli(lli);
 479                 } else {
 480                         left += coh901318_get_bytes_in_lli(cohd->lli);
 481                 }
 482                 i++;
 483         }
 484
 485         /* Also count bytes in the queued jobs */
 486         list_for_each(pos, &cohc->queue) {
 487                 cohd = list_entry(pos, struct coh901318_desc, node);
 488                 left += coh901318_get_bytes_in_lli(cohd->lli);
 489         }
 490
 491         spin_unlock_irqrestore(&cohc->lock, flags);
 492
 493         return left;
 494 }
 495
 496 /*
 497  * Pauses a transfer without losing data. Enables power save.
 498  * Use this function in conjunction with coh901318_resume.
 499  */
 500 static void coh901318_pause(struct dma_chan *chan)
 501 {
 502         u32 val;
 503         unsigned long flags;
 504         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 505         int channel = cohc->id;
 506         void __iomem *virtbase = cohc->base->virtbase;
 507
 508         spin_lock_irqsave(&cohc->lock, flags);
 509
 510         /* Disable channel in HW */
 511         val = readl(virtbase + COH901318_CX_CFG +
 512                     COH901318_CX_CFG_SPACING * channel);
 513
 514         /* Stopping infinite transfer */
 515         if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
 516             (val & COH901318_CX_CFG_CH_ENABLE))
 517                 cohc->stopped = 1;
 518
 519
 520         val &= ~COH901318_CX_CFG_CH_ENABLE;
 521         /* Enable twice, HW bug work around */
 522         writel(val, virtbase + COH901318_CX_CFG +
 523                COH901318_CX_CFG_SPACING * channel);
 524         writel(val, virtbase + COH901318_CX_CFG +
 525                COH901318_CX_CFG_SPACING * channel);
 526
 527         /* Spin-wait for it to actually go inactive */
 528         while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
 529                      channel) & COH901318_CX_STAT_ACTIVE)
 530                 cpu_relax();
 531
 532         /* Check if we stopped an active job */
 533         if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
 534                    channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
 535                 cohc->stopped = 1;
 536
 537         enable_powersave(cohc);
 538
 539         spin_unlock_irqrestore(&cohc->lock, flags);
 540 }
 541
 542 /* Resumes a transfer that has been stopped via 300_dma_stop(..).
 543    Power save is handled.
 544 */
 545 static void coh901318_resume(struct dma_chan *chan)
 546 {
 547         u32 val;
 548         unsigned long flags;
 549         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 550         int channel = cohc->id;
 551
 552         spin_lock_irqsave(&cohc->lock, flags);
 553
 554         disable_powersave(cohc);
 555
 556         if (cohc->stopped) {
 557                 /* Enable channel in HW */
 558                 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
 559                             COH901318_CX_CFG_SPACING * channel);
 560
 561                 val |= COH901318_CX_CFG_CH_ENABLE;
 562
 563                 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
 564                        COH901318_CX_CFG_SPACING*channel);
 565
 566                 cohc->stopped = 0;
 567         }
 568
 569         spin_unlock_irqrestore(&cohc->lock, flags);
 570 }
 571
 572 bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
 573 {
 574         unsigned int ch_nr = (unsigned int) chan_id;
 575
 576         if (ch_nr == to_coh901318_chan(chan)->id)
 577                 return true;
 578
 579         return false;
 580 }
 581 EXPORT_SYMBOL(coh901318_filter_id);
 582
 583 /*
 584  * DMA channel allocation
 585  */
 586 static int coh901318_config(struct coh901318_chan *cohc,
 587                             struct coh901318_params *param)
 588 {
 589         unsigned long flags;
 590         const struct coh901318_params *p;
 591         int channel = cohc->id;
 592         void __iomem *virtbase = cohc->base->virtbase;
 593
 594         spin_lock_irqsave(&cohc->lock, flags);
 595
 596         if (param)
 597                 p = param;
 598         else
 599                 p = &cohc->base->platform->chan_conf[channel].param;
 600
 601         /* Clear any pending BE or TC interrupt */
 602         if (channel < 32) {
 603                 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
 604                 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
 605         } else {
 606                 writel(1 << (channel - 32), virtbase +
 607                        COH901318_BE_INT_CLEAR2);
 608                 writel(1 << (channel - 32), virtbase +
 609                        COH901318_TC_INT_CLEAR2);
 610         }
 611
 612         coh901318_set_conf(cohc, p->config);
 613         coh901318_set_ctrl(cohc, p->ctrl_lli_last);
 614
 615         spin_unlock_irqrestore(&cohc->lock, flags);
 616
 617         return 0;
 618 }
 619
 620 /* must lock when calling this function
 621  * start queued jobs, if any
 622  * TODO: start all queued jobs in one go
 623  *
 624  * Returns descriptor if queued job is started otherwise NULL.
 625  * If the queue is empty NULL is returned.
 626  */
 627 static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
 628 {
 629         struct coh901318_desc *cohd;
 630
 631         /*
 632          * start queued jobs, if any
 633          * TODO: transmit all queued jobs in one go
 634          */
 635         cohd = coh901318_first_queued(cohc);
 636
 637         if (cohd != NULL) {
 638                 /* Remove from queue */
 639                 coh901318_desc_remove(cohd);
 640                 /* initiate DMA job */
 641                 cohc->busy = 1;
 642
 643                 coh901318_desc_submit(cohc, cohd);
 644
 645                 /* Program the transaction head */
 646                 coh901318_set_conf(cohc, cohd->head_config);
 647                 coh901318_set_ctrl(cohc, cohd->head_ctrl);
 648                 coh901318_prep_linked_list(cohc, cohd->lli);
 649
 650                 /* start dma job on this channel */
 651                 coh901318_start(cohc);
 652
 653         }
 654
 655         return cohd;
 656 }
 657
 658 /*
 659  * This tasklet is called from the interrupt handler to
 660  * handle each descriptor (DMA job) that is sent to a channel.
 661  */
 662 static void dma_tasklet(unsigned long data)
 663 {
 664         struct coh901318_chan *cohc = (struct coh901318_chan *) data;
 665         struct coh901318_desc *cohd_fin;
 666         unsigned long flags;
 667         dma_async_tx_callback callback;
 668         void *callback_param;
 669
 670         dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
 671                  " nbr_active_done %ld\n", __func__,
 672                  cohc->id, cohc->nbr_active_done);
 673
 674         spin_lock_irqsave(&cohc->lock, flags);
 675
 676         /* get first active descriptor entry from list */
 677         cohd_fin = coh901318_first_active_get(cohc);
 678
 679         if (cohd_fin == NULL)
 680                 goto err;
 681
 682         /* locate callback to client */
 683         callback = cohd_fin->desc.callback;
 684         callback_param = cohd_fin->desc.callback_param;
 685
 686         /* sign this job as completed on the channel */
 687         dma_cookie_complete(&cohd_fin->desc);
 688
 689         /* release the lli allocation and remove the descriptor */
 690         coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
 691
 692         /* return desc to free-list */
 693         coh901318_desc_remove(cohd_fin);
 694         coh901318_desc_free(cohc, cohd_fin);
 695
 696         spin_unlock_irqrestore(&cohc->lock, flags);
 697
 698         /* Call the callback when we're done */
 699         if (callback)
 700                 callback(callback_param);
 701
 702         spin_lock_irqsave(&cohc->lock, flags);
 703
 704         /*
 705          * If another interrupt fired while the tasklet was scheduling,
 706          * we don't get called twice, so we have this number of active
 707          * counter that keep track of the number of IRQs expected to
 708          * be handled for this channel. If there happen to be more than
 709          * one IRQ to be ack:ed, we simply schedule this tasklet again.
 710          */
 711         cohc->nbr_active_done--;
 712         if (cohc->nbr_active_done) {
 713                 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
 714                         "came in while we were scheduling this tasklet\n");
 715                 if (cohc_chan_conf(cohc)->priority_high)
 716                         tasklet_hi_schedule(&cohc->tasklet);
 717                 else
 718                         tasklet_schedule(&cohc->tasklet);
 719         }
 720
 721         spin_unlock_irqrestore(&cohc->lock, flags);
 722
 723         return;
 724
 725  err:
 726         spin_unlock_irqrestore(&cohc->lock, flags);
 727         dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
 728 }
 729
 730
 731 /* called from interrupt context */
 732 static void dma_tc_handle(struct coh901318_chan *cohc)
 733 {
 734         /*
 735          * If the channel is not allocated, then we shouldn't have
 736          * any TC interrupts on it.
 737          */
 738         if (!cohc->allocated) {
 739                 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
 740                         "unallocated channel\n");
 741                 return;
 742         }
 743
 744         spin_lock(&cohc->lock);
 745
 746         /*
 747          * When we reach this point, at least one queue item
 748          * should have been moved over from cohc->queue to
 749          * cohc->active and run to completion, that is why we're
 750          * getting a terminal count interrupt is it not?
 751          * If you get this BUG() the most probable cause is that
 752          * the individual nodes in the lli chain have IRQ enabled,
 753          * so check your platform config for lli chain ctrl.
 754          */
 755         BUG_ON(list_empty(&cohc->active));
 756
 757         cohc->nbr_active_done++;
 758
 759         /*
 760          * This attempt to take a job from cohc->queue, put it
 761          * into cohc->active and start it.
 762          */
 763         if (coh901318_queue_start(cohc) == NULL)
 764                 cohc->busy = 0;
 765
 766         spin_unlock(&cohc->lock);
 767
 768         /*
 769          * This tasklet will remove items from cohc->active
 770          * and thus terminates them.
 771          */
 772         if (cohc_chan_conf(cohc)->priority_high)
 773                 tasklet_hi_schedule(&cohc->tasklet);
 774         else
 775                 tasklet_schedule(&cohc->tasklet);
 776 }
 777
 778
 779 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 780 {
 781         u32 status1;
 782         u32 status2;
 783         int i;
 784         int ch;
 785         struct coh901318_base *base  = dev_id;
 786         struct coh901318_chan *cohc;
 787         void __iomem *virtbase = base->virtbase;
 788
 789         status1 = readl(virtbase + COH901318_INT_STATUS1);
 790         status2 = readl(virtbase + COH901318_INT_STATUS2);
 791
 792         if (unlikely(status1 == 0 && status2 == 0)) {
 793                 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
 794                 return IRQ_HANDLED;
 795         }
 796
 797         /* TODO: consider handle IRQ in tasklet here to
 798          *       minimize interrupt latency */
 799
 800         /* Check the first 32 DMA channels for IRQ */
 801         while (status1) {
 802                 /* Find first bit set, return as a number. */
 803                 i = ffs(status1) - 1;
 804                 ch = i;
 805
 806                 cohc = &base->chans[ch];
 807                 spin_lock(&cohc->lock);
 808
 809                 /* Mask off this bit */
 810                 status1 &= ~(1 << i);
 811                 /* Check the individual channel bits */
 812                 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
 813                         dev_crit(COHC_2_DEV(cohc),
 814                                  "DMA bus error on channel %d!\n", ch);
 815                         BUG_ON(1);
 816                         /* Clear BE interrupt */
 817                         __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
 818                 } else {
 819                         /* Caused by TC, really? */
 820                         if (unlikely(!test_bit(i, virtbase +
 821                                                COH901318_TC_INT_STATUS1))) {
 822                                 dev_warn(COHC_2_DEV(cohc),
 823                                          "ignoring interrupt not caused by terminal count on channel %d\n", ch);
 824                                 /* Clear TC interrupt */
 825                                 BUG_ON(1);
 826                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
 827                         } else {
 828                                 /* Enable powersave if transfer has finished */
 829                                 if (!(readl(virtbase + COH901318_CX_STAT +
 830                                             COH901318_CX_STAT_SPACING*ch) &
 831                                       COH901318_CX_STAT_ENABLED)) {
 832                                         enable_powersave(cohc);
 833                                 }
 834
 835                                 /* Must clear TC interrupt before calling
 836                                  * dma_tc_handle
 837                                  * in case tc_handle initiate a new dma job
 838                                  */
 839                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
 840
 841                                 dma_tc_handle(cohc);
 842                         }
 843                 }
 844                 spin_unlock(&cohc->lock);
 845         }
 846
 847         /* Check the remaining 32 DMA channels for IRQ */
 848         while (status2) {
 849                 /* Find first bit set, return as a number. */
 850                 i = ffs(status2) - 1;
 851                 ch = i + 32;
 852                 cohc = &base->chans[ch];
 853                 spin_lock(&cohc->lock);
 854
 855                 /* Mask off this bit */
 856                 status2 &= ~(1 << i);
 857                 /* Check the individual channel bits */
 858                 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
 859                         dev_crit(COHC_2_DEV(cohc),
 860                                  "DMA bus error on channel %d!\n", ch);
 861                         /* Clear BE interrupt */
 862                         BUG_ON(1);
 863                         __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
 864                 } else {
 865                         /* Caused by TC, really? */
 866                         if (unlikely(!test_bit(i, virtbase +
 867                                                COH901318_TC_INT_STATUS2))) {
 868                                 dev_warn(COHC_2_DEV(cohc),
 869                                          "ignoring interrupt not caused by terminal count on channel %d\n", ch);
 870                                 /* Clear TC interrupt */
 871                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
 872                                 BUG_ON(1);
 873                         } else {
 874                                 /* Enable powersave if transfer has finished */
 875                                 if (!(readl(virtbase + COH901318_CX_STAT +
 876                                             COH901318_CX_STAT_SPACING*ch) &
 877                                       COH901318_CX_STAT_ENABLED)) {
 878                                         enable_powersave(cohc);
 879                                 }
 880                                 /* Must clear TC interrupt before calling
 881                                  * dma_tc_handle
 882                                  * in case tc_handle initiate a new dma job
 883                                  */
 884                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
 885
 886                                 dma_tc_handle(cohc);
 887                         }
 888                 }
 889                 spin_unlock(&cohc->lock);
 890         }
 891
 892         return IRQ_HANDLED;
 893 }
 894
 895 static int coh901318_alloc_chan_resources(struct dma_chan *chan)
 896 {
 897         struct coh901318_chan   *cohc = to_coh901318_chan(chan);
 898         unsigned long flags;
 899
 900         dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
 901                  __func__, cohc->id);
 902
 903         if (chan->client_count > 1)
 904                 return -EBUSY;
 905
 906         spin_lock_irqsave(&cohc->lock, flags);
 907
 908         coh901318_config(cohc, NULL);
 909
 910         cohc->allocated = 1;
 911         dma_cookie_init(chan);
 912
 913         spin_unlock_irqrestore(&cohc->lock, flags);
 914
 915         return 1;
 916 }
 917
 918 static void
 919 coh901318_free_chan_resources(struct dma_chan *chan)
 920 {
 921         struct coh901318_chan   *cohc = to_coh901318_chan(chan);
 922         int channel = cohc->id;
 923         unsigned long flags;
 924
 925         spin_lock_irqsave(&cohc->lock, flags);
 926
 927         /* Disable HW */
 928         writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
 929                COH901318_CX_CFG_SPACING*channel);
 930         writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
 931                COH901318_CX_CTRL_SPACING*channel);
 932
 933         cohc->allocated = 0;
 934
 935         spin_unlock_irqrestore(&cohc->lock, flags);
 936
 937         chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
 938 }
 939
 940
 941 static dma_cookie_t
 942 coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
 943 {
 944         struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
 945                                                    desc);
 946         struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
 947         unsigned long flags;
 948         dma_cookie_t cookie;
 949
 950         spin_lock_irqsave(&cohc->lock, flags);
 951         cookie = dma_cookie_assign(tx);
 952
 953         coh901318_desc_queue(cohc, cohd);
 954
 955         spin_unlock_irqrestore(&cohc->lock, flags);
 956
 957         return cookie;
 958 }
 959
 960 static struct dma_async_tx_descriptor *
 961 coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 962                       size_t size, unsigned long flags)
 963 {
 964         struct coh901318_lli *lli;
 965         struct coh901318_desc *cohd;
 966         unsigned long flg;
 967         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 968         int lli_len;
 969         u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
 970         int ret;
 971
 972         spin_lock_irqsave(&cohc->lock, flg);
 973
 974         dev_vdbg(COHC_2_DEV(cohc),
 975                  "[%s] channel %d src 0x%x dest 0x%x size %d\n",
 976                  __func__, cohc->id, src, dest, size);
 977
 978         if (flags & DMA_PREP_INTERRUPT)
 979                 /* Trigger interrupt after last lli */
 980                 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
 981
 982         lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
 983         if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
 984                 lli_len++;
 985
 986         lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
 987
 988         if (lli == NULL)
 989                 goto err;
 990
 991         ret = coh901318_lli_fill_memcpy(
 992                 &cohc->base->pool, lli, src, size, dest,
 993                 cohc_chan_param(cohc)->ctrl_lli_chained,
 994                 ctrl_last);
 995         if (ret)
 996                 goto err;
 997
 998         COH_DBG(coh901318_list_print(cohc, lli));
 999
1000         /* Pick a descriptor to handle this transfer */
1001         cohd = coh901318_desc_get(cohc);
1002         cohd->lli = lli;
1003         cohd->flags = flags;
1004         cohd->desc.tx_submit = coh901318_tx_submit;
1005
1006         spin_unlock_irqrestore(&cohc->lock, flg);
1007
1008         return &cohd->desc;
1009  err:
1010         spin_unlock_irqrestore(&cohc->lock, flg);
1011         return NULL;
1012 }
1013
1014 static struct dma_async_tx_descriptor *
1015 coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1016                         unsigned int sg_len, enum dma_transfer_direction direction,
1017                         unsigned long flags, void *context)
1018 {
1019         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1020         struct coh901318_lli *lli;
1021         struct coh901318_desc *cohd;
1022         const struct coh901318_params *params;
1023         struct scatterlist *sg;
1024         int len = 0;
1025         int size;
1026         int i;
1027         u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
1028         u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
1029         u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
1030         u32 config;
1031         unsigned long flg;
1032         int ret;
1033
1034         if (!sgl)
1035                 goto out;
1036         if (sgl->length == 0)
1037                 goto out;
1038
1039         spin_lock_irqsave(&cohc->lock, flg);
1040
1041         dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
1042                  __func__, sg_len, direction);
1043
1044         if (flags & DMA_PREP_INTERRUPT)
1045                 /* Trigger interrupt after last lli */
1046                 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
1047
1048         params = cohc_chan_param(cohc);
1049         config = params->config;
1050         /*
1051          * Add runtime-specific control on top, make
1052          * sure the bits you set per peripheral channel are
1053          * cleared in the default config from the platform.
1054          */
1055         ctrl_chained |= cohc->runtime_ctrl;
1056         ctrl_last |= cohc->runtime_ctrl;
1057         ctrl |= cohc->runtime_ctrl;
1058
1059         if (direction == DMA_MEM_TO_DEV) {
1060                 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
1061                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
1062
1063                 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
1064                 ctrl_chained |= tx_flags;
1065                 ctrl_last |= tx_flags;
1066                 ctrl |= tx_flags;
1067         } else if (direction == DMA_DEV_TO_MEM) {
1068                 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
1069                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
1070
1071                 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
1072                 ctrl_chained |= rx_flags;
1073                 ctrl_last |= rx_flags;
1074                 ctrl |= rx_flags;
1075         } else
1076                 goto err_direction;
1077
1078         /* The dma only supports transmitting packages up to
1079          * MAX_DMA_PACKET_SIZE. Calculate to total number of
1080          * dma elemts required to send the entire sg list
1081          */
1082         for_each_sg(sgl, sg, sg_len, i) {
1083                 unsigned int factor;
1084                 size = sg_dma_len(sg);
1085
1086                 if (size <= MAX_DMA_PACKET_SIZE) {
1087                         len++;
1088                         continue;
1089                 }
1090
1091                 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
1092                 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
1093                         factor++;
1094
1095                 len += factor;
1096         }
1097
1098         pr_debug("Allocate %d lli:s for this transfer\n", len);
1099         lli = coh901318_lli_alloc(&cohc->base->pool, len);
1100
1101         if (lli == NULL)
1102                 goto err_dma_alloc;
1103
1104         /* initiate allocated lli list */
1105         ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
1106                                     cohc_dev_addr(cohc),
1107                                     ctrl_chained,
1108                                     ctrl,
1109                                     ctrl_last,
1110                                     direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
1111         if (ret)
1112                 goto err_lli_fill;
1113
1114
1115         COH_DBG(coh901318_list_print(cohc, lli));
1116
1117         /* Pick a descriptor to handle this transfer */
1118         cohd = coh901318_desc_get(cohc);
1119         cohd->head_config = config;
1120         /*
1121          * Set the default head ctrl for the channel to the one from the
1122          * lli, things may have changed due to odd buffer alignment
1123          * etc.
1124          */
1125         cohd->head_ctrl = lli->control;
1126         cohd->dir = direction;
1127         cohd->flags = flags;
1128         cohd->desc.tx_submit = coh901318_tx_submit;
1129         cohd->lli = lli;
1130
1131         spin_unlock_irqrestore(&cohc->lock, flg);
1132
1133         return &cohd->desc;
1134  err_lli_fill:
1135  err_dma_alloc:
1136  err_direction:
1137         spin_unlock_irqrestore(&cohc->lock, flg);
1138  out:
1139         return NULL;
1140 }
1141
1142 static enum dma_status
1143 coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1144                  struct dma_tx_state *txstate)
1145 {
1146         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1147         enum dma_status ret;
1148
1149         ret = dma_cookie_status(chan, cookie, txstate);
1150         /* FIXME: should be conditional on ret != DMA_SUCCESS? */
1151         dma_set_residue(txstate, coh901318_get_bytes_left(chan));
1152
1153         if (ret == DMA_IN_PROGRESS && cohc->stopped)
1154                 ret = DMA_PAUSED;
1155
1156         return ret;
1157 }
1158
1159 static void
1160 coh901318_issue_pending(struct dma_chan *chan)
1161 {
1162         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1163         unsigned long flags;
1164
1165         spin_lock_irqsave(&cohc->lock, flags);
1166
1167         /*
1168          * Busy means that pending jobs are already being processed,
1169          * and then there is no point in starting the queue: the
1170          * terminal count interrupt on the channel will take the next
1171          * job on the queue and execute it anyway.
1172          */
1173         if (!cohc->busy)
1174                 coh901318_queue_start(cohc);
1175
1176         spin_unlock_irqrestore(&cohc->lock, flags);
1177 }
1178
1179 /*
1180  * Here we wrap in the runtime dma control interface
1181  */
1182 struct burst_table {
1183         int burst_8bit;
1184         int burst_16bit;
1185         int burst_32bit;
1186         u32 reg;
1187 };
1188
1189 static const struct burst_table burst_sizes[] = {
1190         {
1191                 .burst_8bit = 64,
1192                 .burst_16bit = 32,
1193                 .burst_32bit = 16,
1194                 .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
1195         },
1196         {
1197                 .burst_8bit = 48,
1198                 .burst_16bit = 24,
1199                 .burst_32bit = 12,
1200                 .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
1201         },
1202         {
1203                 .burst_8bit = 32,
1204                 .burst_16bit = 16,
1205                 .burst_32bit = 8,
1206                 .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
1207         },
1208         {
1209                 .burst_8bit = 16,
1210                 .burst_16bit = 8,
1211                 .burst_32bit = 4,
1212                 .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
1213         },
1214         {
1215                 .burst_8bit = 8,
1216                 .burst_16bit = 4,
1217                 .burst_32bit = 2,
1218                 .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
1219         },
1220         {
1221                 .burst_8bit = 4,
1222                 .burst_16bit = 2,
1223                 .burst_32bit = 1,
1224                 .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
1225         },
1226         {
1227                 .burst_8bit = 2,
1228                 .burst_16bit = 1,
1229                 .burst_32bit = 0,
1230                 .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
1231         },
1232         {
1233                 .burst_8bit = 1,
1234                 .burst_16bit = 0,
1235                 .burst_32bit = 0,
1236                 .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
1237         },
1238 };
1239
1240 static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
1241                         struct dma_slave_config *config)
1242 {
1243         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1244         dma_addr_t addr;
1245         enum dma_slave_buswidth addr_width;
1246         u32 maxburst;
1247         u32 runtime_ctrl = 0;
1248         int i = 0;
1249
1250         /* We only support mem to per or per to mem transfers */
1251         if (config->direction == DMA_DEV_TO_MEM) {
1252                 addr = config->src_addr;
1253                 addr_width = config->src_addr_width;
1254                 maxburst = config->src_maxburst;
1255         } else if (config->direction == DMA_MEM_TO_DEV) {
1256                 addr = config->dst_addr;
1257                 addr_width = config->dst_addr_width;
1258                 maxburst = config->dst_maxburst;
1259         } else {
1260                 dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
1261                 return;
1262         }
1263
1264         dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
1265                 addr_width);
1266         switch (addr_width)  {
1267         case DMA_SLAVE_BUSWIDTH_1_BYTE:
1268                 runtime_ctrl |=
1269                         COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
1270                         COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
1271
1272                 while (i < ARRAY_SIZE(burst_sizes)) {
1273                         if (burst_sizes[i].burst_8bit <= maxburst)
1274                                 break;
1275                         i++;
1276                 }
1277
1278                 break;
1279         case DMA_SLAVE_BUSWIDTH_2_BYTES:
1280                 runtime_ctrl |=
1281                         COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
1282                         COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
1283
1284                 while (i < ARRAY_SIZE(burst_sizes)) {
1285                         if (burst_sizes[i].burst_16bit <= maxburst)
1286                                 break;
1287                         i++;
1288                 }
1289
1290                 break;
1291         case DMA_SLAVE_BUSWIDTH_4_BYTES:
1292                 /* Direction doesn't matter here, it's 32/32 bits */
1293                 runtime_ctrl |=
1294                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1295                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
1296
1297                 while (i < ARRAY_SIZE(burst_sizes)) {
1298                         if (burst_sizes[i].burst_32bit <= maxburst)
1299                                 break;
1300                         i++;
1301                 }
1302
1303                 break;
1304         default:
1305                 dev_err(COHC_2_DEV(cohc),
1306                         "bad runtimeconfig: alien address width\n");
1307                 return;
1308         }
1309
1310         runtime_ctrl |= burst_sizes[i].reg;
1311         dev_dbg(COHC_2_DEV(cohc),
1312                 "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
1313                 burst_sizes[i].burst_8bit, addr_width, maxburst);
1314
1315         cohc->runtime_addr = addr;
1316         cohc->runtime_ctrl = runtime_ctrl;
1317 }
1318
1319 static int
1320 coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1321                   unsigned long arg)
1322 {
1323         unsigned long flags;
1324         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1325         struct coh901318_desc *cohd;
1326         void __iomem *virtbase = cohc->base->virtbase;
1327
1328         if (cmd == DMA_SLAVE_CONFIG) {
1329                 struct dma_slave_config *config =
1330                         (struct dma_slave_config *) arg;
1331
1332                 coh901318_dma_set_runtimeconfig(chan, config);
1333                 return 0;
1334           }
1335
1336         if (cmd == DMA_PAUSE) {
1337                 coh901318_pause(chan);
1338                 return 0;
1339         }
1340
1341         if (cmd == DMA_RESUME) {
1342                 coh901318_resume(chan);
1343                 return 0;
1344         }
1345
1346         if (cmd != DMA_TERMINATE_ALL)
1347                 return -ENXIO;
1348
1349         /* The remainder of this function terminates the transfer */
1350         coh901318_pause(chan);
1351         spin_lock_irqsave(&cohc->lock, flags);
1352
1353         /* Clear any pending BE or TC interrupt */
1354         if (cohc->id < 32) {
1355                 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
1356                 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
1357         } else {
1358                 writel(1 << (cohc->id - 32), virtbase +
1359                        COH901318_BE_INT_CLEAR2);
1360                 writel(1 << (cohc->id - 32), virtbase +
1361                        COH901318_TC_INT_CLEAR2);
1362         }
1363
1364         enable_powersave(cohc);
1365
1366         while ((cohd = coh901318_first_active_get(cohc))) {
1367                 /* release the lli allocation*/
1368                 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1369
1370                 /* return desc to free-list */
1371                 coh901318_desc_remove(cohd);
1372                 coh901318_desc_free(cohc, cohd);
1373         }
1374
1375         while ((cohd = coh901318_first_queued(cohc))) {
1376                 /* release the lli allocation*/
1377                 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1378
1379                 /* return desc to free-list */
1380                 coh901318_desc_remove(cohd);
1381                 coh901318_desc_free(cohc, cohd);
1382         }
1383
1384
1385         cohc->nbr_active_done = 0;
1386         cohc->busy = 0;
1387
1388         spin_unlock_irqrestore(&cohc->lock, flags);
1389
1390         return 0;
1391 }
1392
1393 void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
1394                          struct coh901318_base *base)
1395 {
1396         int chans_i;
1397         int i = 0;
1398         struct coh901318_chan *cohc;
1399
1400         INIT_LIST_HEAD(&dma->channels);
1401
1402         for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
1403                 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
1404                         cohc = &base->chans[i];
1405
1406                         cohc->base = base;
1407                         cohc->chan.device = dma;
1408                         cohc->id = i;
1409
1410                         /* TODO: do we really need this lock if only one
1411                          * client is connected to each channel?
1412                          */
1413
1414                         spin_lock_init(&cohc->lock);
1415
1416                         cohc->nbr_active_done = 0;
1417                         cohc->busy = 0;
1418                         INIT_LIST_HEAD(&cohc->free);
1419                         INIT_LIST_HEAD(&cohc->active);
1420                         INIT_LIST_HEAD(&cohc->queue);
1421
1422                         tasklet_init(&cohc->tasklet, dma_tasklet,
1423                                      (unsigned long) cohc);
1424
1425                         list_add_tail(&cohc->chan.device_node,
1426                                       &dma->channels);
1427                 }
1428         }
1429 }
1430
1431 static int __init coh901318_probe(struct platform_device *pdev)
1432 {
1433         int err = 0;
1434         struct coh901318_platform *pdata;
1435         struct coh901318_base *base;
1436         int irq;
1437         struct resource *io;
1438
1439         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1440         if (!io)
1441                 goto err_get_resource;
1442
1443         /* Map DMA controller registers to virtual memory */
1444         if (request_mem_region(io->start,
1445                                resource_size(io),
1446                                pdev->dev.driver->name) == NULL) {
1447                 err = -EBUSY;
1448                 goto err_request_mem;
1449         }
1450
1451         pdata = pdev->dev.platform_data;
1452         if (!pdata)
1453                 goto err_no_platformdata;
1454
1455         base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) +
1456                        pdata->max_channels *
1457                        sizeof(struct coh901318_chan),
1458                        GFP_KERNEL);
1459         if (!base)
1460                 goto err_alloc_coh_dma_channels;
1461
1462         base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
1463
1464         base->virtbase = ioremap(io->start, resource_size(io));
1465         if (!base->virtbase) {
1466                 err = -ENOMEM;
1467                 goto err_no_ioremap;
1468         }
1469
1470         base->dev = &pdev->dev;
1471         base->platform = pdata;
1472         spin_lock_init(&base->pm.lock);
1473         base->pm.started_channels = 0;
1474
1475         COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
1476
1477         platform_set_drvdata(pdev, base);
1478
1479         irq = platform_get_irq(pdev, 0);
1480         if (irq < 0)
1481                 goto err_no_irq;
1482
1483         err = request_irq(irq, dma_irq_handler, IRQF_DISABLED,
1484                           "coh901318", base);
1485         if (err) {
1486                 dev_crit(&pdev->dev,
1487                          "Cannot allocate IRQ for DMA controller!\n");
1488                 goto err_request_irq;
1489         }
1490
1491         err = coh901318_pool_create(&base->pool, &pdev->dev,
1492                                     sizeof(struct coh901318_lli),
1493                                     32);
1494         if (err)
1495                 goto err_pool_create;
1496
1497         /* init channels for device transfers */
1498         coh901318_base_init(&base->dma_slave,  base->platform->chans_slave,
1499                             base);
1500
1501         dma_cap_zero(base->dma_slave.cap_mask);
1502         dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
1503
1504         base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1505         base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
1506         base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
1507         base->dma_slave.device_tx_status = coh901318_tx_status;
1508         base->dma_slave.device_issue_pending = coh901318_issue_pending;
1509         base->dma_slave.device_control = coh901318_control;
1510         base->dma_slave.dev = &pdev->dev;
1511
1512         err = dma_async_device_register(&base->dma_slave);
1513
1514         if (err)
1515                 goto err_register_slave;
1516
1517         /* init channels for memcpy */
1518         coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy,
1519                             base);
1520
1521         dma_cap_zero(base->dma_memcpy.cap_mask);
1522         dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
1523
1524         base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1525         base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
1526         base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
1527         base->dma_memcpy.device_tx_status = coh901318_tx_status;
1528         base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
1529         base->dma_memcpy.device_control = coh901318_control;
1530         base->dma_memcpy.dev = &pdev->dev;
1531         /*
1532          * This controller can only access address at even 32bit boundaries,
1533          * i.e. 2^2
1534          */
1535         base->dma_memcpy.copy_align = 2;
1536         err = dma_async_device_register(&base->dma_memcpy);
1537
1538         if (err)
1539                 goto err_register_memcpy;
1540
1541         dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
1542                 (u32) base->virtbase);
1543
1544         return err;
1545
1546  err_register_memcpy:
1547         dma_async_device_unregister(&base->dma_slave);
1548  err_register_slave:
1549         coh901318_pool_destroy(&base->pool);
1550  err_pool_create:
1551         free_irq(platform_get_irq(pdev, 0), base);
1552  err_request_irq:
1553  err_no_irq:
1554         iounmap(base->virtbase);
1555  err_no_ioremap:
1556         kfree(base);
1557  err_alloc_coh_dma_channels:
1558  err_no_platformdata:
1559         release_mem_region(pdev->resource->start,
1560                            resource_size(pdev->resource));
1561  err_request_mem:
1562  err_get_resource:
1563         return err;
1564 }
1565
1566 static int __exit coh901318_remove(struct platform_device *pdev)
1567 {
1568         struct coh901318_base *base = platform_get_drvdata(pdev);
1569
1570         dma_async_device_unregister(&base->dma_memcpy);
1571         dma_async_device_unregister(&base->dma_slave);
1572         coh901318_pool_destroy(&base->pool);
1573         free_irq(platform_get_irq(pdev, 0), base);
1574         iounmap(base->virtbase);
1575         kfree(base);
1576         release_mem_region(pdev->resource->start,
1577                            resource_size(pdev->resource));
1578         return 0;
1579 }
1580
1581
1582 static struct platform_driver coh901318_driver = {
1583         .remove = __exit_p(coh901318_remove),
1584         .driver = {
1585                 .name   = "coh901318",
1586         },
1587 };
1588
1589 int __init coh901318_init(void)
1590 {
1591         return platform_driver_probe(&coh901318_driver, coh901318_probe);
1592 }
1593 subsys_initcall(coh901318_init);
1594
1595 void __exit coh901318_exit(void)
1596 {
1597         platform_driver_unregister(&coh901318_driver);
1598 }
1599 module_exit(coh901318_exit);
1600
1601 MODULE_LICENSE("GPL");
1602 MODULE_AUTHOR("Per Friden");