2 * wanXL serial card driver for Linux
5 * Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License
9 * as published by the Free Software Foundation.
12 * - Only DTE (external clock) support with NRZ and NRZI encodings
13 * - wanXL100 will require minor driver modifications, no access to hw
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/slab.h>
19 #include <linux/sched.h>
20 #include <linux/types.h>
21 #include <linux/fcntl.h>
22 #include <linux/string.h>
23 #include <linux/errno.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/netdevice.h>
27 #include <linux/hdlc.h>
28 #include <linux/pci.h>
30 #include <asm/delay.h>
34 static const char* version = "wanXL serial card driver version: 0.47";
36 #define PLX_CTL_RESET 0x40000000 /* adapter reset */
41 /* MAILBOX #1 - PUTS COMMANDS */
42 #define MBX1_CMD_ABORTJ 0x85000000 /* Abort and Jump */
43 #ifdef __LITTLE_ENDIAN
44 #define MBX1_CMD_BSWAP 0x8C000001 /* little-endian Byte Swap Mode */
46 #define MBX1_CMD_BSWAP 0x8C000000 /* big-endian Byte Swap Mode */
49 /* MAILBOX #2 - DRAM SIZE */
50 #define MBX2_MEMSZ_MASK 0xFFFF0000 /* PUTS Memory Size Register mask */
54 struct net_device *dev;
56 spinlock_t lock; /* for wanxl_xmit */
57 int node; /* physical port #0 - 3 */
58 unsigned int clock_type;
60 struct sk_buff *tx_skbs[TX_BUFFERS];
65 desc_t rx_descs[RX_QUEUE_LENGTH];
66 port_status_t port_status[4];
70 typedef struct card_t {
71 int n_ports; /* 1, 2 or 4 ports */
74 u8 *plx; /* PLX PCI9060 virtual base address */
75 struct pci_dev *pdev; /* for pdev->slot_name */
78 struct sk_buff *rx_skbs[RX_QUEUE_LENGTH];
79 card_status_t *status; /* shared between host and card */
80 dma_addr_t status_address;
86 static inline port_t* dev_to_port(struct net_device *dev)
88 return (port_t *)dev_to_hdlc(dev)->priv;
92 static inline struct net_device *port_to_dev(port_t* port)
98 static inline const char* port_name(port_t *port)
100 return port_to_dev(port)->name;
104 static inline const char* card_name(struct pci_dev *pdev)
106 return pdev->slot_name;
110 static inline port_status_t* get_status(port_t *port)
112 return &port->card->status->port_status[port->node];
117 static inline dma_addr_t pci_map_single_debug(struct pci_dev *pdev, void *ptr,
118 size_t size, int direction)
120 dma_addr_t addr = pci_map_single(pdev, ptr, size, direction);
121 if (addr + size > 0x100000000LL)
122 printk(KERN_CRIT "wanXL %s: pci_map_single() returned memory"
123 " at 0x%LX!\n", card_name(pdev),
124 (unsigned long long)addr);
128 #undef pci_map_single
129 #define pci_map_single pci_map_single_debug
133 /* Cable and/or personality module change interrupt service */
134 static inline void wanxl_cable_intr(port_t *port)
136 u32 value = get_status(port)->cable;
138 const char *cable, *pm, *dte = "", *dsr = "", *dcd = "";
140 switch(value & 0x7) {
141 case STATUS_CABLE_V35: cable = "V.35"; break;
142 case STATUS_CABLE_X21: cable = "X.21"; break;
143 case STATUS_CABLE_V24: cable = "V.24"; break;
144 case STATUS_CABLE_EIA530: cable = "EIA530"; break;
145 case STATUS_CABLE_NONE: cable = "no"; break;
146 default: cable = "invalid";
149 switch((value >> STATUS_CABLE_PM_SHIFT) & 0x7) {
150 case STATUS_CABLE_V35: pm = "V.35"; break;
151 case STATUS_CABLE_X21: pm = "X.21"; break;
152 case STATUS_CABLE_V24: pm = "V.24"; break;
153 case STATUS_CABLE_EIA530: pm = "EIA530"; break;
154 case STATUS_CABLE_NONE: pm = "no personality"; valid = 0; break;
155 default: pm = "invalid personality"; valid = 0;
159 if ((value & 7) == ((value >> STATUS_CABLE_PM_SHIFT) & 7)) {
160 dsr = (value & STATUS_CABLE_DSR) ? ", DSR ON" :
162 dcd = (value & STATUS_CABLE_DCD) ? ", carrier ON" :
165 dte = (value & STATUS_CABLE_DCE) ? " DCE" : " DTE";
167 printk(KERN_INFO "%s: %s%s module, %s cable%s%s\n",
168 port_name(port), pm, dte, cable, dsr, dcd);
170 hdlc_set_carrier(value & STATUS_CABLE_DCD, port_to_dev(port));
175 /* Transmit complete interrupt service */
176 static inline void wanxl_tx_intr(port_t *port)
178 struct net_device *dev = port_to_dev(port);
179 struct net_device_stats *stats = hdlc_stats(dev);
181 desc_t *desc = &get_status(port)->tx_descs[port->tx_in];
182 struct sk_buff *skb = port->tx_skbs[port->tx_in];
184 switch (desc->stat) {
187 netif_wake_queue(dev);
190 case PACKET_UNDERRUN:
192 stats->tx_fifo_errors++;
197 stats->tx_bytes += skb->len;
199 desc->stat = PACKET_EMPTY; /* Free descriptor */
200 pci_unmap_single(port->card->pdev, desc->address, skb->len,
202 dev_kfree_skb_irq(skb);
203 port->tx_in = (port->tx_in + 1) % TX_BUFFERS;
209 /* Receive complete interrupt service */
210 static inline void wanxl_rx_intr(card_t *card)
213 while(desc = &card->status->rx_descs[card->rx_in],
214 desc->stat != PACKET_EMPTY) {
215 struct sk_buff *skb = card->rx_skbs[card->rx_in];
216 port_t *port = card->ports[desc->stat & PACKET_PORT_MASK];
217 struct net_device *dev = port_to_dev(port);
218 struct net_device_stats *stats = hdlc_stats(dev);
220 if ((desc->stat & PACKET_PORT_MASK) > card->n_ports)
221 printk(KERN_CRIT "wanXL %s: received packet for"
222 " nonexistent port\n", card_name(card->pdev));
228 pci_unmap_single(card->pdev, desc->address,
229 BUFFER_LENGTH, PCI_DMA_FROMDEVICE);
230 skb_put(skb, desc->length);
233 printk(KERN_DEBUG "%s RX(%i):", port_name(port),
238 stats->rx_bytes += skb->len;
239 skb->mac.raw = skb->data;
241 dev->last_rx = jiffies;
242 skb->protocol = hdlc_type_trans(skb, dev);
248 skb = dev_alloc_skb(BUFFER_LENGTH);
249 desc->address = skb ?
250 pci_map_single(card->pdev, skb->data,
252 PCI_DMA_FROMDEVICE) : 0;
253 card->rx_skbs[card->rx_in] = skb;
255 desc->stat = PACKET_EMPTY; /* Free descriptor */
256 card->rx_in = (card->rx_in + 1) % RX_QUEUE_LENGTH;
262 static irqreturn_t wanxl_intr(int irq, void* dev_id, struct pt_regs *regs)
264 card_t *card = dev_id;
270 while((stat = readl(card->plx + PLX_DOORBELL_FROM_CARD)) != 0) {
272 writel(stat, card->plx + PLX_DOORBELL_FROM_CARD);
274 for (i = 0; i < card->n_ports; i++) {
275 if (stat & (1 << (DOORBELL_FROM_CARD_TX_0 + i)))
276 wanxl_tx_intr(card->ports[i]);
277 if (stat & (1 << (DOORBELL_FROM_CARD_CABLE_0 + i)))
278 wanxl_cable_intr(card->ports[i]);
280 if (stat & (1 << DOORBELL_FROM_CARD_RX))
284 return IRQ_RETVAL(handled);
289 static int wanxl_xmit(struct sk_buff *skb, struct net_device *dev)
291 port_t *port = dev_to_port(dev);
294 spin_lock(&port->lock);
296 desc = &get_status(port)->tx_descs[port->tx_out];
297 if (desc->stat != PACKET_EMPTY) {
298 /* should never happen - previous xmit should stop queue */
300 printk(KERN_DEBUG "%s: transmitter buffer full\n",
303 netif_stop_queue(dev);
304 spin_unlock_irq(&port->lock);
305 return 1; /* request packet to be queued */
309 printk(KERN_DEBUG "%s TX(%i):", port_name(port), skb->len);
313 port->tx_skbs[port->tx_out] = skb;
314 desc->address = pci_map_single(port->card->pdev, skb->data, skb->len,
316 desc->length = skb->len;
317 desc->stat = PACKET_FULL;
318 writel(1 << (DOORBELL_TO_CARD_TX_0 + port->node),
319 port->card->plx + PLX_DOORBELL_TO_CARD);
320 dev->trans_start = jiffies;
322 port->tx_out = (port->tx_out + 1) % TX_BUFFERS;
324 if (get_status(port)->tx_descs[port->tx_out].stat != PACKET_EMPTY) {
325 netif_stop_queue(dev);
327 printk(KERN_DEBUG "%s: transmitter buffer full\n",
332 spin_unlock(&port->lock);
338 static int wanxl_attach(struct net_device *dev, unsigned short encoding,
339 unsigned short parity)
341 port_t *port = dev_to_port(dev);
343 if (encoding != ENCODING_NRZ &&
344 encoding != ENCODING_NRZI)
347 if (parity != PARITY_NONE &&
348 parity != PARITY_CRC32_PR1_CCITT &&
349 parity != PARITY_CRC16_PR1_CCITT &&
350 parity != PARITY_CRC32_PR0_CCITT &&
351 parity != PARITY_CRC16_PR0_CCITT)
354 get_status(port)->encoding = encoding;
355 get_status(port)->parity = parity;
361 static int wanxl_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
363 const size_t size = sizeof(sync_serial_settings);
364 sync_serial_settings line;
365 port_t *port = dev_to_port(dev);
367 if (cmd != SIOCWANDEV)
368 return hdlc_ioctl(dev, ifr, cmd);
370 switch (ifr->ifr_settings.type) {
372 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
373 if (ifr->ifr_settings.size < size) {
374 ifr->ifr_settings.size = size; /* data size wanted */
377 line.clock_type = get_status(port)->clocking;
381 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &line, size))
385 case IF_IFACE_SYNC_SERIAL:
386 if (!capable(CAP_NET_ADMIN))
388 if (dev->flags & IFF_UP)
391 if (copy_from_user(&line, ifr->ifr_settings.ifs_ifsu.sync,
395 if (line.clock_type != CLOCK_EXT &&
396 line.clock_type != CLOCK_TXFROMRX)
397 return -EINVAL; /* No such clock setting */
399 if (line.loopback != 0)
402 get_status(port)->clocking = line.clock_type;
406 return hdlc_ioctl(dev, ifr, cmd);
412 static int wanxl_open(struct net_device *dev)
414 port_t *port = dev_to_port(dev);
415 u8 *dbr = port->card->plx + PLX_DOORBELL_TO_CARD;
416 unsigned long timeout;
419 if (get_status(port)->open) {
420 printk(KERN_ERR "%s: port already open\n", port_name(port));
423 if ((i = hdlc_open(dev)) != 0)
426 port->tx_in = port->tx_out = 0;
427 for (i = 0; i < TX_BUFFERS; i++)
428 get_status(port)->tx_descs[i].stat = PACKET_EMPTY;
429 /* signal the card */
430 writel(1 << (DOORBELL_TO_CARD_OPEN_0 + port->node), dbr);
432 timeout = jiffies + HZ;
434 if (get_status(port)->open)
436 while (time_after(timeout, jiffies));
438 printk(KERN_ERR "%s: unable to open port\n", port_name(port));
439 /* ask the card to close the port, should it be still alive */
440 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node), dbr);
446 static int wanxl_close(struct net_device *dev)
448 port_t *port = dev_to_port(dev);
449 unsigned long timeout;
453 /* signal the card */
454 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node),
455 port->card->plx + PLX_DOORBELL_TO_CARD);
457 timeout = jiffies + HZ;
459 if (!get_status(port)->open)
461 while (time_after(timeout, jiffies));
463 if (get_status(port)->open)
464 printk(KERN_ERR "%s: unable to close port\n", port_name(port));
466 for (i = 0; i < TX_BUFFERS; i++) {
467 desc_t *desc = &get_status(port)->tx_descs[i];
469 if (desc->stat != PACKET_EMPTY) {
470 desc->stat = PACKET_EMPTY;
471 pci_unmap_single(port->card->pdev, desc->address,
472 port->tx_skbs[i]->len,
474 dev_kfree_skb(port->tx_skbs[i]);
482 static struct net_device_stats *wanxl_get_stats(struct net_device *dev)
484 struct net_device_stats *stats = hdlc_stats(dev);
485 port_t *port = dev_to_port(dev);
487 stats->rx_over_errors = get_status(port)->rx_overruns;
488 stats->rx_frame_errors = get_status(port)->rx_frame_errors;
489 stats->rx_errors = stats->rx_over_errors + stats->rx_frame_errors;
495 static int wanxl_puts_command(card_t *card, u32 cmd)
497 unsigned long timeout = jiffies + 5 * HZ;
499 writel(cmd, card->plx + PLX_MAILBOX_1);
501 if (readl(card->plx + PLX_MAILBOX_1) == 0)
505 }while (time_after(timeout, jiffies));
512 static void wanxl_reset(card_t *card)
514 u32 old_value = readl(card->plx + PLX_CONTROL) & ~PLX_CTL_RESET;
516 writel(0x80, card->plx + PLX_MAILBOX_0);
517 writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL);
518 readl(card->plx + PLX_CONTROL); /* wait for posted write */
520 writel(old_value, card->plx + PLX_CONTROL);
521 readl(card->plx + PLX_CONTROL); /* wait for posted write */
526 static void wanxl_pci_remove_one(struct pci_dev *pdev)
528 card_t *card = pci_get_drvdata(pdev);
531 for (i = 0; i < 4; i++)
532 if (card->ports[i]) {
533 struct net_device *dev = port_to_dev(card->ports[i]);
534 unregister_hdlc_device(dev);
537 /* unregister and free all host resources */
539 free_irq(card->irq, card);
543 for (i = 0; i < RX_QUEUE_LENGTH; i++)
544 if (card->rx_skbs[i]) {
545 pci_unmap_single(card->pdev,
546 card->status->rx_descs[i].address,
547 BUFFER_LENGTH, PCI_DMA_FROMDEVICE);
548 dev_kfree_skb(card->rx_skbs[i]);
555 pci_free_consistent(pdev, sizeof(card_status_t),
556 card->status, card->status_address);
558 for (i = 0; i < card->n_ports; i++)
559 if (card->__ports[i].dev)
560 free_netdev(card->__ports[i].dev);
562 pci_set_drvdata(pdev, NULL);
564 pci_release_regions(pdev);
568 #include "wanxlfw.inc"
570 static int __devinit wanxl_pci_init_one(struct pci_dev *pdev,
571 const struct pci_device_id *ent)
575 unsigned long timeout;
576 u32 plx_phy; /* PLX PCI base address */
577 u32 mem_phy; /* memory PCI base addr */
578 u8 *mem; /* memory virtual base addr */
579 int i, ports, alloc_size;
582 static int printed_version;
583 if (!printed_version) {
585 printk(KERN_INFO "%s\n", version);
589 i = pci_enable_device(pdev);
593 /* QUICC can only access first 256 MB of host RAM directly,
594 but PLX9060 DMA does 32-bits for actual packet data transfers */
596 /* FIXME when PCI/DMA subsystems are fixed.
597 We set both dma_mask and consistent_dma_mask to 28 bits
598 and pray pci_alloc_consistent() will use this info. It should
599 work on most platforms */
600 if (pci_set_consistent_dma_mask(pdev, 0x0FFFFFFF) ||
601 pci_set_dma_mask(pdev, 0x0FFFFFFF)) {
602 printk(KERN_ERR "No usable DMA configuration\n");
606 i = pci_request_regions(pdev, "wanXL");
610 switch (pdev->device) {
611 case PCI_DEVICE_ID_SBE_WANXL100: ports = 1; break;
612 case PCI_DEVICE_ID_SBE_WANXL200: ports = 2; break;
616 alloc_size = sizeof(card_t) + ports * sizeof(port_t);
617 card = kmalloc(alloc_size, GFP_KERNEL);
619 printk(KERN_ERR "wanXL %s: unable to allocate memory\n",
621 pci_release_regions(pdev);
624 memset(card, 0, alloc_size);
626 pci_set_drvdata(pdev, card);
628 card->n_ports = ports;
630 for (i = 0; i < ports; i++) {
631 card->__ports[i].dev = alloc_hdlcdev(&card->__ports[i]);
632 if (!card->__ports[i].dev) {
633 printk(KERN_ERR "wanXL %s: unable to allocate memory\n",
635 wanxl_pci_remove_one(pdev);
640 card->status = pci_alloc_consistent(pdev, sizeof(card_status_t),
641 &card->status_address);
642 if (card->status == NULL) {
643 wanxl_pci_remove_one(pdev);
648 printk(KERN_DEBUG "wanXL %s: pci_alloc_consistent() returned memory"
649 " at 0x%LX\n", card_name(pdev),
650 (unsigned long long)card->status_address);
653 /* FIXME when PCI/DMA subsystems are fixed.
654 We set both dma_mask and consistent_dma_mask back to 32 bits
655 to indicate the card can do 32-bit DMA addressing */
656 if (pci_set_consistent_dma_mask(pdev, 0xFFFFFFFF) ||
657 pci_set_dma_mask(pdev, 0xFFFFFFFF)) {
658 printk(KERN_ERR "No usable DMA configuration\n");
659 wanxl_pci_remove_one(pdev);
663 /* set up PLX mapping */
664 plx_phy = pci_resource_start(pdev, 0);
665 card->plx = ioremap_nocache(plx_phy, 0x70);
667 #if RESET_WHILE_LOADING
671 timeout = jiffies + 20 * HZ;
672 while ((stat = readl(card->plx + PLX_MAILBOX_0)) != 0) {
673 if (time_before(timeout, jiffies)) {
674 printk(KERN_WARNING "wanXL %s: timeout waiting for"
675 " PUTS to complete\n", card_name(pdev));
676 wanxl_pci_remove_one(pdev);
680 switch(stat & 0xC0) {
681 case 0x00: /* hmm - PUTS completed with non-zero code? */
682 case 0x80: /* PUTS still testing the hardware */
686 printk(KERN_WARNING "wanXL %s: PUTS test 0x%X"
687 " failed\n", card_name(pdev), stat & 0x30);
688 wanxl_pci_remove_one(pdev);
695 /* get on-board memory size (PUTS detects no more than 4 MB) */
696 ramsize = readl(card->plx + PLX_MAILBOX_2) & MBX2_MEMSZ_MASK;
698 /* set up on-board RAM mapping */
699 mem_phy = pci_resource_start(pdev, 2);
702 /* sanity check the board's reported memory size */
703 if (ramsize < BUFFERS_ADDR +
704 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports) {
705 printk(KERN_WARNING "wanXL %s: no enough on-board RAM"
706 " (%u bytes detected, %u bytes required)\n",
707 card_name(pdev), ramsize, BUFFERS_ADDR +
708 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports);
709 wanxl_pci_remove_one(pdev);
713 if (wanxl_puts_command(card, MBX1_CMD_BSWAP)) {
714 printk(KERN_WARNING "wanXL %s: unable to Set Byte Swap"
715 " Mode\n", card_name(pdev));
716 wanxl_pci_remove_one(pdev);
720 for (i = 0; i < RX_QUEUE_LENGTH; i++) {
721 struct sk_buff *skb = dev_alloc_skb(BUFFER_LENGTH);
722 card->rx_skbs[i] = skb;
724 card->status->rx_descs[i].address =
725 pci_map_single(card->pdev, skb->data,
730 mem = ioremap_nocache(mem_phy, PDM_OFFSET + sizeof(firmware));
731 for (i = 0; i < sizeof(firmware); i += 4)
732 writel(htonl(*(u32*)(firmware + i)), mem + PDM_OFFSET + i);
734 for (i = 0; i < ports; i++)
735 writel(card->status_address +
736 (void *)&card->status->port_status[i] -
737 (void *)card->status, mem + PDM_OFFSET + 4 + i * 4);
738 writel(card->status_address, mem + PDM_OFFSET + 20);
739 writel(PDM_OFFSET, mem);
742 writel(0, card->plx + PLX_MAILBOX_5);
744 if (wanxl_puts_command(card, MBX1_CMD_ABORTJ)) {
745 printk(KERN_WARNING "wanXL %s: unable to Abort and Jump\n",
747 wanxl_pci_remove_one(pdev);
752 timeout = jiffies + 5 * HZ;
754 if ((stat = readl(card->plx + PLX_MAILBOX_5)) != 0)
757 }while (time_after(timeout, jiffies));
760 printk(KERN_WARNING "wanXL %s: timeout while initializing card"
761 "firmware\n", card_name(pdev));
762 wanxl_pci_remove_one(pdev);
770 printk(KERN_INFO "wanXL %s: at 0x%X, %u KB of RAM at 0x%X, irq"
771 " %u\n" KERN_INFO "wanXL %s: port", card_name(pdev),
772 plx_phy, ramsize / 1024, mem_phy, pdev->irq, card_name(pdev));
774 for (i = 0; i < ports; i++)
775 printk("%s #%i: %s", i ? "," : "", i,
776 port_name(card->ports[i]));
780 if(request_irq(pdev->irq, wanxl_intr, SA_SHIRQ, "wanXL", card)) {
781 printk(KERN_WARNING "wanXL %s: could not allocate IRQ%i.\n",
782 card_name(pdev), pdev->irq);
783 wanxl_pci_remove_one(pdev);
786 card->irq = pdev->irq;
788 for (i = 0; i < ports; i++) {
789 port_t *port = &card->__ports[i];
790 struct net_device *dev = port_to_dev(port);
791 hdlc_device *hdlc = dev_to_hdlc(dev);
792 spin_lock_init(&port->lock);
793 SET_MODULE_OWNER(dev);
794 dev->tx_queue_len = 50;
795 dev->do_ioctl = wanxl_ioctl;
796 dev->open = wanxl_open;
797 dev->stop = wanxl_close;
798 hdlc->attach = wanxl_attach;
799 hdlc->xmit = wanxl_xmit;
800 card->ports[i] = port;
801 dev->get_stats = wanxl_get_stats;
804 get_status(port)->clocking = CLOCK_EXT;
805 if (register_hdlc_device(dev)) {
806 printk(KERN_ERR "wanXL %s: unable to register hdlc"
807 " device\n", card_name(pdev));
808 card->ports[i] = NULL;
809 wanxl_pci_remove_one(pdev);
817 static struct pci_device_id wanxl_pci_tbl[] __devinitdata = {
818 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL100, PCI_ANY_ID,
819 PCI_ANY_ID, 0, 0, 0 },
820 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL200, PCI_ANY_ID,
821 PCI_ANY_ID, 0, 0, 0 },
822 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL400, PCI_ANY_ID,
823 PCI_ANY_ID, 0, 0, 0 },
828 static struct pci_driver wanxl_pci_driver = {
830 id_table: wanxl_pci_tbl,
831 probe: wanxl_pci_init_one,
832 remove: wanxl_pci_remove_one,
836 static int __init wanxl_init_module(void)
839 printk(KERN_INFO "%s\n", version);
841 return pci_module_init(&wanxl_pci_driver);
844 static void __exit wanxl_cleanup_module(void)
846 pci_unregister_driver(&wanxl_pci_driver);
850 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
851 MODULE_DESCRIPTION("SBE Inc. wanXL serial port driver");
852 MODULE_LICENSE("GPL v2");
853 MODULE_DEVICE_TABLE(pci, wanxl_pci_tbl);
855 module_init(wanxl_init_module);
856 module_exit(wanxl_cleanup_module);