2 * linux/arch/i386/kernel/head.S -- the 32-bit startup code.
4 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Enhanced CPU detection and feature setting code by Mike Jagdis
7 * and Martin Mares, November 1997.
11 #include <linux/config.h>
12 #include <linux/threads.h>
13 #include <linux/linkage.h>
14 #include <asm/segment.h>
16 #include <asm/pgtable.h>
18 #include <asm/cache.h>
19 #include <asm/thread_info.h>
22 #define OLD_CL_MAGIC_ADDR 0x90020
23 #define OLD_CL_MAGIC 0xA33F
24 #define OLD_CL_BASE_ADDR 0x90000
25 #define OLD_CL_OFFSET 0x90022
26 #define NEW_CL_POINTER 0x228 /* Relative to real mode data */
29 * References to members of the new_cpu_data structure.
32 #define CPU_PARAMS new_cpu_data
33 #define X86 CPU_PARAMS+0
34 #define X86_VENDOR CPU_PARAMS+1
35 #define X86_MODEL CPU_PARAMS+2
36 #define X86_MASK CPU_PARAMS+3
37 #define X86_HARD_MATH CPU_PARAMS+6
38 #define X86_CPUID CPU_PARAMS+8
39 #define X86_CAPABILITY CPU_PARAMS+12
40 #define X86_VENDOR_ID CPU_PARAMS+36 /* offset dependent on NCAPINTS */
43 * Initialize page tables
45 #define INIT_PAGE_TABLES \
46 movl $pg0 - __PAGE_OFFSET, %edi; \
47 /* "007" doesn't mean with license to kill, but PRESENT+RW+USER */ \
51 cmp $empty_zero_page - __PAGE_OFFSET, %edi; \
55 * swapper_pg_dir is the main page directory, address 0x00101000
57 * On entry, %esi points to the real-mode code as a 32-bit pointer.
61 #ifdef CONFIG_X86_VISWS
63 * On SGI Visual Workstations boot CPU starts in protected mode.
68 movl $swapper_pg_dir - __PAGE_OFFSET, %eax
75 * Set segments to known values
78 movl $(__BOOT_DS),%eax
88 * New page tables may be in 4Mbyte page mode and may
89 * be using the global pages.
91 * NOTE! If we are on a 486 we may have no cr4 at all!
92 * So we do not try to touch it unless we really have
93 * some bits in it to set. This won't work if the BSP
94 * implements cr4 but this AP does not -- very unlikely
95 * but be warned! The same applies to the pse feature
96 * if not equally supported. --macro
98 * NOTE! We have to correct for the fact that we're
99 * not yet offset PAGE_OFFSET..
101 #define cr4_bits mmu_cr4_features-__PAGE_OFFSET
104 movl %cr4,%eax # Turn on paging options (PSE,PAE,..)
115 movl $swapper_pg_dir-__PAGE_OFFSET,%eax
116 movl %eax,%cr3 /* set the page table pointer.. */
119 movl %eax,%cr0 /* ..and set paging (PG) bit */
120 jmp 1f /* flush the prefetch-queue */
123 jmp *%eax /* make sure eip is relocated */
125 /* Set up the stack pointer */
130 jz 1f /* Initial CPU cleans BSS */
135 #endif /* CONFIG_SMP */
138 * Clear BSS first so that there are no surprises...
139 * No need to cld as DF is already clear from cld above...
142 movl $__bss_start,%edi
143 movl $__bss_stop,%ecx
149 * start system 32-bit setup. We need to re-do some of the things done
150 * in 16-bit mode for the "real" operations.
154 * Initialize eflags. Some BIOS's leave bits like NT set. This would
155 * confuse the debugger if this code is traced.
156 * XXX - best to initialize before switching to protected mode.
161 * Copy bootup parameters out of the way. First 2kB of
162 * _empty_zero_page is for boot parameters, second 2kB
163 * is for the command line.
165 * Note: %esi still has the pointer to the real-mode data.
167 movl $empty_zero_page,%edi
176 movl empty_zero_page+NEW_CL_POINTER,%esi
178 jnz 2f # New command line protocol
179 cmpw $(OLD_CL_MAGIC),OLD_CL_MAGIC_ADDR
181 movzwl OLD_CL_OFFSET,%esi
182 addl $(OLD_CL_BASE_ADDR),%esi
184 movl $empty_zero_page+2048,%edi
191 movl $-1,X86_CPUID # -1 for no CPUID initially
193 /* check if it is 486 or 386. */
195 * XXX - this does a lot of unnecessary setup. Alignment checks don't
196 * apply at our cpl of 0 and the stack ought to be aligned already, and
197 * we don't need to preserve eflags.
200 movb $3,X86 # at least 386
202 popl %eax # get EFLAGS
203 movl %eax,%ecx # save original EFLAGS
204 xorl $0x240000,%eax # flip AC and ID bits in EFLAGS
205 pushl %eax # copy to EFLAGS
207 pushfl # get new EFLAGS
208 popl %eax # put it in eax
209 xorl %ecx,%eax # change in flags
210 pushl %ecx # restore original EFLAGS
212 testl $0x40000,%eax # check if AC bit changed
215 movb $4,X86 # at least 486
216 testl $0x200000,%eax # check if ID bit changed
219 /* get vendor info */
220 xorl %eax,%eax # call CPUID with 0 -> return vendor ID
222 movl %eax,X86_CPUID # save CPUID level
223 movl %ebx,X86_VENDOR_ID # lo 4 chars
224 movl %edx,X86_VENDOR_ID+4 # next 4 chars
225 movl %ecx,X86_VENDOR_ID+8 # last 4 chars
227 orl %eax,%eax # do we have processor info as well?
230 movl $1,%eax # Use the CPUID instruction to get CPU type
232 movb %al,%cl # save reg for future use
233 andb $0x0f,%ah # mask processor family
235 andb $0xf0,%al # mask model
238 andb $0x0f,%cl # mask mask revision
240 movl %edx,X86_CAPABILITY
242 is486: movl $0x50022,%ecx # set AM, WP, NE and MP
245 is386: movl $2,%ecx # set MP
247 andl $0x80000011,%eax # Save PG,PE,ET
255 ljmp $(__KERNEL_CS),$1f
256 1: movl $(__KERNEL_DS),%eax # reload all the segment registers
257 movl %eax,%ss # after changing gdt.
259 movl $(__USER_DS),%eax # DS/ES contains default USER segment
263 xorl %eax,%eax # Clear FS/GS and LDT
267 cld # gcc2 wants the direction flag cleared at all times
271 je 1f # the first CPU calls start_kernel
272 # all other CPUs call initialize_secondary
273 call initialize_secondary
279 jmp L6 # main should never return here, but
280 # just in case, we know what happens.
285 * We depend on ET to be correct. This checks for 287/387.
288 movb $0,X86_HARD_MATH
294 movl %cr0,%eax /* no coprocessor: have to set bits */
295 xorl $4,%eax /* set EM */
299 1: movb $1,X86_HARD_MATH
300 .byte 0xDB,0xE4 /* fsetpm for 287, ignored by 387 */
306 * sets up a idt with 256 entries pointing to
307 * ignore_int, interrupt gates. It doesn't actually load
308 * idt - that can be done only after paging has been enabled
309 * and the kernel moved to PAGE_OFFSET. Interrupts
310 * are enabled elsewhere, when we can be relatively
311 * sure everything is ok.
315 movl $(__KERNEL_CS << 16),%eax
316 movw %dx,%ax /* selector = 0x0010 = cs */
317 movw $0x8E00,%dx /* interrupt gate - dpl=0, present */
330 .long init_thread_union+THREAD_SIZE
333 /* This is the default interrupt "handler" :-) */
335 .asciz "Unknown interrupt\n"
344 movl $(__KERNEL_DS),%eax
358 * The IDT and GDT 'descriptors' are a strange 48-bit object
359 * only used by the lidt and lgdt instructions. They are not
360 * like usual segment descriptors - they consist of a 16-bit
361 * segment size, and 32-bit linear address value:
368 .word 0 # 32-bit align idt_desc.address
370 .word IDT_ENTRIES*8-1 # idt contains 256 entries
373 # boot GDT descriptor (later on used by CPU#0):
374 .word 0 # 32 bit align gdt_desc.address
376 .word GDT_ENTRIES*8-1
379 .fill NR_CPUS-1,8,0 # space for the other GDT descriptors
382 * This is initialized to create an identity-mapping at 0-8M (for bootup
383 * purposes) and another mapping of the 0-8M area at virtual address
387 ENTRY(swapper_pg_dir)
390 .fill BOOT_USER_PGD_PTRS-2,4,0
391 /* default: 766 entries */
394 /* default: 254 entries */
395 .fill BOOT_KERNEL_PGD_PTRS-2,4,0
398 * The page tables are initialized to only 8MB here - the final page
399 * tables are set up later depending on memory size.
408 * empty_zero_page must immediately follow the page tables ! (The
409 * initialization loop counts until empty_zero_page)
413 ENTRY(empty_zero_page)
418 * Real beginning of normal "text" segment
424 * This starts the data section. Note that the above is all
425 * in the text section because it has alignment requirements
426 * that we cannot fulfill any other way.
431 * The Global Descriptor Table contains 28 quadwords, per-CPU.
433 #if defined(CONFIG_SMP) || defined(CONFIG_X86_VISWS)
435 * The boot_gdt_table must mirror the equivalent in setup.S and is
436 * used only by the trampoline for booting other CPUs
438 .align L1_CACHE_BYTES
439 ENTRY(boot_gdt_table)
440 .fill GDT_ENTRY_BOOT_CS,8,0
441 .quad 0x00cf9a000000ffff /* kernel 4GB code at 0x00000000 */
442 .quad 0x00cf92000000ffff /* kernel 4GB data at 0x00000000 */
444 .align L1_CACHE_BYTES
446 .quad 0x0000000000000000 /* NULL descriptor */
447 .quad 0x0000000000000000 /* 0x0b reserved */
448 .quad 0x0000000000000000 /* 0x13 reserved */
449 .quad 0x0000000000000000 /* 0x1b reserved */
450 .quad 0x0000000000000000 /* 0x20 unused */
451 .quad 0x0000000000000000 /* 0x28 unused */
452 .quad 0x0000000000000000 /* 0x33 TLS entry 1 */
453 .quad 0x0000000000000000 /* 0x3b TLS entry 2 */
454 .quad 0x0000000000000000 /* 0x43 TLS entry 3 */
455 .quad 0x0000000000000000 /* 0x4b reserved */
456 .quad 0x0000000000000000 /* 0x53 reserved */
457 .quad 0x0000000000000000 /* 0x5b reserved */
459 .quad 0x00cf9a000000ffff /* 0x60 kernel 4GB code at 0x00000000 */
460 .quad 0x00cf92000000ffff /* 0x68 kernel 4GB data at 0x00000000 */
461 .quad 0x00cffa000000ffff /* 0x73 user 4GB code at 0x00000000 */
462 .quad 0x00cff2000000ffff /* 0x7b user 4GB data at 0x00000000 */
464 .quad 0x0000000000000000 /* 0x80 TSS descriptor */
465 .quad 0x0000000000000000 /* 0x88 LDT descriptor */
467 /* Segments used for calling PnP BIOS */
468 .quad 0x00c09a0000000000 /* 0x90 32-bit code */
469 .quad 0x00809a0000000000 /* 0x98 16-bit code */
470 .quad 0x0080920000000000 /* 0xa0 16-bit data */
471 .quad 0x0080920000000000 /* 0xa8 16-bit data */
472 .quad 0x0080920000000000 /* 0xb0 16-bit data */
474 * The APM segments have byte granularity and their bases
475 * and limits are set at run time.
477 .quad 0x00409a0000000000 /* 0xb8 APM CS code */
478 .quad 0x00009a0000000000 /* 0xc0 APM CS 16 code (16 bit) */
479 .quad 0x0040920000000000 /* 0xc8 APM DS data */
481 .quad 0x0000000000000000 /* 0xd0 - unused */
482 .quad 0x0000000000000000 /* 0xd8 - unused */
483 .quad 0x0000000000000000 /* 0xe0 - unused */
484 .quad 0x0000000000000000 /* 0xe8 - unused */
485 .quad 0x0000000000000000 /* 0xf0 - unused */
486 .quad 0x0000000000000000 /* 0xf8 - GDT entry 31: double-fault TSS */
489 .fill (NR_CPUS-1)*GDT_ENTRIES,8,0 /* other CPU's GDT */