drivers/staging/iio/accel/lis3l02dq_core.c

   1 /*
   2  * lis3l02dq.c  support STMicroelectronics LISD02DQ
   3  *              3d 2g Linear Accelerometers via SPI
   4  *
   5  * Copyright (c) 2007 Jonathan Cameron <jic23@cam.ac.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Settings:
  12  * 16 bit left justified mode used.
  13  */
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/gpio.h>
  18 #include <linux/workqueue.h>
  19 #include <linux/mutex.h>
  20 #include <linux/device.h>
  21 #include <linux/kernel.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/slab.h>
  24
  25 #include <linux/sysfs.h>
  26 #include <linux/list.h>
  27
  28 #include "../iio.h"
  29 #include "../sysfs.h"
  30 #include "accel.h"
  31
  32 #include "lis3l02dq.h"
  33
  34 /* At the moment the spi framework doesn't allow global setting of cs_change.
  35  * It's in the likely to be added comment at the top of spi.h.
  36  * This means that use cannot be made of spi_write etc.
  37  */
  38
  39 /**
  40  * lis3l02dq_spi_read_reg_8() - read single byte from a single register
  41  * @dev: device asosciated with child of actual device (iio_dev or iio_trig)
  42  * @reg_address: the address of the register to be read
  43  * @val: pass back the resulting value
  44  **/
  45 int lis3l02dq_spi_read_reg_8(struct device *dev, u8 reg_address, u8 *val)
  46 {
  47         int ret;
  48         struct spi_message msg;
  49         struct iio_dev *indio_dev = dev_get_drvdata(dev);
  50         struct lis3l02dq_state *st = iio_dev_get_devdata(indio_dev);
  51         struct spi_transfer xfer = {
  52                 .tx_buf = st->tx,
  53                 .rx_buf = st->rx,
  54                 .bits_per_word = 8,
  55                 .len = 2,
  56                 .cs_change = 1,
  57         };
  58
  59         mutex_lock(&st->buf_lock);
  60         st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
  61         st->tx[1] = 0;
  62
  63         spi_message_init(&msg);
  64         spi_message_add_tail(&xfer, &msg);
  65         ret = spi_sync(st->us, &msg);
  66         *val = st->rx[1];
  67         mutex_unlock(&st->buf_lock);
  68
  69         return ret;
  70 }
  71
  72 /**
  73  * lis3l02dq_spi_write_reg_8() - write single byte to a register
  74  * @dev: device associated with child of actual device (iio_dev or iio_trig)
  75  * @reg_address: the address of the register to be writen
  76  * @val: the value to write
  77  **/
  78 int lis3l02dq_spi_write_reg_8(struct device *dev,
  79                               u8 reg_address,
  80                               u8 *val)
  81 {
  82         int ret;
  83         struct spi_message msg;
  84         struct iio_dev *indio_dev = dev_get_drvdata(dev);
  85         struct lis3l02dq_state *st = iio_dev_get_devdata(indio_dev);
  86         struct spi_transfer xfer = {
  87                 .tx_buf = st->tx,
  88                 .bits_per_word = 8,
  89                 .len = 2,
  90                 .cs_change = 1,
  91         };
  92
  93         mutex_lock(&st->buf_lock);
  94         st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
  95         st->tx[1] = *val;
  96
  97         spi_message_init(&msg);
  98         spi_message_add_tail(&xfer, &msg);
  99         ret =  spi_sync(st->us, &msg);
 100         mutex_unlock(&st->buf_lock);
 101
 102         return ret;
 103 }
 104
 105 /**
 106  * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
 107  * @dev: device associated with child of actual device (iio_dev or iio_trig)
 108  * @reg_address: the address of the lower of the two registers. Second register
 109  *               is assumed to have address one greater.
 110  * @val: value to be written
 111  **/
 112 static int lis3l02dq_spi_write_reg_s16(struct device *dev,
 113                                        u8 lower_reg_address,
 114                                        s16 value)
 115 {
 116         int ret;
 117         struct spi_message msg;
 118         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 119         struct lis3l02dq_state *st = iio_dev_get_devdata(indio_dev);
 120         struct spi_transfer xfers[] = { {
 121                         .tx_buf = st->tx,
 122                         .bits_per_word = 8,
 123                         .len = 2,
 124                         .cs_change = 1,
 125                 }, {
 126                         .tx_buf = st->tx + 2,
 127                         .bits_per_word = 8,
 128                         .len = 2,
 129                         .cs_change = 1,
 130                 },
 131         };
 132
 133         mutex_lock(&st->buf_lock);
 134         st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
 135         st->tx[1] = value & 0xFF;
 136         st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
 137         st->tx[3] = (value >> 8) & 0xFF;
 138
 139         spi_message_init(&msg);
 140         spi_message_add_tail(&xfers[0], &msg);
 141         spi_message_add_tail(&xfers[1], &msg);
 142         ret = spi_sync(st->us, &msg);
 143         mutex_unlock(&st->buf_lock);
 144
 145         return ret;
 146 }
 147
 148 /**
 149  * lisl302dq_spi_read_reg_s16() - write 2 bytes to a pair of registers
 150  * @dev: device associated with child of actual device (iio_dev or iio_trig)
 151  * @reg_address: the address of the lower of the two registers. Second register
 152  *               is assumed to have address one greater.
 153  * @val: somewhere to pass back the value read
 154  **/
 155 static int lis3l02dq_spi_read_reg_s16(struct device *dev,
 156                                       u8 lower_reg_address,
 157                                       s16 *val)
 158 {
 159         struct spi_message msg;
 160         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 161         struct lis3l02dq_state *st = iio_dev_get_devdata(indio_dev);
 162         int ret;
 163         struct spi_transfer xfers[] = { {
 164                         .tx_buf = st->tx,
 165                         .rx_buf = st->rx,
 166                         .bits_per_word = 8,
 167                         .len = 2,
 168                         .cs_change = 1,
 169                 }, {
 170                         .tx_buf = st->tx + 2,
 171                         .rx_buf = st->rx + 2,
 172                         .bits_per_word = 8,
 173                         .len = 2,
 174                         .cs_change = 1,
 175
 176                 },
 177         };
 178
 179         mutex_lock(&st->buf_lock);
 180         st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
 181         st->tx[1] = 0;
 182         st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address+1);
 183         st->tx[3] = 0;
 184
 185         spi_message_init(&msg);
 186         spi_message_add_tail(&xfers[0], &msg);
 187         spi_message_add_tail(&xfers[1], &msg);
 188         ret = spi_sync(st->us, &msg);
 189         if (ret) {
 190                 dev_err(&st->us->dev, "problem when reading 16 bit register");
 191                 goto error_ret;
 192         }
 193         *val = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
 194
 195 error_ret:
 196         mutex_unlock(&st->buf_lock);
 197         return ret;
 198 }
 199
 200 /**
 201  * lis3l02dq_read_signed() - attribute function used for 8 bit signed values
 202  * @dev: the child device associated with the iio_dev or iio_trigger
 203  * @attr: the attribute being processed
 204  * @buf: buffer into which put the output string
 205  **/
 206 static ssize_t lis3l02dq_read_signed(struct device *dev,
 207                                      struct device_attribute *attr,
 208                                      char *buf)
 209 {
 210         int ret;
 211         s8 val;
 212         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 213
 214         ret = lis3l02dq_spi_read_reg_8(dev, this_attr->address, (u8 *)&val);
 215
 216         return ret ? ret : sprintf(buf, "%d\n", val);
 217 }
 218
 219 static ssize_t lis3l02dq_read_unsigned(struct device *dev,
 220                                        struct device_attribute *attr,
 221                                        char *buf)
 222 {
 223         int ret;
 224         u8 val;
 225         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 226
 227         ret = lis3l02dq_spi_read_reg_8(dev, this_attr->address, &val);
 228
 229         return ret ? ret : sprintf(buf, "%d\n", val);
 230 }
 231
 232 static ssize_t lis3l02dq_write_signed(struct device *dev,
 233                                       struct device_attribute *attr,
 234                                       const char *buf,
 235                                       size_t len)
 236 {
 237         long valin;
 238         s8 val;
 239         int ret;
 240         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 241
 242         ret = strict_strtol(buf, 10, &valin);
 243         if (ret)
 244                 goto error_ret;
 245         val = valin;
 246         ret = lis3l02dq_spi_write_reg_8(dev, this_attr->address, (u8 *)&val);
 247
 248 error_ret:
 249         return ret ? ret : len;
 250 }
 251
 252 static ssize_t lis3l02dq_write_unsigned(struct device *dev,
 253                                         struct device_attribute *attr,
 254                                         const char *buf,
 255                                         size_t len)
 256 {
 257         int ret;
 258         ulong valin;
 259         u8 val;
 260         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 261
 262         ret = strict_strtoul(buf, 10, &valin);
 263         if (ret)
 264                 goto err_ret;
 265         val = valin;
 266         ret = lis3l02dq_spi_write_reg_8(dev, this_attr->address, &val);
 267
 268 err_ret:
 269         return ret ? ret : len;
 270 }
 271
 272 static ssize_t lis3l02dq_read_16bit_signed(struct device *dev,
 273                                            struct device_attribute *attr,
 274                                            char *buf)
 275 {
 276         int ret;
 277         s16 val = 0;
 278         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 279
 280         ret = lis3l02dq_spi_read_reg_s16(dev, this_attr->address, &val);
 281
 282         if (ret)
 283                 return ret;
 284
 285         return sprintf(buf, "%d\n", val);
 286 }
 287
 288 static ssize_t lis3l02dq_read_accel(struct device *dev,
 289                                     struct device_attribute *attr,
 290                                     char *buf)
 291 {
 292         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 293         ssize_t ret;
 294
 295         /* Take the iio_dev status lock */
 296         mutex_lock(&indio_dev->mlock);
 297         if (indio_dev->currentmode == INDIO_RING_TRIGGERED)
 298                 ret = lis3l02dq_read_accel_from_ring(dev, attr, buf);
 299         else
 300                 ret =  lis3l02dq_read_16bit_signed(dev, attr, buf);
 301         mutex_unlock(&indio_dev->mlock);
 302
 303         return ret;
 304 }
 305
 306 static ssize_t lis3l02dq_write_16bit_signed(struct device *dev,
 307                                             struct device_attribute *attr,
 308                                             const char *buf,
 309                                             size_t len)
 310 {
 311         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 312         int ret;
 313         long val;
 314
 315         ret = strict_strtol(buf, 10, &val);
 316         if (ret)
 317                 goto error_ret;
 318         ret = lis3l02dq_spi_write_reg_s16(dev, this_attr->address, val);
 319
 320 error_ret:
 321         return ret ? ret : len;
 322 }
 323
 324 static ssize_t lis3l02dq_read_frequency(struct device *dev,
 325                                         struct device_attribute *attr,
 326                                         char *buf)
 327 {
 328         int ret, len = 0;
 329         s8 t;
 330         ret = lis3l02dq_spi_read_reg_8(dev,
 331                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 332                                        (u8 *)&t);
 333         if (ret)
 334                 return ret;
 335         t &= LIS3L02DQ_DEC_MASK;
 336         switch (t) {
 337         case LIS3L02DQ_REG_CTRL_1_DF_128:
 338                 len = sprintf(buf, "280\n");
 339                 break;
 340         case LIS3L02DQ_REG_CTRL_1_DF_64:
 341                 len = sprintf(buf, "560\n");
 342                 break;
 343         case LIS3L02DQ_REG_CTRL_1_DF_32:
 344                 len = sprintf(buf, "1120\n");
 345                 break;
 346         case LIS3L02DQ_REG_CTRL_1_DF_8:
 347                 len = sprintf(buf, "4480\n");
 348                 break;
 349         }
 350         return len;
 351 }
 352
 353 static ssize_t lis3l02dq_write_frequency(struct device *dev,
 354                                          struct device_attribute *attr,
 355                                          const char *buf,
 356                                          size_t len)
 357 {
 358         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 359         long val;
 360         int ret;
 361         u8 t;
 362
 363         ret = strict_strtol(buf, 10, &val);
 364         if (ret)
 365                 return ret;
 366
 367         mutex_lock(&indio_dev->mlock);
 368         ret = lis3l02dq_spi_read_reg_8(dev,
 369                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 370                                        &t);
 371         if (ret)
 372                 goto error_ret_mutex;
 373         /* Wipe the bits clean */
 374         t &= ~LIS3L02DQ_DEC_MASK;
 375         switch (val) {
 376         case 280:
 377                 t |= LIS3L02DQ_REG_CTRL_1_DF_128;
 378                 break;
 379         case 560:
 380                 t |= LIS3L02DQ_REG_CTRL_1_DF_64;
 381                 break;
 382         case 1120:
 383                 t |= LIS3L02DQ_REG_CTRL_1_DF_32;
 384                 break;
 385         case 4480:
 386                 t |= LIS3L02DQ_REG_CTRL_1_DF_8;
 387                 break;
 388         default:
 389                 ret = -EINVAL;
 390                 goto error_ret_mutex;
 391         };
 392
 393         ret = lis3l02dq_spi_write_reg_8(dev,
 394                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 395                                         &t);
 396
 397 error_ret_mutex:
 398         mutex_unlock(&indio_dev->mlock);
 399
 400         return ret ? ret : len;
 401 }
 402
 403 static int lis3l02dq_initial_setup(struct lis3l02dq_state *st)
 404 {
 405         int ret;
 406         u8 val, valtest;
 407
 408         st->us->mode = SPI_MODE_3;
 409
 410         spi_setup(st->us);
 411
 412         val = LIS3L02DQ_DEFAULT_CTRL1;
 413         /* Write suitable defaults to ctrl1 */
 414         ret = lis3l02dq_spi_write_reg_8(&st->indio_dev->dev,
 415                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 416                                         &val);
 417         if (ret) {
 418                 dev_err(&st->us->dev, "problem with setup control register 1");
 419                 goto err_ret;
 420         }
 421         /* Repeat as sometimes doesn't work first time?*/
 422         ret = lis3l02dq_spi_write_reg_8(&st->indio_dev->dev,
 423                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 424                                         &val);
 425         if (ret) {
 426                 dev_err(&st->us->dev, "problem with setup control register 1");
 427                 goto err_ret;
 428         }
 429
 430         /* Read back to check this has worked acts as loose test of correct
 431          * chip */
 432         ret = lis3l02dq_spi_read_reg_8(&st->indio_dev->dev,
 433                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 434                                        &valtest);
 435         if (ret || (valtest != val)) {
 436                 dev_err(&st->indio_dev->dev, "device not playing ball");
 437                 ret = -EINVAL;
 438                 goto err_ret;
 439         }
 440
 441         val = LIS3L02DQ_DEFAULT_CTRL2;
 442         ret = lis3l02dq_spi_write_reg_8(&st->indio_dev->dev,
 443                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 444                                         &val);
 445         if (ret) {
 446                 dev_err(&st->us->dev, "problem with setup control register 2");
 447                 goto err_ret;
 448         }
 449
 450         val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
 451         ret = lis3l02dq_spi_write_reg_8(&st->indio_dev->dev,
 452                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 453                                         &val);
 454         if (ret)
 455                 dev_err(&st->us->dev, "problem with interrupt cfg register");
 456 err_ret:
 457
 458         return ret;
 459 }
 460
 461 #define LIS3L02DQ_SIGNED_ATTR(name, reg)        \
 462         IIO_DEVICE_ATTR(name,                   \
 463                         S_IWUSR | S_IRUGO,      \
 464                         lis3l02dq_read_signed,  \
 465                         lis3l02dq_write_signed, \
 466                         reg);
 467
 468 #define LIS3L02DQ_UNSIGNED_ATTR(name, reg)              \
 469         IIO_DEVICE_ATTR(name,                           \
 470                         S_IWUSR | S_IRUGO,              \
 471                         lis3l02dq_read_unsigned,        \
 472                         lis3l02dq_write_unsigned,       \
 473                         reg);
 474
 475 static LIS3L02DQ_SIGNED_ATTR(accel_x_calibbias,
 476                              LIS3L02DQ_REG_OFFSET_X_ADDR);
 477 static LIS3L02DQ_SIGNED_ATTR(accel_y_calibbias,
 478                              LIS3L02DQ_REG_OFFSET_Y_ADDR);
 479 static LIS3L02DQ_SIGNED_ATTR(accel_z_calibbias,
 480                              LIS3L02DQ_REG_OFFSET_Z_ADDR);
 481
 482 static LIS3L02DQ_UNSIGNED_ATTR(accel_x_calibscale,
 483                                LIS3L02DQ_REG_GAIN_X_ADDR);
 484 static LIS3L02DQ_UNSIGNED_ATTR(accel_y_calibscale,
 485                                LIS3L02DQ_REG_GAIN_Y_ADDR);
 486 static LIS3L02DQ_UNSIGNED_ATTR(accel_z_calibscale,
 487                                LIS3L02DQ_REG_GAIN_Z_ADDR);
 488
 489 static IIO_DEVICE_ATTR(accel_mag_either_rising_value,
 490                        S_IWUSR | S_IRUGO,
 491                        lis3l02dq_read_16bit_signed,
 492                        lis3l02dq_write_16bit_signed,
 493                        LIS3L02DQ_REG_THS_L_ADDR);
 494 /* RFC The reading method for these will change depending on whether
 495  * ring buffer capture is in use. Is it worth making these take two
 496  * functions and let the core handle which to call, or leave as in this
 497  * driver where it is the drivers problem to manage this?
 498  */
 499
 500 static IIO_DEV_ATTR_ACCEL_X(lis3l02dq_read_accel,
 501                             LIS3L02DQ_REG_OUT_X_L_ADDR);
 502
 503 static IIO_DEV_ATTR_ACCEL_Y(lis3l02dq_read_accel,
 504                             LIS3L02DQ_REG_OUT_Y_L_ADDR);
 505
 506 static IIO_DEV_ATTR_ACCEL_Z(lis3l02dq_read_accel,
 507                             LIS3L02DQ_REG_OUT_Z_L_ADDR);
 508
 509 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
 510                               lis3l02dq_read_frequency,
 511                               lis3l02dq_write_frequency);
 512
 513 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
 514
 515 static ssize_t lis3l02dq_read_interrupt_config(struct device *dev,
 516                                                struct device_attribute *attr,
 517                                                char *buf)
 518 {
 519         int ret;
 520         s8 val;
 521         struct iio_event_attr *this_attr = to_iio_event_attr(attr);
 522
 523         ret = lis3l02dq_spi_read_reg_8(dev->parent,
 524                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 525                                        (u8 *)&val);
 526
 527         return ret ? ret : sprintf(buf, "%d\n",
 528                                    (val & this_attr->mask) ? 1 : 0);;
 529 }
 530
 531 static ssize_t lis3l02dq_write_interrupt_config(struct device *dev,
 532                                                 struct device_attribute *attr,
 533                                                 const char *buf,
 534                                                 size_t len)
 535 {
 536         struct iio_event_attr *this_attr = to_iio_event_attr(attr);
 537         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 538         int ret, currentlyset, changed = 0;
 539         u8 valold, controlold;
 540         bool val;
 541
 542         val = !(buf[0] == '0');
 543
 544         mutex_lock(&indio_dev->mlock);
 545         /* read current value */
 546         ret = lis3l02dq_spi_read_reg_8(dev->parent,
 547                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 548                                        &valold);
 549         if (ret)
 550                 goto error_mutex_unlock;
 551
 552         /* read current control */
 553         ret = lis3l02dq_spi_read_reg_8(dev,
 554                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 555                                        &controlold);
 556         if (ret)
 557                 goto error_mutex_unlock;
 558         currentlyset = !!(valold & this_attr->mask);
 559         if (val == false && currentlyset) {
 560                 valold &= ~this_attr->mask;
 561                 changed = 1;
 562                 iio_remove_event_from_list(this_attr->listel,
 563                                                  &indio_dev->interrupts[0]
 564                                                  ->ev_list);
 565         } else if (val == true && !currentlyset) {
 566                 changed = 1;
 567                 valold |= this_attr->mask;
 568                 iio_add_event_to_list(this_attr->listel,
 569                                             &indio_dev->interrupts[0]->ev_list);
 570         }
 571
 572         if (changed) {
 573                 ret = lis3l02dq_spi_write_reg_8(dev,
 574                                                 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 575                                                 &valold);
 576                 if (ret)
 577                         goto error_mutex_unlock;
 578                 /* This always enables the interrupt, even if we've remove the
 579                  * last thing using it. For this device we can use the reference
 580                  * count on the handler to tell us if anyone wants the interrupt
 581                  */
 582                 controlold = this_attr->listel->refcount ?
 583                         (controlold | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
 584                         (controlold & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
 585                 ret = lis3l02dq_spi_write_reg_8(dev,
 586                                                 LIS3L02DQ_REG_CTRL_2_ADDR,
 587                                                 &controlold);
 588                 if (ret)
 589                         goto error_mutex_unlock;
 590         }
 591 error_mutex_unlock:
 592         mutex_unlock(&indio_dev->mlock);
 593
 594         return ret ? ret : len;
 595 }
 596
 597
 598 static int lis3l02dq_thresh_handler_th(struct iio_dev *dev_info,
 599                                        int index,
 600                                        s64 timestamp,
 601                                        int no_test)
 602 {
 603         struct lis3l02dq_state *st = dev_info->dev_data;
 604
 605         /* Stash the timestamp somewhere convenient for the bh */
 606         st->last_timestamp = timestamp;
 607         schedule_work(&st->work_cont_thresh.ws);
 608
 609         return 0;
 610 }
 611
 612
 613 /* Unforunately it appears the interrupt won't clear unless you read from the
 614  * src register.
 615  */
 616 static void lis3l02dq_thresh_handler_bh_no_check(struct work_struct *work_s)
 617 {
 618         struct iio_work_cont *wc
 619                 = container_of(work_s, struct iio_work_cont, ws);
 620         struct lis3l02dq_state *st = wc->st;
 621         u8 t;
 622
 623         lis3l02dq_spi_read_reg_8(&st->indio_dev->dev,
 624                                  LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 625                                  &t);
 626
 627         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
 628                 iio_push_event(st->indio_dev, 0,
 629                                IIO_EVENT_CODE_ACCEL_Z_HIGH,
 630                                st->last_timestamp);
 631
 632         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
 633                 iio_push_event(st->indio_dev, 0,
 634                                IIO_EVENT_CODE_ACCEL_Z_LOW,
 635                                st->last_timestamp);
 636
 637         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
 638                 iio_push_event(st->indio_dev, 0,
 639                                IIO_EVENT_CODE_ACCEL_Y_HIGH,
 640                                st->last_timestamp);
 641
 642         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
 643                 iio_push_event(st->indio_dev, 0,
 644                                IIO_EVENT_CODE_ACCEL_Y_LOW,
 645                                st->last_timestamp);
 646
 647         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
 648                 iio_push_event(st->indio_dev, 0,
 649                                IIO_EVENT_CODE_ACCEL_X_HIGH,
 650                                st->last_timestamp);
 651
 652         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
 653                 iio_push_event(st->indio_dev, 0,
 654                                IIO_EVENT_CODE_ACCEL_X_LOW,
 655                                st->last_timestamp);
 656         /* reenable the irq */
 657         enable_irq(st->us->irq);
 658         /* Ack and allow for new interrupts */
 659         lis3l02dq_spi_read_reg_8(&st->indio_dev->dev,
 660                                  LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
 661                                  &t);
 662
 663         return;
 664 }
 665
 666 /* A shared handler for a number of threshold types */
 667 IIO_EVENT_SH(threshold, &lis3l02dq_thresh_handler_th);
 668
 669 IIO_EVENT_ATTR_SH(accel_x_mag_pos_rising_en,
 670                   iio_event_threshold,
 671                   lis3l02dq_read_interrupt_config,
 672                   lis3l02dq_write_interrupt_config,
 673                   LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_X_HIGH);
 674
 675 IIO_EVENT_ATTR_SH(accel_y_mag_pos_rising_en,
 676                   iio_event_threshold,
 677                   lis3l02dq_read_interrupt_config,
 678                   lis3l02dq_write_interrupt_config,
 679                   LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Y_HIGH);
 680
 681 IIO_EVENT_ATTR_SH(accel_z_mag_pos_rising_en,
 682                   iio_event_threshold,
 683                   lis3l02dq_read_interrupt_config,
 684                   lis3l02dq_write_interrupt_config,
 685                   LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_HIGH);
 686
 687 IIO_EVENT_ATTR_SH(accel_x_mag_neg_rising_en,
 688                   iio_event_threshold,
 689                   lis3l02dq_read_interrupt_config,
 690                   lis3l02dq_write_interrupt_config,
 691                   LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_X_LOW);
 692
 693 IIO_EVENT_ATTR_SH(accel_y_mag_neg_rising_en,
 694                   iio_event_threshold,
 695                   lis3l02dq_read_interrupt_config,
 696                   lis3l02dq_write_interrupt_config,
 697                   LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Y_LOW);
 698
 699 IIO_EVENT_ATTR_SH(accel_z_mag_neg_rising_en,
 700                   iio_event_threshold,
 701                   lis3l02dq_read_interrupt_config,
 702                   lis3l02dq_write_interrupt_config,
 703                   LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_LOW);
 704
 705
 706 static struct attribute *lis3l02dq_event_attributes[] = {
 707         &iio_event_attr_accel_x_mag_pos_rising_en.dev_attr.attr,
 708         &iio_event_attr_accel_y_mag_pos_rising_en.dev_attr.attr,
 709         &iio_event_attr_accel_z_mag_pos_rising_en.dev_attr.attr,
 710         &iio_event_attr_accel_x_mag_neg_rising_en.dev_attr.attr,
 711         &iio_event_attr_accel_y_mag_neg_rising_en.dev_attr.attr,
 712         &iio_event_attr_accel_z_mag_neg_rising_en.dev_attr.attr,
 713         &iio_dev_attr_accel_mag_either_rising_value.dev_attr.attr,
 714         NULL
 715 };
 716
 717 static struct attribute_group lis3l02dq_event_attribute_group = {
 718         .attrs = lis3l02dq_event_attributes,
 719 };
 720
 721 static IIO_CONST_ATTR(name, "lis3l02dq");
 722 static IIO_CONST_ATTR(accel_scale, "0.00958");
 723
 724 static struct attribute *lis3l02dq_attributes[] = {
 725         &iio_dev_attr_accel_x_calibbias.dev_attr.attr,
 726         &iio_dev_attr_accel_y_calibbias.dev_attr.attr,
 727         &iio_dev_attr_accel_z_calibbias.dev_attr.attr,
 728         &iio_dev_attr_accel_x_calibscale.dev_attr.attr,
 729         &iio_dev_attr_accel_y_calibscale.dev_attr.attr,
 730         &iio_dev_attr_accel_z_calibscale.dev_attr.attr,
 731         &iio_const_attr_accel_scale.dev_attr.attr,
 732         &iio_dev_attr_accel_x_raw.dev_attr.attr,
 733         &iio_dev_attr_accel_y_raw.dev_attr.attr,
 734         &iio_dev_attr_accel_z_raw.dev_attr.attr,
 735         &iio_dev_attr_sampling_frequency.dev_attr.attr,
 736         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 737         &iio_const_attr_name.dev_attr.attr,
 738         NULL
 739 };
 740
 741 static const struct attribute_group lis3l02dq_attribute_group = {
 742         .attrs = lis3l02dq_attributes,
 743 };
 744
 745 static int __devinit lis3l02dq_probe(struct spi_device *spi)
 746 {
 747         int ret, regdone = 0;
 748         struct lis3l02dq_state *st = kzalloc(sizeof *st, GFP_KERNEL);
 749         if (!st) {
 750                 ret =  -ENOMEM;
 751                 goto error_ret;
 752         }
 753         /* this is only used tor removal purposes */
 754         spi_set_drvdata(spi, st);
 755
 756         /* Allocate the comms buffers */
 757         st->rx = kzalloc(sizeof(*st->rx)*LIS3L02DQ_MAX_RX, GFP_KERNEL);
 758         if (st->rx == NULL) {
 759                 ret = -ENOMEM;
 760                 goto error_free_st;
 761         }
 762         st->tx = kzalloc(sizeof(*st->tx)*LIS3L02DQ_MAX_TX, GFP_KERNEL);
 763         if (st->tx == NULL) {
 764                 ret = -ENOMEM;
 765                 goto error_free_rx;
 766         }
 767         st->us = spi;
 768         mutex_init(&st->buf_lock);
 769         /* setup the industrialio driver allocated elements */
 770         st->indio_dev = iio_allocate_device();
 771         if (st->indio_dev == NULL) {
 772                 ret = -ENOMEM;
 773                 goto error_free_tx;
 774         }
 775
 776         st->indio_dev->dev.parent = &spi->dev;
 777         st->indio_dev->num_interrupt_lines = 1;
 778         st->indio_dev->event_attrs = &lis3l02dq_event_attribute_group;
 779         st->indio_dev->attrs = &lis3l02dq_attribute_group;
 780         st->indio_dev->dev_data = (void *)(st);
 781         st->indio_dev->driver_module = THIS_MODULE;
 782         st->indio_dev->modes = INDIO_DIRECT_MODE;
 783
 784         ret = lis3l02dq_configure_ring(st->indio_dev);
 785         if (ret)
 786                 goto error_free_dev;
 787
 788         ret = iio_device_register(st->indio_dev);
 789         if (ret)
 790                 goto error_unreg_ring_funcs;
 791         regdone = 1;
 792
 793         ret = lis3l02dq_initialize_ring(st->indio_dev->ring);
 794         if (ret) {
 795                 printk(KERN_ERR "failed to initialize the ring\n");
 796                 goto error_unreg_ring_funcs;
 797         }
 798
 799         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) {
 800                 /* This is a little unusual, in that the device seems
 801                    to need a full read of the interrupt source reg before
 802                    the interrupt will reset.
 803                    Hence the two handlers are the same */
 804                 iio_init_work_cont(&st->work_cont_thresh,
 805                                    lis3l02dq_thresh_handler_bh_no_check,
 806                                    lis3l02dq_thresh_handler_bh_no_check,
 807                                    LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 808                                    0,
 809                                    st);
 810                 st->inter = 0;
 811                 ret = iio_register_interrupt_line(spi->irq,
 812                                                   st->indio_dev,
 813                                                   0,
 814                                                   IRQF_TRIGGER_RISING,
 815                                                   "lis3l02dq");
 816                 if (ret)
 817                         goto error_uninitialize_ring;
 818
 819                 ret = lis3l02dq_probe_trigger(st->indio_dev);
 820                 if (ret)
 821                         goto error_unregister_line;
 822         }
 823
 824         /* Get the device into a sane initial state */
 825         ret = lis3l02dq_initial_setup(st);
 826         if (ret)
 827                 goto error_remove_trigger;
 828         return 0;
 829
 830 error_remove_trigger:
 831         if (st->indio_dev->modes & INDIO_RING_TRIGGERED)
 832                 lis3l02dq_remove_trigger(st->indio_dev);
 833 error_unregister_line:
 834         if (st->indio_dev->modes & INDIO_RING_TRIGGERED)
 835                 iio_unregister_interrupt_line(st->indio_dev, 0);
 836 error_uninitialize_ring:
 837         lis3l02dq_uninitialize_ring(st->indio_dev->ring);
 838 error_unreg_ring_funcs:
 839         lis3l02dq_unconfigure_ring(st->indio_dev);
 840 error_free_dev:
 841         if (regdone)
 842                 iio_device_unregister(st->indio_dev);
 843         else
 844                 iio_free_device(st->indio_dev);
 845 error_free_tx:
 846         kfree(st->tx);
 847 error_free_rx:
 848         kfree(st->rx);
 849 error_free_st:
 850         kfree(st);
 851 error_ret:
 852         return ret;
 853 }
 854
 855 /* Power down the device */
 856 static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
 857 {
 858         int ret;
 859         struct lis3l02dq_state *st = indio_dev->dev_data;
 860         u8 val = 0;
 861
 862         mutex_lock(&indio_dev->mlock);
 863         ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev,
 864                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 865                                         &val);
 866         if (ret) {
 867                 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
 868                 goto err_ret;
 869         }
 870
 871         ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev,
 872                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 873                                         &val);
 874         if (ret)
 875                 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
 876 err_ret:
 877         mutex_unlock(&indio_dev->mlock);
 878         return ret;
 879 }
 880
 881 /* fixme, confirm ordering in this function */
 882 static int lis3l02dq_remove(struct spi_device *spi)
 883 {
 884         int ret;
 885         struct lis3l02dq_state *st = spi_get_drvdata(spi);
 886         struct iio_dev *indio_dev = st->indio_dev;
 887
 888         ret = lis3l02dq_stop_device(indio_dev);
 889         if (ret)
 890                 goto err_ret;
 891
 892         flush_scheduled_work();
 893
 894         lis3l02dq_remove_trigger(indio_dev);
 895         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
 896                 iio_unregister_interrupt_line(indio_dev, 0);
 897
 898         lis3l02dq_uninitialize_ring(indio_dev->ring);
 899         lis3l02dq_unconfigure_ring(indio_dev);
 900         iio_device_unregister(indio_dev);
 901         kfree(st->tx);
 902         kfree(st->rx);
 903         kfree(st);
 904
 905         return 0;
 906
 907 err_ret:
 908         return ret;
 909 }
 910
 911 static struct spi_driver lis3l02dq_driver = {
 912         .driver = {
 913                 .name = "lis3l02dq",
 914                 .owner = THIS_MODULE,
 915         },
 916         .probe = lis3l02dq_probe,
 917         .remove = __devexit_p(lis3l02dq_remove),
 918 };
 919
 920 static __init int lis3l02dq_init(void)
 921 {
 922         return spi_register_driver(&lis3l02dq_driver);
 923 }
 924 module_init(lis3l02dq_init);
 925
 926 static __exit void lis3l02dq_exit(void)
 927 {
 928         spi_unregister_driver(&lis3l02dq_driver);
 929 }
 930 module_exit(lis3l02dq_exit);
 931
 932 MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
 933 MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
 934 MODULE_LICENSE("GPL v2");