2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 /*********************************\
24 * Protocol Control Unit Functions *
25 \*********************************/
27 #include <asm/unaligned.h>
39 * ath5k_hw_set_opmode - Set PCU operating mode
41 * @ah: The &struct ath5k_hw
42 * @op_mode: &enum nl80211_iftype operating mode
44 * Initialize PCU for the various operating modes (AP/STA etc)
46 int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
48 struct ath_common *common = ath5k_hw_common(ah);
49 u32 pcu_reg, beacon_reg, low_id, high_id;
51 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
53 /* Preserve rest settings */
54 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
55 pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
56 | AR5K_STA_ID1_KEYSRCH_MODE
57 | (ah->ah_version == AR5K_AR5210 ?
58 (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));
62 ATH5K_TRACE(ah->ah_sc);
65 case NL80211_IFTYPE_ADHOC:
66 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE;
67 beacon_reg |= AR5K_BCR_ADHOC;
68 if (ah->ah_version == AR5K_AR5210)
69 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
71 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
74 case NL80211_IFTYPE_AP:
75 case NL80211_IFTYPE_MESH_POINT:
76 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE;
77 beacon_reg |= AR5K_BCR_AP;
78 if (ah->ah_version == AR5K_AR5210)
79 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
81 AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
84 case NL80211_IFTYPE_STATION:
85 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
86 | (ah->ah_version == AR5K_AR5210 ?
87 AR5K_STA_ID1_PWR_SV : 0);
88 case NL80211_IFTYPE_MONITOR:
89 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
90 | (ah->ah_version == AR5K_AR5210 ?
91 AR5K_STA_ID1_NO_PSPOLL : 0);
101 low_id = get_unaligned_le32(common->macaddr);
102 high_id = get_unaligned_le16(common->macaddr + 4);
103 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
104 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
107 * Set Beacon Control Register on 5210
109 if (ah->ah_version == AR5K_AR5210)
110 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
116 * ath5k_hw_update - Update MIB counters (mac layer statistics)
118 * @ah: The &struct ath5k_hw
120 * Reads MIB counters from PCU and updates sw statistics. Is called after a
121 * MIB interrupt, because one of these counters might have reached their maximum
122 * and triggered the MIB interrupt, to let us read and clear the counter.
124 * Is called in interrupt context!
126 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
128 struct ath5k_statistics *stats = &ah->ah_sc->stats;
131 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
132 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
133 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
134 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
135 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
139 * ath5k_hw_set_ack_bitrate - set bitrate for ACKs
141 * @ah: The &struct ath5k_hw
142 * @high: Flag to determine if we want to use high transmition rate
145 * If high flag is set, we tell hw to use a set of control rates based on
146 * the current transmition rate (check out control_rates array inside reset.c).
147 * If not hw just uses the lowest rate available for the current modulation
148 * scheme being used (1Mbit for CCK and 6Mbits for OFDM).
150 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
152 if (ah->ah_version != AR5K_AR5212)
155 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
157 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
159 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
169 * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
171 * @ah: The &struct ath5k_hw
172 * @timeout: Timeout in usec
174 static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
176 ATH5K_TRACE(ah->ah_sc);
177 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
181 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
182 ath5k_hw_htoclock(ah, timeout));
188 * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
190 * @ah: The &struct ath5k_hw
191 * @timeout: Timeout in usec
193 static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
195 ATH5K_TRACE(ah->ah_sc);
196 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
200 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
201 ath5k_hw_htoclock(ah, timeout));
207 * ath5k_hw_htoclock - Translate usec to hw clock units
209 * @ah: The &struct ath5k_hw
210 * @usec: value in microseconds
212 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
214 return usec * ath5k_hw_get_clockrate(ah);
218 * ath5k_hw_clocktoh - Translate hw clock units to usec
219 * @clock: value in hw clock units
221 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
223 return clock / ath5k_hw_get_clockrate(ah);
227 * ath5k_hw_get_clockrate - Get the clock rate for current mode
229 * @ah: The &struct ath5k_hw
231 unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah)
233 struct ieee80211_channel *channel = ah->ah_current_channel;
236 if (channel->hw_value & CHANNEL_5GHZ)
237 clock = 40; /* 802.11a */
238 else if (channel->hw_value & CHANNEL_CCK)
239 clock = 22; /* 802.11b */
241 clock = 44; /* 802.11g */
243 /* Clock rate in turbo modes is twice the normal rate */
244 if (channel->hw_value & CHANNEL_TURBO)
251 * ath5k_hw_get_default_slottime - Get the default slot time for current mode
253 * @ah: The &struct ath5k_hw
255 static unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
257 struct ieee80211_channel *channel = ah->ah_current_channel;
259 if (channel->hw_value & CHANNEL_TURBO)
260 return 6; /* both turbo modes */
262 if (channel->hw_value & CHANNEL_CCK)
263 return 20; /* 802.11b */
265 return 9; /* 802.11 a/g */
269 * ath5k_hw_get_default_sifs - Get the default SIFS for current mode
271 * @ah: The &struct ath5k_hw
273 static unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
275 struct ieee80211_channel *channel = ah->ah_current_channel;
277 if (channel->hw_value & CHANNEL_TURBO)
278 return 8; /* both turbo modes */
280 if (channel->hw_value & CHANNEL_5GHZ)
281 return 16; /* 802.11a */
283 return 10; /* 802.11 b/g */
287 * ath5k_hw_set_lladdr - Set station id
289 * @ah: The &struct ath5k_hw
290 * @mac: The card's mac address
292 * Set station id on hw using the provided mac address
294 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
296 struct ath_common *common = ath5k_hw_common(ah);
300 ATH5K_TRACE(ah->ah_sc);
301 /* Set new station ID */
302 memcpy(common->macaddr, mac, ETH_ALEN);
304 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
306 low_id = get_unaligned_le32(mac);
307 high_id = get_unaligned_le16(mac + 4);
309 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
310 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
316 * ath5k_hw_set_associd - Set BSSID for association
318 * @ah: The &struct ath5k_hw
320 * @assoc_id: Assoc id
322 * Sets the BSSID which trigers the "SME Join" operation
324 void ath5k_hw_set_associd(struct ath5k_hw *ah)
326 struct ath_common *common = ath5k_hw_common(ah);
330 * Set simple BSSID mask on 5212
332 if (ah->ah_version == AR5K_AR5212)
333 ath_hw_setbssidmask(common);
336 * Set BSSID which triggers the "SME Join" operation
338 ath5k_hw_reg_write(ah,
339 get_unaligned_le32(common->curbssid),
341 ath5k_hw_reg_write(ah,
342 get_unaligned_le16(common->curbssid + 4) |
343 ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S),
346 if (common->curaid == 0) {
347 ath5k_hw_disable_pspoll(ah);
351 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
352 tim_offset ? tim_offset + 4 : 0);
354 ath5k_hw_enable_pspoll(ah, NULL, 0);
357 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
359 struct ath_common *common = ath5k_hw_common(ah);
360 ATH5K_TRACE(ah->ah_sc);
362 /* Cache bssid mask so that we can restore it
364 memcpy(common->bssidmask, mask, ETH_ALEN);
365 if (ah->ah_version == AR5K_AR5212)
366 ath_hw_setbssidmask(common);
374 * ath5k_hw_start_rx_pcu - Start RX engine
376 * @ah: The &struct ath5k_hw
378 * Starts RX engine on PCU so that hw can process RXed frames
381 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
383 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
385 ATH5K_TRACE(ah->ah_sc);
386 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
390 * at5k_hw_stop_rx_pcu - Stop RX engine
392 * @ah: The &struct ath5k_hw
394 * Stops RX engine on PCU
396 * TODO: Detach ANI here
398 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
400 ATH5K_TRACE(ah->ah_sc);
401 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
405 * Set multicast filter
407 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
409 ATH5K_TRACE(ah->ah_sc);
410 /* Set the multicat filter */
411 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
412 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
416 * ath5k_hw_get_rx_filter - Get current rx filter
418 * @ah: The &struct ath5k_hw
420 * Returns the RX filter by reading rx filter and
421 * phy error filter registers. RX filter is used
422 * to set the allowed frame types that PCU will accept
423 * and pass to the driver. For a list of frame types
426 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
428 u32 data, filter = 0;
430 ATH5K_TRACE(ah->ah_sc);
431 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
433 /*Radar detection for 5212*/
434 if (ah->ah_version == AR5K_AR5212) {
435 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
437 if (data & AR5K_PHY_ERR_FIL_RADAR)
438 filter |= AR5K_RX_FILTER_RADARERR;
439 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
440 filter |= AR5K_RX_FILTER_PHYERR;
447 * ath5k_hw_set_rx_filter - Set rx filter
449 * @ah: The &struct ath5k_hw
450 * @filter: RX filter mask (see reg.h)
452 * Sets RX filter register and also handles PHY error filter
453 * register on 5212 and newer chips so that we have proper PHY
456 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
460 ATH5K_TRACE(ah->ah_sc);
462 /* Set PHY error filter register on 5212*/
463 if (ah->ah_version == AR5K_AR5212) {
464 if (filter & AR5K_RX_FILTER_RADARERR)
465 data |= AR5K_PHY_ERR_FIL_RADAR;
466 if (filter & AR5K_RX_FILTER_PHYERR)
467 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
471 * The AR5210 uses promiscous mode to detect radar activity
473 if (ah->ah_version == AR5K_AR5210 &&
474 (filter & AR5K_RX_FILTER_RADARERR)) {
475 filter &= ~AR5K_RX_FILTER_RADARERR;
476 filter |= AR5K_RX_FILTER_PROM;
479 /*Zero length DMA (phy error reporting) */
481 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
483 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
485 /*Write RX Filter register*/
486 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
488 /*Write PHY error filter register on 5212*/
489 if (ah->ah_version == AR5K_AR5212)
490 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
499 #define ATH5K_MAX_TSF_READ 10
502 * ath5k_hw_get_tsf64 - Get the full 64bit TSF
504 * @ah: The &struct ath5k_hw
506 * Returns the current TSF
508 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
510 u32 tsf_lower, tsf_upper1, tsf_upper2;
514 * While reading TSF upper and then lower part, the clock is still
515 * counting (or jumping in case of IBSS merge) so we might get
516 * inconsistent values. To avoid this, we read the upper part again
517 * and check it has not been changed. We make the hypothesis that a
518 * maximum of 3 changes can happens in a row (we use 10 as a safe
521 * Impact on performance is pretty small, since in most cases, only
522 * 3 register reads are needed.
525 tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
526 for (i = 0; i < ATH5K_MAX_TSF_READ; i++) {
527 tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
528 tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
529 if (tsf_upper2 == tsf_upper1)
531 tsf_upper1 = tsf_upper2;
534 WARN_ON( i == ATH5K_MAX_TSF_READ );
536 ATH5K_TRACE(ah->ah_sc);
538 return (((u64)tsf_upper1 << 32) | tsf_lower);
542 * ath5k_hw_set_tsf64 - Set a new 64bit TSF
544 * @ah: The &struct ath5k_hw
545 * @tsf64: The new 64bit TSF
549 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64)
551 ATH5K_TRACE(ah->ah_sc);
553 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32);
554 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32);
558 * ath5k_hw_reset_tsf - Force a TSF reset
560 * @ah: The &struct ath5k_hw
562 * Forces a TSF reset on PCU
564 void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
568 ATH5K_TRACE(ah->ah_sc);
570 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;
573 * Each write to the RESET_TSF bit toggles a hardware internal
574 * signal to reset TSF, but if left high it will cause a TSF reset
575 * on the next chip reset as well. Thus we always write the value
576 * twice to clear the signal.
578 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
579 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
583 * Initialize beacon timers
585 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
587 u32 timer1, timer2, timer3;
589 ATH5K_TRACE(ah->ah_sc);
591 * Set the additional timers by mode
593 switch (ah->ah_sc->opmode) {
594 case NL80211_IFTYPE_MONITOR:
595 case NL80211_IFTYPE_STATION:
596 /* In STA mode timer1 is used as next wakeup
597 * timer and timer2 as next CFP duration start
598 * timer. Both in 1/8TUs. */
599 /* TODO: PCF handling */
600 if (ah->ah_version == AR5K_AR5210) {
607 /* Mark associated AP as PCF incapable for now */
608 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF);
610 case NL80211_IFTYPE_ADHOC:
611 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM);
613 /* On non-STA modes timer1 is used as next DMA
614 * beacon alert (DBA) timer and timer2 as next
615 * software beacon alert. Both in 1/8TUs. */
616 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
617 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
621 /* Timer3 marks the end of our ATIM window
622 * a zero length window is not allowed because
623 * we 'll get no beacons */
624 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
627 * Set the beacon register and enable all timers.
629 /* When in AP or Mesh Point mode zero timer0 to start TSF */
630 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP ||
631 ah->ah_sc->opmode == NL80211_IFTYPE_MESH_POINT)
632 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
634 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
635 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
636 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
637 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
639 /* Force a TSF reset if requested and enable beacons */
640 if (interval & AR5K_BEACON_RESET_TSF)
641 ath5k_hw_reset_tsf(ah);
643 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
647 /* Flush any pending BMISS interrupts on ISR by
648 * performing a clear-on-write operation on PISR
649 * register for the BMISS bit (writing a bit on
650 * ISR togles a reset for that bit and leaves
651 * the rest bits intact) */
652 if (ah->ah_version == AR5K_AR5210)
653 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR);
655 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR);
657 /* TODO: Set enchanced sleep registers on AR5212
658 * based on vif->bss_conf params, until then
659 * disable power save reporting.*/
660 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV);
665 /*********************\
666 * Key table functions *
667 \*********************/
670 * Reset a key entry on the table
672 int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
674 unsigned int i, type;
675 u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET;
677 ATH5K_TRACE(ah->ah_sc);
678 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
680 type = ath5k_hw_reg_read(ah, AR5K_KEYTABLE_TYPE(entry));
682 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
683 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
685 /* Reset associated MIC entry if TKIP
686 * is enabled located at offset (entry + 64) */
687 if (type == AR5K_KEYTABLE_TYPE_TKIP) {
688 AR5K_ASSERT_ENTRY(micentry, AR5K_KEYTABLE_SIZE);
689 for (i = 0; i < AR5K_KEYCACHE_SIZE / 2 ; i++)
690 ath5k_hw_reg_write(ah, 0,
691 AR5K_KEYTABLE_OFF(micentry, i));
695 * Set NULL encryption on AR5212+
697 * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5)
698 * AR5K_KEYTABLE_TYPE_NULL -> 0x00000007
700 * Note2: Windows driver (ndiswrapper) sets this to
701 * 0x00000714 instead of 0x00000007
703 if (ah->ah_version >= AR5K_AR5211) {
704 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
705 AR5K_KEYTABLE_TYPE(entry));
707 if (type == AR5K_KEYTABLE_TYPE_TKIP) {
708 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
709 AR5K_KEYTABLE_TYPE(micentry));
717 int ath5k_keycache_type(const struct ieee80211_key_conf *key)
721 return AR5K_KEYTABLE_TYPE_TKIP;
723 return AR5K_KEYTABLE_TYPE_CCM;
725 if (key->keylen == WLAN_KEY_LEN_WEP40)
726 return AR5K_KEYTABLE_TYPE_40;
727 else if (key->keylen == WLAN_KEY_LEN_WEP104)
728 return AR5K_KEYTABLE_TYPE_104;
737 * Set a key entry on the table
739 int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
740 const struct ieee80211_key_conf *key, const u8 *mac)
744 __le32 key_v[5] = {};
745 __le32 key0 = 0, key1 = 0;
746 __le32 *rxmic, *txmic;
748 u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET;
752 ATH5K_TRACE(ah->ah_sc);
754 is_tkip = (key->alg == ALG_TKIP);
757 * key->keylen comes in from mac80211 in bytes.
758 * TKIP is 128 bit + 128 bit mic
760 keylen = (is_tkip) ? (128 / 8) : key->keylen;
762 if (entry > AR5K_KEYTABLE_SIZE ||
763 (is_tkip && micentry > AR5K_KEYTABLE_SIZE))
766 if (unlikely(keylen > 16))
769 keytype = ath5k_keycache_type(key);
774 * each key block is 6 bytes wide, written as pairs of
775 * alternating 32 and 16 bit le values.
778 for (i = 0; keylen >= 6; keylen -= 6) {
779 memcpy(&key_v[i], key_ptr, 6);
784 memcpy(&key_v[i], key_ptr, keylen);
786 /* intentionally corrupt key until mic is installed */
788 key0 = key_v[0] = ~key_v[0];
789 key1 = key_v[1] = ~key_v[1];
792 for (i = 0; i < ARRAY_SIZE(key_v); i++)
793 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
794 AR5K_KEYTABLE_OFF(entry, i));
796 ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry));
799 /* Install rx/tx MIC */
800 rxmic = (__le32 *) &key->key[16];
801 txmic = (__le32 *) &key->key[24];
803 if (ah->ah_combined_mic) {
805 key_v[1] = cpu_to_le32(le32_to_cpu(txmic[0]) >> 16);
807 key_v[3] = cpu_to_le32(le32_to_cpu(txmic[0]) & 0xffff);
816 for (i = 0; i < ARRAY_SIZE(key_v); i++)
817 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
818 AR5K_KEYTABLE_OFF(micentry, i));
820 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
821 AR5K_KEYTABLE_TYPE(micentry));
822 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC0(micentry));
823 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC1(micentry));
825 /* restore first 2 words of key */
826 ath5k_hw_reg_write(ah, le32_to_cpu(~key0),
827 AR5K_KEYTABLE_OFF(entry, 0));
828 ath5k_hw_reg_write(ah, le32_to_cpu(~key1),
829 AR5K_KEYTABLE_OFF(entry, 1));
832 return ath5k_hw_set_key_lladdr(ah, entry, mac);
835 int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac)
839 ATH5K_TRACE(ah->ah_sc);
840 /* Invalid entry (key table overflow) */
841 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
844 * MAC may be NULL if it's a broadcast key. In this case no need to
845 * to compute get_unaligned_le32 and get_unaligned_le16 as we
850 high_id = 0xffff | AR5K_KEYTABLE_VALID;
852 low_id = get_unaligned_le32(mac);
853 high_id = get_unaligned_le16(mac + 4) | AR5K_KEYTABLE_VALID;
856 ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry));
857 ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry));
863 * ath5k_hw_set_coverage_class - Set IEEE 802.11 coverage class
865 * @ah: The &struct ath5k_hw
866 * @coverage_class: IEEE 802.11 coverage class number
868 * Sets slot time, ACK timeout and CTS timeout for given coverage class.
870 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
872 /* As defined by IEEE 802.11-2007 17.3.8.6 */
873 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class;
874 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time;
875 int cts_timeout = ack_timeout;
877 ath5k_hw_set_slot_time(ah, slot_time);
878 ath5k_hw_set_ack_timeout(ah, ack_timeout);
879 ath5k_hw_set_cts_timeout(ah, cts_timeout);
881 ah->ah_coverage_class = coverage_class;