drivers/net/sfc/falcon.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2009 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/i2c.h>
  17 #include <linux/mii.h>
  18 #include <linux/slab.h>
  19 #include "net_driver.h"
  20 #include "bitfield.h"
  21 #include "efx.h"
  22 #include "mac.h"
  23 #include "spi.h"
  24 #include "nic.h"
  25 #include "regs.h"
  26 #include "io.h"
  27 #include "mdio_10g.h"
  28 #include "phy.h"
  29 #include "workarounds.h"
  30
  31 /* Hardware control for SFC4000 (aka Falcon). */
  32
  33 static const unsigned int
  34 /* "Large" EEPROM device: Atmel AT25640 or similar
  35  * 8 KB, 16-bit address, 32 B write block */
  36 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
  37                      | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  38                      | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
  39 /* Default flash device: Atmel AT25F1024
  40  * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
  41 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
  42                       | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  43                       | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
  44                       | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
  45                       | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
  46
  47 /**************************************************************************
  48  *
  49  * I2C bus - this is a bit-bashing interface using GPIO pins
  50  * Note that it uses the output enables to tristate the outputs
  51  * SDA is the data pin and SCL is the clock
  52  *
  53  **************************************************************************
  54  */
  55 static void falcon_setsda(void *data, int state)
  56 {
  57         struct efx_nic *efx = (struct efx_nic *)data;
  58         efx_oword_t reg;
  59
  60         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  61         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
  62         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
  63 }
  64
  65 static void falcon_setscl(void *data, int state)
  66 {
  67         struct efx_nic *efx = (struct efx_nic *)data;
  68         efx_oword_t reg;
  69
  70         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  71         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
  72         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
  73 }
  74
  75 static int falcon_getsda(void *data)
  76 {
  77         struct efx_nic *efx = (struct efx_nic *)data;
  78         efx_oword_t reg;
  79
  80         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  81         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
  82 }
  83
  84 static int falcon_getscl(void *data)
  85 {
  86         struct efx_nic *efx = (struct efx_nic *)data;
  87         efx_oword_t reg;
  88
  89         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  90         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
  91 }
  92
  93 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
  94         .setsda         = falcon_setsda,
  95         .setscl         = falcon_setscl,
  96         .getsda         = falcon_getsda,
  97         .getscl         = falcon_getscl,
  98         .udelay         = 5,
  99         /* Wait up to 50 ms for slave to let us pull SCL high */
 100         .timeout        = DIV_ROUND_UP(HZ, 20),
 101 };
 102
 103 static void falcon_push_irq_moderation(struct efx_channel *channel)
 104 {
 105         efx_dword_t timer_cmd;
 106         struct efx_nic *efx = channel->efx;
 107
 108         /* Set timer register */
 109         if (channel->irq_moderation) {
 110                 EFX_POPULATE_DWORD_2(timer_cmd,
 111                                      FRF_AB_TC_TIMER_MODE,
 112                                      FFE_BB_TIMER_MODE_INT_HLDOFF,
 113                                      FRF_AB_TC_TIMER_VAL,
 114                                      channel->irq_moderation - 1);
 115         } else {
 116                 EFX_POPULATE_DWORD_2(timer_cmd,
 117                                      FRF_AB_TC_TIMER_MODE,
 118                                      FFE_BB_TIMER_MODE_DIS,
 119                                      FRF_AB_TC_TIMER_VAL, 0);
 120         }
 121         BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
 122         efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
 123                                channel->channel);
 124 }
 125
 126 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
 127
 128 static void falcon_prepare_flush(struct efx_nic *efx)
 129 {
 130         falcon_deconfigure_mac_wrapper(efx);
 131
 132         /* Wait for the tx and rx fifo's to get to the next packet boundary
 133          * (~1ms without back-pressure), then to drain the remainder of the
 134          * fifo's at data path speeds (negligible), with a healthy margin. */
 135         msleep(10);
 136 }
 137
 138 /* Acknowledge a legacy interrupt from Falcon
 139  *
 140  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
 141  *
 142  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
 143  * BIU. Interrupt acknowledge is read sensitive so must write instead
 144  * (then read to ensure the BIU collector is flushed)
 145  *
 146  * NB most hardware supports MSI interrupts
 147  */
 148 inline void falcon_irq_ack_a1(struct efx_nic *efx)
 149 {
 150         efx_dword_t reg;
 151
 152         EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
 153         efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
 154         efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
 155 }
 156
 157
 158 irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
 159 {
 160         struct efx_nic *efx = dev_id;
 161         efx_oword_t *int_ker = efx->irq_status.addr;
 162         struct efx_channel *channel;
 163         int syserr;
 164         int queues;
 165
 166         /* Check to see if this is our interrupt.  If it isn't, we
 167          * exit without having touched the hardware.
 168          */
 169         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
 170                 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
 171                           raw_smp_processor_id());
 172                 return IRQ_NONE;
 173         }
 174         efx->last_irq_cpu = raw_smp_processor_id();
 175         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
 176                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
 177
 178         /* Determine interrupting queues, clear interrupt status
 179          * register and acknowledge the device interrupt.
 180          */
 181         BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
 182         queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
 183
 184         /* Check to see if we have a serious error condition */
 185         if (queues & (1U << efx->fatal_irq_level)) {
 186                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
 187                 if (unlikely(syserr))
 188                         return efx_nic_fatal_interrupt(efx);
 189         }
 190
 191         EFX_ZERO_OWORD(*int_ker);
 192         wmb(); /* Ensure the vector is cleared before interrupt ack */
 193         falcon_irq_ack_a1(efx);
 194
 195         /* Schedule processing of any interrupting queues */
 196         channel = &efx->channel[0];
 197         while (queues) {
 198                 if (queues & 0x01)
 199                         efx_schedule_channel(channel);
 200                 channel++;
 201                 queues >>= 1;
 202         }
 203
 204         return IRQ_HANDLED;
 205 }
 206 /**************************************************************************
 207  *
 208  * EEPROM/flash
 209  *
 210  **************************************************************************
 211  */
 212
 213 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
 214
 215 static int falcon_spi_poll(struct efx_nic *efx)
 216 {
 217         efx_oword_t reg;
 218         efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
 219         return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
 220 }
 221
 222 /* Wait for SPI command completion */
 223 static int falcon_spi_wait(struct efx_nic *efx)
 224 {
 225         /* Most commands will finish quickly, so we start polling at
 226          * very short intervals.  Sometimes the command may have to
 227          * wait for VPD or expansion ROM access outside of our
 228          * control, so we allow up to 100 ms. */
 229         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
 230         int i;
 231
 232         for (i = 0; i < 10; i++) {
 233                 if (!falcon_spi_poll(efx))
 234                         return 0;
 235                 udelay(10);
 236         }
 237
 238         for (;;) {
 239                 if (!falcon_spi_poll(efx))
 240                         return 0;
 241                 if (time_after_eq(jiffies, timeout)) {
 242                         EFX_ERR(efx, "timed out waiting for SPI\n");
 243                         return -ETIMEDOUT;
 244                 }
 245                 schedule_timeout_uninterruptible(1);
 246         }
 247 }
 248
 249 int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi,
 250                    unsigned int command, int address,
 251                    const void *in, void *out, size_t len)
 252 {
 253         bool addressed = (address >= 0);
 254         bool reading = (out != NULL);
 255         efx_oword_t reg;
 256         int rc;
 257
 258         /* Input validation */
 259         if (len > FALCON_SPI_MAX_LEN)
 260                 return -EINVAL;
 261         BUG_ON(!mutex_is_locked(&efx->spi_lock));
 262
 263         /* Check that previous command is not still running */
 264         rc = falcon_spi_poll(efx);
 265         if (rc)
 266                 return rc;
 267
 268         /* Program address register, if we have an address */
 269         if (addressed) {
 270                 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
 271                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
 272         }
 273
 274         /* Program data register, if we have data */
 275         if (in != NULL) {
 276                 memcpy(&reg, in, len);
 277                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
 278         }
 279
 280         /* Issue read/write command */
 281         EFX_POPULATE_OWORD_7(reg,
 282                              FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
 283                              FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
 284                              FRF_AB_EE_SPI_HCMD_DABCNT, len,
 285                              FRF_AB_EE_SPI_HCMD_READ, reading,
 286                              FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
 287                              FRF_AB_EE_SPI_HCMD_ADBCNT,
 288                              (addressed ? spi->addr_len : 0),
 289                              FRF_AB_EE_SPI_HCMD_ENC, command);
 290         efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
 291
 292         /* Wait for read/write to complete */
 293         rc = falcon_spi_wait(efx);
 294         if (rc)
 295                 return rc;
 296
 297         /* Read data */
 298         if (out != NULL) {
 299                 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
 300                 memcpy(out, &reg, len);
 301         }
 302
 303         return 0;
 304 }
 305
 306 static size_t
 307 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
 308 {
 309         return min(FALCON_SPI_MAX_LEN,
 310                    (spi->block_size - (start & (spi->block_size - 1))));
 311 }
 312
 313 static inline u8
 314 efx_spi_munge_command(const struct efx_spi_device *spi,
 315                       const u8 command, const unsigned int address)
 316 {
 317         return command | (((address >> 8) & spi->munge_address) << 3);
 318 }
 319
 320 /* Wait up to 10 ms for buffered write completion */
 321 int
 322 falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi)
 323 {
 324         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
 325         u8 status;
 326         int rc;
 327
 328         for (;;) {
 329                 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
 330                                     &status, sizeof(status));
 331                 if (rc)
 332                         return rc;
 333                 if (!(status & SPI_STATUS_NRDY))
 334                         return 0;
 335                 if (time_after_eq(jiffies, timeout)) {
 336                         EFX_ERR(efx, "SPI write timeout on device %d"
 337                                 " last status=0x%02x\n",
 338                                 spi->device_id, status);
 339                         return -ETIMEDOUT;
 340                 }
 341                 schedule_timeout_uninterruptible(1);
 342         }
 343 }
 344
 345 int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi,
 346                     loff_t start, size_t len, size_t *retlen, u8 *buffer)
 347 {
 348         size_t block_len, pos = 0;
 349         unsigned int command;
 350         int rc = 0;
 351
 352         while (pos < len) {
 353                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
 354
 355                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
 356                 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
 357                                     buffer + pos, block_len);
 358                 if (rc)
 359                         break;
 360                 pos += block_len;
 361
 362                 /* Avoid locking up the system */
 363                 cond_resched();
 364                 if (signal_pending(current)) {
 365                         rc = -EINTR;
 366                         break;
 367                 }
 368         }
 369
 370         if (retlen)
 371                 *retlen = pos;
 372         return rc;
 373 }
 374
 375 int
 376 falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi,
 377                  loff_t start, size_t len, size_t *retlen, const u8 *buffer)
 378 {
 379         u8 verify_buffer[FALCON_SPI_MAX_LEN];
 380         size_t block_len, pos = 0;
 381         unsigned int command;
 382         int rc = 0;
 383
 384         while (pos < len) {
 385                 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
 386                 if (rc)
 387                         break;
 388
 389                 block_len = min(len - pos,
 390                                 falcon_spi_write_limit(spi, start + pos));
 391                 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
 392                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
 393                                     buffer + pos, NULL, block_len);
 394                 if (rc)
 395                         break;
 396
 397                 rc = falcon_spi_wait_write(efx, spi);
 398                 if (rc)
 399                         break;
 400
 401                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
 402                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
 403                                     NULL, verify_buffer, block_len);
 404                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
 405                         rc = -EIO;
 406                         break;
 407                 }
 408
 409                 pos += block_len;
 410
 411                 /* Avoid locking up the system */
 412                 cond_resched();
 413                 if (signal_pending(current)) {
 414                         rc = -EINTR;
 415                         break;
 416                 }
 417         }
 418
 419         if (retlen)
 420                 *retlen = pos;
 421         return rc;
 422 }
 423
 424 /**************************************************************************
 425  *
 426  * MAC wrapper
 427  *
 428  **************************************************************************
 429  */
 430
 431 static void falcon_push_multicast_hash(struct efx_nic *efx)
 432 {
 433         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
 434
 435         WARN_ON(!mutex_is_locked(&efx->mac_lock));
 436
 437         efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
 438         efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
 439 }
 440
 441 static void falcon_reset_macs(struct efx_nic *efx)
 442 {
 443         struct falcon_nic_data *nic_data = efx->nic_data;
 444         efx_oword_t reg, mac_ctrl;
 445         int count;
 446
 447         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
 448                 /* It's not safe to use GLB_CTL_REG to reset the
 449                  * macs, so instead use the internal MAC resets
 450                  */
 451                 if (!EFX_IS10G(efx)) {
 452                         EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
 453                         efx_writeo(efx, &reg, FR_AB_GM_CFG1);
 454                         udelay(1000);
 455
 456                         EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
 457                         efx_writeo(efx, &reg, FR_AB_GM_CFG1);
 458                         udelay(1000);
 459                         return;
 460                 } else {
 461                         EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
 462                         efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
 463
 464                         for (count = 0; count < 10000; count++) {
 465                                 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
 466                                 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
 467                                     0)
 468                                         return;
 469                                 udelay(10);
 470                         }
 471
 472                         EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
 473                 }
 474         }
 475
 476         /* Mac stats will fail whist the TX fifo is draining */
 477         WARN_ON(nic_data->stats_disable_count == 0);
 478
 479         efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
 480         EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
 481         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
 482
 483         efx_reado(efx, &reg, FR_AB_GLB_CTL);
 484         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
 485         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
 486         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
 487         efx_writeo(efx, &reg, FR_AB_GLB_CTL);
 488
 489         count = 0;
 490         while (1) {
 491                 efx_reado(efx, &reg, FR_AB_GLB_CTL);
 492                 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
 493                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
 494                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
 495                         EFX_LOG(efx, "Completed MAC reset after %d loops\n",
 496                                 count);
 497                         break;
 498                 }
 499                 if (count > 20) {
 500                         EFX_ERR(efx, "MAC reset failed\n");
 501                         break;
 502                 }
 503                 count++;
 504                 udelay(10);
 505         }
 506
 507         /* Ensure the correct MAC is selected before statistics
 508          * are re-enabled by the caller */
 509         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
 510
 511         /* This can run even when the GMAC is selected */
 512         falcon_setup_xaui(efx);
 513 }
 514
 515 void falcon_drain_tx_fifo(struct efx_nic *efx)
 516 {
 517         efx_oword_t reg;
 518
 519         if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
 520             (efx->loopback_mode != LOOPBACK_NONE))
 521                 return;
 522
 523         efx_reado(efx, &reg, FR_AB_MAC_CTRL);
 524         /* There is no point in draining more than once */
 525         if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
 526                 return;
 527
 528         falcon_reset_macs(efx);
 529 }
 530
 531 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
 532 {
 533         efx_oword_t reg;
 534
 535         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
 536                 return;
 537
 538         /* Isolate the MAC -> RX */
 539         efx_reado(efx, &reg, FR_AZ_RX_CFG);
 540         EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
 541         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
 542
 543         /* Isolate TX -> MAC */
 544         falcon_drain_tx_fifo(efx);
 545 }
 546
 547 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
 548 {
 549         struct efx_link_state *link_state = &efx->link_state;
 550         efx_oword_t reg;
 551         int link_speed;
 552
 553         switch (link_state->speed) {
 554         case 10000: link_speed = 3; break;
 555         case 1000:  link_speed = 2; break;
 556         case 100:   link_speed = 1; break;
 557         default:    link_speed = 0; break;
 558         }
 559         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
 560          * as advertised.  Disable to ensure packets are not
 561          * indefinitely held and TX queue can be flushed at any point
 562          * while the link is down. */
 563         EFX_POPULATE_OWORD_5(reg,
 564                              FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
 565                              FRF_AB_MAC_BCAD_ACPT, 1,
 566                              FRF_AB_MAC_UC_PROM, efx->promiscuous,
 567                              FRF_AB_MAC_LINK_STATUS, 1, /* always set */
 568                              FRF_AB_MAC_SPEED, link_speed);
 569         /* On B0, MAC backpressure can be disabled and packets get
 570          * discarded. */
 571         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
 572                 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
 573                                     !link_state->up);
 574         }
 575
 576         efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
 577
 578         /* Restore the multicast hash registers. */
 579         falcon_push_multicast_hash(efx);
 580
 581         efx_reado(efx, &reg, FR_AZ_RX_CFG);
 582         /* Enable XOFF signal from RX FIFO (we enabled it during NIC
 583          * initialisation but it may read back as 0) */
 584         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
 585         /* Unisolate the MAC -> RX */
 586         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
 587                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
 588         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
 589 }
 590
 591 static void falcon_stats_request(struct efx_nic *efx)
 592 {
 593         struct falcon_nic_data *nic_data = efx->nic_data;
 594         efx_oword_t reg;
 595
 596         WARN_ON(nic_data->stats_pending);
 597         WARN_ON(nic_data->stats_disable_count);
 598
 599         if (nic_data->stats_dma_done == NULL)
 600                 return; /* no mac selected */
 601
 602         *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE;
 603         nic_data->stats_pending = true;
 604         wmb(); /* ensure done flag is clear */
 605
 606         /* Initiate DMA transfer of stats */
 607         EFX_POPULATE_OWORD_2(reg,
 608                              FRF_AB_MAC_STAT_DMA_CMD, 1,
 609                              FRF_AB_MAC_STAT_DMA_ADR,
 610                              efx->stats_buffer.dma_addr);
 611         efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
 612
 613         mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
 614 }
 615
 616 static void falcon_stats_complete(struct efx_nic *efx)
 617 {
 618         struct falcon_nic_data *nic_data = efx->nic_data;
 619
 620         if (!nic_data->stats_pending)
 621                 return;
 622
 623         nic_data->stats_pending = 0;
 624         if (*nic_data->stats_dma_done == FALCON_STATS_DONE) {
 625                 rmb(); /* read the done flag before the stats */
 626                 efx->mac_op->update_stats(efx);
 627         } else {
 628                 EFX_ERR(efx, "timed out waiting for statistics\n");
 629         }
 630 }
 631
 632 static void falcon_stats_timer_func(unsigned long context)
 633 {
 634         struct efx_nic *efx = (struct efx_nic *)context;
 635         struct falcon_nic_data *nic_data = efx->nic_data;
 636
 637         spin_lock(&efx->stats_lock);
 638
 639         falcon_stats_complete(efx);
 640         if (nic_data->stats_disable_count == 0)
 641                 falcon_stats_request(efx);
 642
 643         spin_unlock(&efx->stats_lock);
 644 }
 645
 646 static void falcon_switch_mac(struct efx_nic *efx);
 647
 648 static bool falcon_loopback_link_poll(struct efx_nic *efx)
 649 {
 650         struct efx_link_state old_state = efx->link_state;
 651
 652         WARN_ON(!mutex_is_locked(&efx->mac_lock));
 653         WARN_ON(!LOOPBACK_INTERNAL(efx));
 654
 655         efx->link_state.fd = true;
 656         efx->link_state.fc = efx->wanted_fc;
 657         efx->link_state.up = true;
 658
 659         if (efx->loopback_mode == LOOPBACK_GMAC)
 660                 efx->link_state.speed = 1000;
 661         else
 662                 efx->link_state.speed = 10000;
 663
 664         return !efx_link_state_equal(&efx->link_state, &old_state);
 665 }
 666
 667 static int falcon_reconfigure_port(struct efx_nic *efx)
 668 {
 669         int rc;
 670
 671         WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
 672
 673         /* Poll the PHY link state *before* reconfiguring it. This means we
 674          * will pick up the correct speed (in loopback) to select the correct
 675          * MAC.
 676          */
 677         if (LOOPBACK_INTERNAL(efx))
 678                 falcon_loopback_link_poll(efx);
 679         else
 680                 efx->phy_op->poll(efx);
 681
 682         falcon_stop_nic_stats(efx);
 683         falcon_deconfigure_mac_wrapper(efx);
 684
 685         falcon_switch_mac(efx);
 686
 687         efx->phy_op->reconfigure(efx);
 688         rc = efx->mac_op->reconfigure(efx);
 689         BUG_ON(rc);
 690
 691         falcon_start_nic_stats(efx);
 692
 693         /* Synchronise efx->link_state with the kernel */
 694         efx_link_status_changed(efx);
 695
 696         return 0;
 697 }
 698
 699 /**************************************************************************
 700  *
 701  * PHY access via GMII
 702  *
 703  **************************************************************************
 704  */
 705
 706 /* Wait for GMII access to complete */
 707 static int falcon_gmii_wait(struct efx_nic *efx)
 708 {
 709         efx_oword_t md_stat;
 710         int count;
 711
 712         /* wait upto 50ms - taken max from datasheet */
 713         for (count = 0; count < 5000; count++) {
 714                 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
 715                 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
 716                         if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
 717                             EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
 718                                 EFX_ERR(efx, "error from GMII access "
 719                                         EFX_OWORD_FMT"\n",
 720                                         EFX_OWORD_VAL(md_stat));
 721                                 return -EIO;
 722                         }
 723                         return 0;
 724                 }
 725                 udelay(10);
 726         }
 727         EFX_ERR(efx, "timed out waiting for GMII\n");
 728         return -ETIMEDOUT;
 729 }
 730
 731 /* Write an MDIO register of a PHY connected to Falcon. */
 732 static int falcon_mdio_write(struct net_device *net_dev,
 733                              int prtad, int devad, u16 addr, u16 value)
 734 {
 735         struct efx_nic *efx = netdev_priv(net_dev);
 736         efx_oword_t reg;
 737         int rc;
 738
 739         EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
 740                     prtad, devad, addr, value);
 741
 742         mutex_lock(&efx->mdio_lock);
 743
 744         /* Check MDIO not currently being accessed */
 745         rc = falcon_gmii_wait(efx);
 746         if (rc)
 747                 goto out;
 748
 749         /* Write the address/ID register */
 750         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
 751         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
 752
 753         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
 754                              FRF_AB_MD_DEV_ADR, devad);
 755         efx_writeo(efx, &reg, FR_AB_MD_ID);
 756
 757         /* Write data */
 758         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
 759         efx_writeo(efx, &reg, FR_AB_MD_TXD);
 760
 761         EFX_POPULATE_OWORD_2(reg,
 762                              FRF_AB_MD_WRC, 1,
 763                              FRF_AB_MD_GC, 0);
 764         efx_writeo(efx, &reg, FR_AB_MD_CS);
 765
 766         /* Wait for data to be written */
 767         rc = falcon_gmii_wait(efx);
 768         if (rc) {
 769                 /* Abort the write operation */
 770                 EFX_POPULATE_OWORD_2(reg,
 771                                      FRF_AB_MD_WRC, 0,
 772                                      FRF_AB_MD_GC, 1);
 773                 efx_writeo(efx, &reg, FR_AB_MD_CS);
 774                 udelay(10);
 775         }
 776
 777 out:
 778         mutex_unlock(&efx->mdio_lock);
 779         return rc;
 780 }
 781
 782 /* Read an MDIO register of a PHY connected to Falcon. */
 783 static int falcon_mdio_read(struct net_device *net_dev,
 784                             int prtad, int devad, u16 addr)
 785 {
 786         struct efx_nic *efx = netdev_priv(net_dev);
 787         efx_oword_t reg;
 788         int rc;
 789
 790         mutex_lock(&efx->mdio_lock);
 791
 792         /* Check MDIO not currently being accessed */
 793         rc = falcon_gmii_wait(efx);
 794         if (rc)
 795                 goto out;
 796
 797         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
 798         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
 799
 800         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
 801                              FRF_AB_MD_DEV_ADR, devad);
 802         efx_writeo(efx, &reg, FR_AB_MD_ID);
 803
 804         /* Request data to be read */
 805         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
 806         efx_writeo(efx, &reg, FR_AB_MD_CS);
 807
 808         /* Wait for data to become available */
 809         rc = falcon_gmii_wait(efx);
 810         if (rc == 0) {
 811                 efx_reado(efx, &reg, FR_AB_MD_RXD);
 812                 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
 813                 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
 814                             prtad, devad, addr, rc);
 815         } else {
 816                 /* Abort the read operation */
 817                 EFX_POPULATE_OWORD_2(reg,
 818                                      FRF_AB_MD_RIC, 0,
 819                                      FRF_AB_MD_GC, 1);
 820                 efx_writeo(efx, &reg, FR_AB_MD_CS);
 821
 822                 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
 823                         prtad, devad, addr, rc);
 824         }
 825
 826 out:
 827         mutex_unlock(&efx->mdio_lock);
 828         return rc;
 829 }
 830
 831 static void falcon_clock_mac(struct efx_nic *efx)
 832 {
 833         unsigned strap_val;
 834         efx_oword_t nic_stat;
 835
 836         /* Configure the NIC generated MAC clock correctly */
 837         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
 838         strap_val = EFX_IS10G(efx) ? 5 : 3;
 839         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
 840                 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
 841                 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
 842                 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
 843         } else {
 844                 /* Falcon A1 does not support 1G/10G speed switching
 845                  * and must not be used with a PHY that does. */
 846                 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
 847                        strap_val);
 848         }
 849 }
 850
 851 static void falcon_switch_mac(struct efx_nic *efx)
 852 {
 853         struct efx_mac_operations *old_mac_op = efx->mac_op;
 854         struct falcon_nic_data *nic_data = efx->nic_data;
 855         unsigned int stats_done_offset;
 856
 857         WARN_ON(!mutex_is_locked(&efx->mac_lock));
 858         WARN_ON(nic_data->stats_disable_count == 0);
 859
 860         efx->mac_op = (EFX_IS10G(efx) ?
 861                        &falcon_xmac_operations : &falcon_gmac_operations);
 862
 863         if (EFX_IS10G(efx))
 864                 stats_done_offset = XgDmaDone_offset;
 865         else
 866                 stats_done_offset = GDmaDone_offset;
 867         nic_data->stats_dma_done = efx->stats_buffer.addr + stats_done_offset;
 868
 869         if (old_mac_op == efx->mac_op)
 870                 return;
 871
 872         falcon_clock_mac(efx);
 873
 874         EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
 875         /* Not all macs support a mac-level link state */
 876         efx->xmac_poll_required = false;
 877         falcon_reset_macs(efx);
 878 }
 879
 880 /* This call is responsible for hooking in the MAC and PHY operations */
 881 static int falcon_probe_port(struct efx_nic *efx)
 882 {
 883         int rc;
 884
 885         switch (efx->phy_type) {
 886         case PHY_TYPE_SFX7101:
 887                 efx->phy_op = &falcon_sfx7101_phy_ops;
 888                 break;
 889         case PHY_TYPE_SFT9001A:
 890         case PHY_TYPE_SFT9001B:
 891                 efx->phy_op = &falcon_sft9001_phy_ops;
 892                 break;
 893         case PHY_TYPE_QT2022C2:
 894         case PHY_TYPE_QT2025C:
 895                 efx->phy_op = &falcon_qt202x_phy_ops;
 896                 break;
 897         default:
 898                 EFX_ERR(efx, "Unknown PHY type %d\n",
 899                         efx->phy_type);
 900                 return -ENODEV;
 901         }
 902
 903         /* Fill out MDIO structure and loopback modes */
 904         efx->mdio.mdio_read = falcon_mdio_read;
 905         efx->mdio.mdio_write = falcon_mdio_write;
 906         rc = efx->phy_op->probe(efx);
 907         if (rc != 0)
 908                 return rc;
 909
 910         /* Initial assumption */
 911         efx->link_state.speed = 10000;
 912         efx->link_state.fd = true;
 913
 914         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
 915         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
 916                 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
 917         else
 918                 efx->wanted_fc = EFX_FC_RX;
 919         if (efx->mdio.mmds & MDIO_DEVS_AN)
 920                 efx->wanted_fc |= EFX_FC_AUTO;
 921
 922         /* Allocate buffer for stats */
 923         rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
 924                                   FALCON_MAC_STATS_SIZE);
 925         if (rc)
 926                 return rc;
 927         EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
 928                 (u64)efx->stats_buffer.dma_addr,
 929                 efx->stats_buffer.addr,
 930                 (u64)virt_to_phys(efx->stats_buffer.addr));
 931
 932         return 0;
 933 }
 934
 935 static void falcon_remove_port(struct efx_nic *efx)
 936 {
 937         efx->phy_op->remove(efx);
 938         efx_nic_free_buffer(efx, &efx->stats_buffer);
 939 }
 940
 941 /**************************************************************************
 942  *
 943  * Falcon test code
 944  *
 945  **************************************************************************/
 946
 947 static int
 948 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
 949 {
 950         struct falcon_nvconfig *nvconfig;
 951         struct efx_spi_device *spi;
 952         void *region;
 953         int rc, magic_num, struct_ver;
 954         __le16 *word, *limit;
 955         u32 csum;
 956
 957         spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
 958         if (!spi)
 959                 return -EINVAL;
 960
 961         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
 962         if (!region)
 963                 return -ENOMEM;
 964         nvconfig = region + FALCON_NVCONFIG_OFFSET;
 965
 966         mutex_lock(&efx->spi_lock);
 967         rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
 968         mutex_unlock(&efx->spi_lock);
 969         if (rc) {
 970                 EFX_ERR(efx, "Failed to read %s\n",
 971                         efx->spi_flash ? "flash" : "EEPROM");
 972                 rc = -EIO;
 973                 goto out;
 974         }
 975
 976         magic_num = le16_to_cpu(nvconfig->board_magic_num);
 977         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
 978
 979         rc = -EINVAL;
 980         if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
 981                 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
 982                 goto out;
 983         }
 984         if (struct_ver < 2) {
 985                 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
 986                 goto out;
 987         } else if (struct_ver < 4) {
 988                 word = &nvconfig->board_magic_num;
 989                 limit = (__le16 *) (nvconfig + 1);
 990         } else {
 991                 word = region;
 992                 limit = region + FALCON_NVCONFIG_END;
 993         }
 994         for (csum = 0; word < limit; ++word)
 995                 csum += le16_to_cpu(*word);
 996
 997         if (~csum & 0xffff) {
 998                 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
 999                 goto out;
1000         }
1001
1002         rc = 0;
1003         if (nvconfig_out)
1004                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
1005
1006  out:
1007         kfree(region);
1008         return rc;
1009 }
1010
1011 static int falcon_test_nvram(struct efx_nic *efx)
1012 {
1013         return falcon_read_nvram(efx, NULL);
1014 }
1015
1016 static const struct efx_nic_register_test falcon_b0_register_tests[] = {
1017         { FR_AZ_ADR_REGION,
1018           EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
1019         { FR_AZ_RX_CFG,
1020           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
1021         { FR_AZ_TX_CFG,
1022           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
1023         { FR_AZ_TX_RESERVED,
1024           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
1025         { FR_AB_MAC_CTRL,
1026           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
1027         { FR_AZ_SRM_TX_DC_CFG,
1028           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
1029         { FR_AZ_RX_DC_CFG,
1030           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
1031         { FR_AZ_RX_DC_PF_WM,
1032           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
1033         { FR_BZ_DP_CTRL,
1034           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
1035         { FR_AB_GM_CFG2,
1036           EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
1037         { FR_AB_GMF_CFG0,
1038           EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
1039         { FR_AB_XM_GLB_CFG,
1040           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
1041         { FR_AB_XM_TX_CFG,
1042           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
1043         { FR_AB_XM_RX_CFG,
1044           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
1045         { FR_AB_XM_RX_PARAM,
1046           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
1047         { FR_AB_XM_FC,
1048           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
1049         { FR_AB_XM_ADR_LO,
1050           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
1051         { FR_AB_XX_SD_CTL,
1052           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
1053 };
1054
1055 static int falcon_b0_test_registers(struct efx_nic *efx)
1056 {
1057         return efx_nic_test_registers(efx, falcon_b0_register_tests,
1058                                       ARRAY_SIZE(falcon_b0_register_tests));
1059 }
1060
1061 /**************************************************************************
1062  *
1063  * Device reset
1064  *
1065  **************************************************************************
1066  */
1067
1068 /* Resets NIC to known state.  This routine must be called in process
1069  * context and is allowed to sleep. */
1070 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1071 {
1072         struct falcon_nic_data *nic_data = efx->nic_data;
1073         efx_oword_t glb_ctl_reg_ker;
1074         int rc;
1075
1076         EFX_LOG(efx, "performing %s hardware reset\n", RESET_TYPE(method));
1077
1078         /* Initiate device reset */
1079         if (method == RESET_TYPE_WORLD) {
1080                 rc = pci_save_state(efx->pci_dev);
1081                 if (rc) {
1082                         EFX_ERR(efx, "failed to backup PCI state of primary "
1083                                 "function prior to hardware reset\n");
1084                         goto fail1;
1085                 }
1086                 if (efx_nic_is_dual_func(efx)) {
1087                         rc = pci_save_state(nic_data->pci_dev2);
1088                         if (rc) {
1089                                 EFX_ERR(efx, "failed to backup PCI state of "
1090                                         "secondary function prior to "
1091                                         "hardware reset\n");
1092                                 goto fail2;
1093                         }
1094                 }
1095
1096                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
1097                                      FRF_AB_EXT_PHY_RST_DUR,
1098                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
1099                                      FRF_AB_SWRST, 1);
1100         } else {
1101                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
1102                                      /* exclude PHY from "invisible" reset */
1103                                      FRF_AB_EXT_PHY_RST_CTL,
1104                                      method == RESET_TYPE_INVISIBLE,
1105                                      /* exclude EEPROM/flash and PCIe */
1106                                      FRF_AB_PCIE_CORE_RST_CTL, 1,
1107                                      FRF_AB_PCIE_NSTKY_RST_CTL, 1,
1108                                      FRF_AB_PCIE_SD_RST_CTL, 1,
1109                                      FRF_AB_EE_RST_CTL, 1,
1110                                      FRF_AB_EXT_PHY_RST_DUR,
1111                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
1112                                      FRF_AB_SWRST, 1);
1113         }
1114         efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1115
1116         EFX_LOG(efx, "waiting for hardware reset\n");
1117         schedule_timeout_uninterruptible(HZ / 20);
1118
1119         /* Restore PCI configuration if needed */
1120         if (method == RESET_TYPE_WORLD) {
1121                 if (efx_nic_is_dual_func(efx)) {
1122                         rc = pci_restore_state(nic_data->pci_dev2);
1123                         if (rc) {
1124                                 EFX_ERR(efx, "failed to restore PCI config for "
1125                                         "the secondary function\n");
1126                                 goto fail3;
1127                         }
1128                 }
1129                 rc = pci_restore_state(efx->pci_dev);
1130                 if (rc) {
1131                         EFX_ERR(efx, "failed to restore PCI config for the "
1132                                 "primary function\n");
1133                         goto fail4;
1134                 }
1135                 EFX_LOG(efx, "successfully restored PCI config\n");
1136         }
1137
1138         /* Assert that reset complete */
1139         efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1140         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
1141                 rc = -ETIMEDOUT;
1142                 EFX_ERR(efx, "timed out waiting for hardware reset\n");
1143                 goto fail5;
1144         }
1145         EFX_LOG(efx, "hardware reset complete\n");
1146
1147         return 0;
1148
1149         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
1150 fail2:
1151 fail3:
1152         pci_restore_state(efx->pci_dev);
1153 fail1:
1154 fail4:
1155 fail5:
1156         return rc;
1157 }
1158
1159 static void falcon_monitor(struct efx_nic *efx)
1160 {
1161         bool link_changed;
1162         int rc;
1163
1164         BUG_ON(!mutex_is_locked(&efx->mac_lock));
1165
1166         rc = falcon_board(efx)->type->monitor(efx);
1167         if (rc) {
1168                 EFX_ERR(efx, "Board sensor %s; shutting down PHY\n",
1169                         (rc == -ERANGE) ? "reported fault" : "failed");
1170                 efx->phy_mode |= PHY_MODE_LOW_POWER;
1171                 rc = __efx_reconfigure_port(efx);
1172                 WARN_ON(rc);
1173         }
1174
1175         if (LOOPBACK_INTERNAL(efx))
1176                 link_changed = falcon_loopback_link_poll(efx);
1177         else
1178                 link_changed = efx->phy_op->poll(efx);
1179
1180         if (link_changed) {
1181                 falcon_stop_nic_stats(efx);
1182                 falcon_deconfigure_mac_wrapper(efx);
1183
1184                 falcon_switch_mac(efx);
1185                 rc = efx->mac_op->reconfigure(efx);
1186                 BUG_ON(rc);
1187
1188                 falcon_start_nic_stats(efx);
1189
1190                 efx_link_status_changed(efx);
1191         }
1192
1193         if (EFX_IS10G(efx))
1194                 falcon_poll_xmac(efx);
1195 }
1196
1197 /* Zeroes out the SRAM contents.  This routine must be called in
1198  * process context and is allowed to sleep.
1199  */
1200 static int falcon_reset_sram(struct efx_nic *efx)
1201 {
1202         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
1203         int count;
1204
1205         /* Set the SRAM wake/sleep GPIO appropriately. */
1206         efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1207         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
1208         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
1209         efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1210
1211         /* Initiate SRAM reset */
1212         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
1213                              FRF_AZ_SRM_INIT_EN, 1,
1214                              FRF_AZ_SRM_NB_SZ, 0);
1215         efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1216
1217         /* Wait for SRAM reset to complete */
1218         count = 0;
1219         do {
1220                 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
1221
1222                 /* SRAM reset is slow; expect around 16ms */
1223                 schedule_timeout_uninterruptible(HZ / 50);
1224
1225                 /* Check for reset complete */
1226                 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1227                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
1228                         EFX_LOG(efx, "SRAM reset complete\n");
1229
1230                         return 0;
1231                 }
1232         } while (++count < 20); /* wait upto 0.4 sec */
1233
1234         EFX_ERR(efx, "timed out waiting for SRAM reset\n");
1235         return -ETIMEDOUT;
1236 }
1237
1238 static int falcon_spi_device_init(struct efx_nic *efx,
1239                                   struct efx_spi_device **spi_device_ret,
1240                                   unsigned int device_id, u32 device_type)
1241 {
1242         struct efx_spi_device *spi_device;
1243
1244         if (device_type != 0) {
1245                 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
1246                 if (!spi_device)
1247                         return -ENOMEM;
1248                 spi_device->device_id = device_id;
1249                 spi_device->size =
1250                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
1251                 spi_device->addr_len =
1252                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
1253                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
1254                                              spi_device->addr_len == 1);
1255                 spi_device->erase_command =
1256                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
1257                 spi_device->erase_size =
1258                         1 << SPI_DEV_TYPE_FIELD(device_type,
1259                                                 SPI_DEV_TYPE_ERASE_SIZE);
1260                 spi_device->block_size =
1261                         1 << SPI_DEV_TYPE_FIELD(device_type,
1262                                                 SPI_DEV_TYPE_BLOCK_SIZE);
1263         } else {
1264                 spi_device = NULL;
1265         }
1266
1267         kfree(*spi_device_ret);
1268         *spi_device_ret = spi_device;
1269         return 0;
1270 }
1271
1272 static void falcon_remove_spi_devices(struct efx_nic *efx)
1273 {
1274         kfree(efx->spi_eeprom);
1275         efx->spi_eeprom = NULL;
1276         kfree(efx->spi_flash);
1277         efx->spi_flash = NULL;
1278 }
1279
1280 /* Extract non-volatile configuration */
1281 static int falcon_probe_nvconfig(struct efx_nic *efx)
1282 {
1283         struct falcon_nvconfig *nvconfig;
1284         int board_rev;
1285         int rc;
1286
1287         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
1288         if (!nvconfig)
1289                 return -ENOMEM;
1290
1291         rc = falcon_read_nvram(efx, nvconfig);
1292         if (rc == -EINVAL) {
1293                 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
1294                 efx->phy_type = PHY_TYPE_NONE;
1295                 efx->mdio.prtad = MDIO_PRTAD_NONE;
1296                 board_rev = 0;
1297                 rc = 0;
1298         } else if (rc) {
1299                 goto fail1;
1300         } else {
1301                 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
1302                 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
1303
1304                 efx->phy_type = v2->port0_phy_type;
1305                 efx->mdio.prtad = v2->port0_phy_addr;
1306                 board_rev = le16_to_cpu(v2->board_revision);
1307
1308                 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
1309                         rc = falcon_spi_device_init(
1310                                 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
1311                                 le32_to_cpu(v3->spi_device_type
1312                                             [FFE_AB_SPI_DEVICE_FLASH]));
1313                         if (rc)
1314                                 goto fail2;
1315                         rc = falcon_spi_device_init(
1316                                 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
1317                                 le32_to_cpu(v3->spi_device_type
1318                                             [FFE_AB_SPI_DEVICE_EEPROM]));
1319                         if (rc)
1320                                 goto fail2;
1321                 }
1322         }
1323
1324         /* Read the MAC addresses */
1325         memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
1326
1327         EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
1328
1329         rc = falcon_probe_board(efx, board_rev);
1330         if (rc)
1331                 goto fail2;
1332
1333         kfree(nvconfig);
1334         return 0;
1335
1336  fail2:
1337         falcon_remove_spi_devices(efx);
1338  fail1:
1339         kfree(nvconfig);
1340         return rc;
1341 }
1342
1343 /* Probe all SPI devices on the NIC */
1344 static void falcon_probe_spi_devices(struct efx_nic *efx)
1345 {
1346         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
1347         int boot_dev;
1348
1349         efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
1350         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1351         efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1352
1353         if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
1354                 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
1355                             FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
1356                 EFX_LOG(efx, "Booted from %s\n",
1357                         boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
1358         } else {
1359                 /* Disable VPD and set clock dividers to safe
1360                  * values for initial programming. */
1361                 boot_dev = -1;
1362                 EFX_LOG(efx, "Booted from internal ASIC settings;"
1363                         " setting SPI config\n");
1364                 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
1365                                      /* 125 MHz / 7 ~= 20 MHz */
1366                                      FRF_AB_EE_SF_CLOCK_DIV, 7,
1367                                      /* 125 MHz / 63 ~= 2 MHz */
1368                                      FRF_AB_EE_EE_CLOCK_DIV, 63);
1369                 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1370         }
1371
1372         if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
1373                 falcon_spi_device_init(efx, &efx->spi_flash,
1374                                        FFE_AB_SPI_DEVICE_FLASH,
1375                                        default_flash_type);
1376         if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
1377                 falcon_spi_device_init(efx, &efx->spi_eeprom,
1378                                        FFE_AB_SPI_DEVICE_EEPROM,
1379                                        large_eeprom_type);
1380 }
1381
1382 static int falcon_probe_nic(struct efx_nic *efx)
1383 {
1384         struct falcon_nic_data *nic_data;
1385         struct falcon_board *board;
1386         int rc;
1387
1388         /* Allocate storage for hardware specific data */
1389         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1390         if (!nic_data)
1391                 return -ENOMEM;
1392         efx->nic_data = nic_data;
1393
1394         rc = -ENODEV;
1395
1396         if (efx_nic_fpga_ver(efx) != 0) {
1397                 EFX_ERR(efx, "Falcon FPGA not supported\n");
1398                 goto fail1;
1399         }
1400
1401         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1402                 efx_oword_t nic_stat;
1403                 struct pci_dev *dev;
1404                 u8 pci_rev = efx->pci_dev->revision;
1405
1406                 if ((pci_rev == 0xff) || (pci_rev == 0)) {
1407                         EFX_ERR(efx, "Falcon rev A0 not supported\n");
1408                         goto fail1;
1409                 }
1410                 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1411                 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
1412                         EFX_ERR(efx, "Falcon rev A1 1G not supported\n");
1413                         goto fail1;
1414                 }
1415                 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
1416                         EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
1417                         goto fail1;
1418                 }
1419
1420                 dev = pci_dev_get(efx->pci_dev);
1421                 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
1422                                              dev))) {
1423                         if (dev->bus == efx->pci_dev->bus &&
1424                             dev->devfn == efx->pci_dev->devfn + 1) {
1425                                 nic_data->pci_dev2 = dev;
1426                                 break;
1427                         }
1428                 }
1429                 if (!nic_data->pci_dev2) {
1430                         EFX_ERR(efx, "failed to find secondary function\n");
1431                         rc = -ENODEV;
1432                         goto fail2;
1433                 }
1434         }
1435
1436         /* Now we can reset the NIC */
1437         rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
1438         if (rc) {
1439                 EFX_ERR(efx, "failed to reset NIC\n");
1440                 goto fail3;
1441         }
1442
1443         /* Allocate memory for INT_KER */
1444         rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
1445         if (rc)
1446                 goto fail4;
1447         BUG_ON(efx->irq_status.dma_addr & 0x0f);
1448
1449         EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
1450                 (u64)efx->irq_status.dma_addr,
1451                 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
1452
1453         falcon_probe_spi_devices(efx);
1454
1455         /* Read in the non-volatile configuration */
1456         rc = falcon_probe_nvconfig(efx);
1457         if (rc)
1458                 goto fail5;
1459
1460         /* Initialise I2C adapter */
1461         board = falcon_board(efx);
1462         board->i2c_adap.owner = THIS_MODULE;
1463         board->i2c_data = falcon_i2c_bit_operations;
1464         board->i2c_data.data = efx;
1465         board->i2c_adap.algo_data = &board->i2c_data;
1466         board->i2c_adap.dev.parent = &efx->pci_dev->dev;
1467         strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
1468                 sizeof(board->i2c_adap.name));
1469         rc = i2c_bit_add_bus(&board->i2c_adap);
1470         if (rc)
1471                 goto fail5;
1472
1473         rc = falcon_board(efx)->type->init(efx);
1474         if (rc) {
1475                 EFX_ERR(efx, "failed to initialise board\n");
1476                 goto fail6;
1477         }
1478
1479         nic_data->stats_disable_count = 1;
1480         setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
1481                     (unsigned long)efx);
1482
1483         return 0;
1484
1485  fail6:
1486         BUG_ON(i2c_del_adapter(&board->i2c_adap));
1487         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1488  fail5:
1489         falcon_remove_spi_devices(efx);
1490         efx_nic_free_buffer(efx, &efx->irq_status);
1491  fail4:
1492  fail3:
1493         if (nic_data->pci_dev2) {
1494                 pci_dev_put(nic_data->pci_dev2);
1495                 nic_data->pci_dev2 = NULL;
1496         }
1497  fail2:
1498  fail1:
1499         kfree(efx->nic_data);
1500         return rc;
1501 }
1502
1503 static void falcon_init_rx_cfg(struct efx_nic *efx)
1504 {
1505         /* Prior to Siena the RX DMA engine will split each frame at
1506          * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
1507          * be so large that that never happens. */
1508         const unsigned huge_buf_size = (3 * 4096) >> 5;
1509         /* RX control FIFO thresholds (32 entries) */
1510         const unsigned ctrl_xon_thr = 20;
1511         const unsigned ctrl_xoff_thr = 25;
1512         /* RX data FIFO thresholds (256-byte units; size varies) */
1513         int data_xon_thr = efx_nic_rx_xon_thresh >> 8;
1514         int data_xoff_thr = efx_nic_rx_xoff_thresh >> 8;
1515         efx_oword_t reg;
1516
1517         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1518         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1519                 /* Data FIFO size is 5.5K */
1520                 if (data_xon_thr < 0)
1521                         data_xon_thr = 512 >> 8;
1522                 if (data_xoff_thr < 0)
1523                         data_xoff_thr = 2048 >> 8;
1524                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
1525                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
1526                                     huge_buf_size);
1527                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
1528                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
1529                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
1530                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
1531         } else {
1532                 /* Data FIFO size is 80K; register fields moved */
1533                 if (data_xon_thr < 0)
1534                         data_xon_thr = 27648 >> 8; /* ~3*max MTU */
1535                 if (data_xoff_thr < 0)
1536                         data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
1537                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
1538                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
1539                                     huge_buf_size);
1540                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
1541                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
1542                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
1543                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
1544                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1545         }
1546         /* Always enable XOFF signal from RX FIFO.  We enable
1547          * or disable transmission of pause frames at the MAC. */
1548         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1549         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1550 }
1551
1552 /* This call performs hardware-specific global initialisation, such as
1553  * defining the descriptor cache sizes and number of RSS channels.
1554  * It does not set up any buffers, descriptor rings or event queues.
1555  */
1556 static int falcon_init_nic(struct efx_nic *efx)
1557 {
1558         efx_oword_t temp;
1559         int rc;
1560
1561         /* Use on-chip SRAM */
1562         efx_reado(efx, &temp, FR_AB_NIC_STAT);
1563         EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
1564         efx_writeo(efx, &temp, FR_AB_NIC_STAT);
1565
1566         /* Set the source of the GMAC clock */
1567         if (efx_nic_rev(efx) == EFX_REV_FALCON_B0) {
1568                 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
1569                 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
1570                 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
1571         }
1572
1573         /* Select the correct MAC */
1574         falcon_clock_mac(efx);
1575
1576         rc = falcon_reset_sram(efx);
1577         if (rc)
1578                 return rc;
1579
1580         /* Clear the parity enables on the TX data fifos as
1581          * they produce false parity errors because of timing issues
1582          */
1583         if (EFX_WORKAROUND_5129(efx)) {
1584                 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
1585                 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
1586                 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
1587         }
1588
1589         if (EFX_WORKAROUND_7244(efx)) {
1590                 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
1591                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
1592                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
1593                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
1594                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
1595                 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
1596         }
1597
1598         /* XXX This is documented only for Falcon A0/A1 */
1599         /* Setup RX.  Wait for descriptor is broken and must
1600          * be disabled.  RXDP recovery shouldn't be needed, but is.
1601          */
1602         efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
1603         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
1604         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
1605         if (EFX_WORKAROUND_5583(efx))
1606                 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
1607         efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
1608
1609         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
1610          * descriptors (which is bad).
1611          */
1612         efx_reado(efx, &temp, FR_AZ_TX_CFG);
1613         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
1614         efx_writeo(efx, &temp, FR_AZ_TX_CFG);
1615
1616         falcon_init_rx_cfg(efx);
1617
1618         /* Set destination of both TX and RX Flush events */
1619         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1620                 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
1621                 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
1622         }
1623
1624         efx_nic_init_common(efx);
1625
1626         return 0;
1627 }
1628
1629 static void falcon_remove_nic(struct efx_nic *efx)
1630 {
1631         struct falcon_nic_data *nic_data = efx->nic_data;
1632         struct falcon_board *board = falcon_board(efx);
1633         int rc;
1634
1635         board->type->fini(efx);
1636
1637         /* Remove I2C adapter and clear it in preparation for a retry */
1638         rc = i2c_del_adapter(&board->i2c_adap);
1639         BUG_ON(rc);
1640         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1641
1642         falcon_remove_spi_devices(efx);
1643         efx_nic_free_buffer(efx, &efx->irq_status);
1644
1645         falcon_reset_hw(efx, RESET_TYPE_ALL);
1646
1647         /* Release the second function after the reset */
1648         if (nic_data->pci_dev2) {
1649                 pci_dev_put(nic_data->pci_dev2);
1650                 nic_data->pci_dev2 = NULL;
1651         }
1652
1653         /* Tear down the private nic state */
1654         kfree(efx->nic_data);
1655         efx->nic_data = NULL;
1656 }
1657
1658 static void falcon_update_nic_stats(struct efx_nic *efx)
1659 {
1660         struct falcon_nic_data *nic_data = efx->nic_data;
1661         efx_oword_t cnt;
1662
1663         if (nic_data->stats_disable_count)
1664                 return;
1665
1666         efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
1667         efx->n_rx_nodesc_drop_cnt +=
1668                 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
1669
1670         if (nic_data->stats_pending &&
1671             *nic_data->stats_dma_done == FALCON_STATS_DONE) {
1672                 nic_data->stats_pending = false;
1673                 rmb(); /* read the done flag before the stats */
1674                 efx->mac_op->update_stats(efx);
1675         }
1676 }
1677
1678 void falcon_start_nic_stats(struct efx_nic *efx)
1679 {
1680         struct falcon_nic_data *nic_data = efx->nic_data;
1681
1682         spin_lock_bh(&efx->stats_lock);
1683         if (--nic_data->stats_disable_count == 0)
1684                 falcon_stats_request(efx);
1685         spin_unlock_bh(&efx->stats_lock);
1686 }
1687
1688 void falcon_stop_nic_stats(struct efx_nic *efx)
1689 {
1690         struct falcon_nic_data *nic_data = efx->nic_data;
1691         int i;
1692
1693         might_sleep();
1694
1695         spin_lock_bh(&efx->stats_lock);
1696         ++nic_data->stats_disable_count;
1697         spin_unlock_bh(&efx->stats_lock);
1698
1699         del_timer_sync(&nic_data->stats_timer);
1700
1701         /* Wait enough time for the most recent transfer to
1702          * complete. */
1703         for (i = 0; i < 4 && nic_data->stats_pending; i++) {
1704                 if (*nic_data->stats_dma_done == FALCON_STATS_DONE)
1705                         break;
1706                 msleep(1);
1707         }
1708
1709         spin_lock_bh(&efx->stats_lock);
1710         falcon_stats_complete(efx);
1711         spin_unlock_bh(&efx->stats_lock);
1712 }
1713
1714 static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
1715 {
1716         falcon_board(efx)->type->set_id_led(efx, mode);
1717 }
1718
1719 /**************************************************************************
1720  *
1721  * Wake on LAN
1722  *
1723  **************************************************************************
1724  */
1725
1726 static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1727 {
1728         wol->supported = 0;
1729         wol->wolopts = 0;
1730         memset(&wol->sopass, 0, sizeof(wol->sopass));
1731 }
1732
1733 static int falcon_set_wol(struct efx_nic *efx, u32 type)
1734 {
1735         if (type != 0)
1736                 return -EINVAL;
1737         return 0;
1738 }
1739
1740 /**************************************************************************
1741  *
1742  * Revision-dependent attributes used by efx.c and nic.c
1743  *
1744  **************************************************************************
1745  */
1746
1747 struct efx_nic_type falcon_a1_nic_type = {
1748         .probe = falcon_probe_nic,
1749         .remove = falcon_remove_nic,
1750         .init = falcon_init_nic,
1751         .fini = efx_port_dummy_op_void,
1752         .monitor = falcon_monitor,
1753         .reset = falcon_reset_hw,
1754         .probe_port = falcon_probe_port,
1755         .remove_port = falcon_remove_port,
1756         .prepare_flush = falcon_prepare_flush,
1757         .update_stats = falcon_update_nic_stats,
1758         .start_stats = falcon_start_nic_stats,
1759         .stop_stats = falcon_stop_nic_stats,
1760         .set_id_led = falcon_set_id_led,
1761         .push_irq_moderation = falcon_push_irq_moderation,
1762         .push_multicast_hash = falcon_push_multicast_hash,
1763         .reconfigure_port = falcon_reconfigure_port,
1764         .get_wol = falcon_get_wol,
1765         .set_wol = falcon_set_wol,
1766         .resume_wol = efx_port_dummy_op_void,
1767         .test_nvram = falcon_test_nvram,
1768         .default_mac_ops = &falcon_xmac_operations,
1769
1770         .revision = EFX_REV_FALCON_A1,
1771         .mem_map_size = 0x20000,
1772         .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
1773         .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
1774         .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
1775         .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
1776         .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
1777         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1778         .rx_buffer_padding = 0x24,
1779         .max_interrupt_mode = EFX_INT_MODE_MSI,
1780         .phys_addr_channels = 4,
1781         .tx_dc_base = 0x130000,
1782         .rx_dc_base = 0x100000,
1783         .offload_features = NETIF_F_IP_CSUM,
1784         .reset_world_flags = ETH_RESET_IRQ,
1785 };
1786
1787 struct efx_nic_type falcon_b0_nic_type = {
1788         .probe = falcon_probe_nic,
1789         .remove = falcon_remove_nic,
1790         .init = falcon_init_nic,
1791         .fini = efx_port_dummy_op_void,
1792         .monitor = falcon_monitor,
1793         .reset = falcon_reset_hw,
1794         .probe_port = falcon_probe_port,
1795         .remove_port = falcon_remove_port,
1796         .prepare_flush = falcon_prepare_flush,
1797         .update_stats = falcon_update_nic_stats,
1798         .start_stats = falcon_start_nic_stats,
1799         .stop_stats = falcon_stop_nic_stats,
1800         .set_id_led = falcon_set_id_led,
1801         .push_irq_moderation = falcon_push_irq_moderation,
1802         .push_multicast_hash = falcon_push_multicast_hash,
1803         .reconfigure_port = falcon_reconfigure_port,
1804         .get_wol = falcon_get_wol,
1805         .set_wol = falcon_set_wol,
1806         .resume_wol = efx_port_dummy_op_void,
1807         .test_registers = falcon_b0_test_registers,
1808         .test_nvram = falcon_test_nvram,
1809         .default_mac_ops = &falcon_xmac_operations,
1810
1811         .revision = EFX_REV_FALCON_B0,
1812         /* Map everything up to and including the RSS indirection
1813          * table.  Don't map MSI-X table, MSI-X PBA since Linux
1814          * requires that they not be mapped.  */
1815         .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
1816                          FR_BZ_RX_INDIRECTION_TBL_STEP *
1817                          FR_BZ_RX_INDIRECTION_TBL_ROWS),
1818         .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1819         .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1820         .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1821         .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1822         .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1823         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1824         .rx_buffer_padding = 0,
1825         .max_interrupt_mode = EFX_INT_MODE_MSIX,
1826         .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
1827                                    * interrupt handler only supports 32
1828                                    * channels */
1829         .tx_dc_base = 0x130000,
1830         .rx_dc_base = 0x100000,
1831         .offload_features = NETIF_F_IP_CSUM,
1832         .reset_world_flags = ETH_RESET_IRQ,
1833 };
1834