2 * Kernel support for the ptrace() and syscall tracing interfaces.
4 * Copyright (C) 1999-2003 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Derived from the x86 and Alpha versions. Most of the code in here
8 * could actually be factored into a common set of routines.
10 #include <linux/config.h>
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/slab.h>
15 #include <linux/errno.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp_lock.h>
18 #include <linux/user.h>
19 #include <linux/security.h>
21 #include <asm/pgtable.h>
22 #include <asm/processor.h>
23 #include <asm/ptrace_offsets.h>
25 #include <asm/system.h>
26 #include <asm/uaccess.h>
27 #include <asm/unwind.h>
29 #include <asm/perfmon.h>
33 * Bits in the PSR that we allow ptrace() to change:
34 * be, up, ac, mfl, mfh (the user mask; five bits total)
35 * db (debug breakpoint fault; one bit)
36 * id (instruction debug fault disable; one bit)
37 * dd (data debug fault disable; one bit)
38 * ri (restart instruction; two bits)
39 * is (instruction set; one bit)
41 #define IPSR_WRITE_MASK \
42 (IA64_PSR_UM | IA64_PSR_DB | IA64_PSR_IS | IA64_PSR_ID | IA64_PSR_DD | IA64_PSR_RI)
43 #define IPSR_READ_MASK IPSR_WRITE_MASK
45 #define PTRACE_DEBUG 1
48 # define dprintk(format...) printk(format)
51 # define dprintk(format...)
55 * Collect the NaT bits for r1-r31 from scratch_unat and return a NaT
56 * bitset where bit i is set iff the NaT bit of register i is set.
59 ia64_get_scratch_nat_bits (struct pt_regs *pt, unsigned long scratch_unat)
61 # define GET_BITS(first, last, unat) \
63 unsigned long bit = ia64_unat_pos(&pt->r##first); \
64 unsigned long mask = ((1UL << (last - first + 1)) - 1) << first; \
65 (ia64_rotl(unat, first) >> bit) & mask; \
69 val = GET_BITS( 1, 3, scratch_unat);
70 val |= GET_BITS(12, 15, scratch_unat);
71 val |= GET_BITS( 8, 11, scratch_unat);
72 val |= GET_BITS(16, 31, scratch_unat);
79 * Set the NaT bits for the scratch registers according to NAT and
80 * return the resulting unat (assuming the scratch registers are
84 ia64_put_scratch_nat_bits (struct pt_regs *pt, unsigned long nat)
86 unsigned long scratch_unat;
88 # define PUT_BITS(first, last, nat) \
90 unsigned long bit = ia64_unat_pos(&pt->r##first); \
91 unsigned long mask = ((1UL << (last - first + 1)) - 1) << bit; \
92 (ia64_rotr(nat, first) << bit) & mask; \
94 scratch_unat = PUT_BITS( 1, 3, nat);
95 scratch_unat |= PUT_BITS(12, 15, nat);
96 scratch_unat |= PUT_BITS( 8, 11, nat);
97 scratch_unat |= PUT_BITS(16, 31, nat);
104 #define IA64_MLX_TEMPLATE 0x2
105 #define IA64_MOVL_OPCODE 6
108 ia64_increment_ip (struct pt_regs *regs)
110 unsigned long w0, ri = ia64_psr(regs)->ri + 1;
115 } else if (ri == 2) {
116 get_user(w0, (char *) regs->cr_iip + 0);
117 if (((w0 >> 1) & 0xf) == IA64_MLX_TEMPLATE) {
119 * rfi'ing to slot 2 of an MLX bundle causes
120 * an illegal operation fault. We don't want
127 ia64_psr(regs)->ri = ri;
131 ia64_decrement_ip (struct pt_regs *regs)
133 unsigned long w0, ri = ia64_psr(regs)->ri - 1;
135 if (ia64_psr(regs)->ri == 0) {
138 get_user(w0, (char *) regs->cr_iip + 0);
139 if (((w0 >> 1) & 0xf) == IA64_MLX_TEMPLATE) {
141 * rfi'ing to slot 2 of an MLX bundle causes
142 * an illegal operation fault. We don't want
148 ia64_psr(regs)->ri = ri;
152 * This routine is used to read an rnat bits that are stored on the kernel backing store.
153 * Since, in general, the alignment of the user and kernel are different, this is not
154 * completely trivial. In essence, we need to construct the user RNAT based on up to two
155 * kernel RNAT values and/or the RNAT value saved in the child's pt_regs.
159 * +--------+ <-- lowest address
166 * | slot01 | > child_regs->ar_rnat
168 * | slot02 | / kernel rbs
169 * +--------+ +--------+
170 * <- child_regs->ar_bspstore | slot61 | <-- krbs
171 * +- - - - + +--------+
173 * +- - - - + +--------+
175 * +- - - - + +--------+
177 * +- - - - + +--------+
182 * | slot01 | > child_stack->ar_rnat
186 * <--- child_stack->ar_bspstore
188 * The way to think of this code is as follows: bit 0 in the user rnat corresponds to some
189 * bit N (0 <= N <= 62) in one of the kernel rnat value. The kernel rnat value holding
190 * this bit is stored in variable rnat0. rnat1 is loaded with the kernel rnat value that
191 * form the upper bits of the user rnat value.
195 * o when reading the rnat "below" the first rnat slot on the kernel backing store,
196 * rnat0/rnat1 are set to 0 and the low order bits are merged in from pt->ar_rnat.
198 * o when reading the rnat "above" the last rnat slot on the kernel backing store,
199 * rnat0/rnat1 gets its value from sw->ar_rnat.
202 get_rnat (struct pt_regs *pt, struct switch_stack *sw,
203 unsigned long *krbs, unsigned long *urnat_addr)
205 unsigned long rnat0 = 0, rnat1 = 0, urnat = 0, *slot0_kaddr, kmask = ~0UL;
206 unsigned long *kbsp, *ubspstore, *rnat0_kaddr, *rnat1_kaddr, shift;
209 kbsp = (unsigned long *) sw->ar_bspstore;
210 ubspstore = (unsigned long *) pt->ar_bspstore;
212 * First, figure out which bit number slot 0 in user-land maps
213 * to in the kernel rnat. Do this by figuring out how many
214 * register slots we're beyond the user's backingstore and
215 * then computing the equivalent address in kernel space.
217 num_regs = ia64_rse_num_regs(ubspstore, urnat_addr + 1);
218 slot0_kaddr = ia64_rse_skip_regs(krbs, num_regs);
219 shift = ia64_rse_slot_num(slot0_kaddr);
220 rnat1_kaddr = ia64_rse_rnat_addr(slot0_kaddr);
221 rnat0_kaddr = rnat1_kaddr - 64;
223 if (ubspstore + 63 > urnat_addr) {
224 /* some bits need to be merged in from pt->ar_rnat */
225 kmask = ~((1UL << ia64_rse_slot_num(ubspstore)) - 1);
226 urnat = (pt->ar_rnat & ~kmask);
228 if (rnat0_kaddr >= kbsp) {
230 } else if (rnat0_kaddr > krbs) {
231 rnat0 = *rnat0_kaddr;
233 if (rnat1_kaddr >= kbsp) {
235 } else if (rnat1_kaddr > krbs) {
236 rnat1 = *rnat1_kaddr;
238 urnat |= ((rnat1 << (63 - shift)) | (rnat0 >> shift)) & kmask;
243 * The reverse of get_rnat.
246 put_rnat (struct pt_regs *pt, struct switch_stack *sw,
247 unsigned long *krbs, unsigned long *urnat_addr, unsigned long urnat)
249 unsigned long rnat0 = 0, rnat1 = 0, rnat = 0, *slot0_kaddr, kmask = ~0UL, mask;
250 unsigned long *kbsp, *ubspstore, *rnat0_kaddr, *rnat1_kaddr, shift;
253 kbsp = (unsigned long *) sw->ar_bspstore;
254 ubspstore = (unsigned long *) pt->ar_bspstore;
256 * First, figure out which bit number slot 0 in user-land maps
257 * to in the kernel rnat. Do this by figuring out how many
258 * register slots we're beyond the user's backingstore and
259 * then computing the equivalent address in kernel space.
261 num_regs = (long) ia64_rse_num_regs(ubspstore, urnat_addr + 1);
262 slot0_kaddr = ia64_rse_skip_regs(krbs, num_regs);
263 shift = ia64_rse_slot_num(slot0_kaddr);
264 rnat1_kaddr = ia64_rse_rnat_addr(slot0_kaddr);
265 rnat0_kaddr = rnat1_kaddr - 64;
267 if (ubspstore + 63 > urnat_addr) {
268 /* some bits need to be place in pt->ar_rnat: */
269 kmask = ~((1UL << ia64_rse_slot_num(ubspstore)) - 1);
270 pt->ar_rnat = (pt->ar_rnat & kmask) | (rnat & ~kmask);
273 * Note: Section 11.1 of the EAS guarantees that bit 63 of an
274 * rnat slot is ignored. so we don't have to clear it here.
276 rnat0 = (urnat << shift);
277 mask = ~0UL << shift;
278 if (rnat0_kaddr >= kbsp) {
279 sw->ar_rnat = (sw->ar_rnat & ~mask) | (rnat0 & mask);
280 } else if (rnat0_kaddr > krbs) {
281 *rnat0_kaddr = ((*rnat0_kaddr & ~mask) | (rnat0 & mask));
284 rnat1 = (urnat >> (63 - shift));
285 mask = ~0UL >> (63 - shift);
286 if (rnat1_kaddr >= kbsp) {
287 sw->ar_rnat = (sw->ar_rnat & ~mask) | (rnat1 & mask);
288 } else if (rnat1_kaddr > krbs) {
289 *rnat1_kaddr = ((*rnat1_kaddr & ~mask) | (rnat1 & mask));
294 * Read a word from the user-level backing store of task CHILD. ADDR is the user-level
295 * address to read the word from, VAL a pointer to the return value, and USER_BSP gives
296 * the end of the user-level backing store (i.e., it's the address that would be in ar.bsp
297 * after the user executed a "cover" instruction).
299 * This routine takes care of accessing the kernel register backing store for those
300 * registers that got spilled there. It also takes care of calculating the appropriate
301 * RNaT collection words.
304 ia64_peek (struct task_struct *child, struct switch_stack *child_stack, unsigned long user_rbs_end,
305 unsigned long addr, long *val)
307 unsigned long *bspstore, *krbs, regnum, *laddr, *urbs_end, *rnat_addr;
308 struct pt_regs *child_regs;
312 urbs_end = (long *) user_rbs_end;
313 laddr = (unsigned long *) addr;
314 child_regs = ia64_task_regs(child);
315 bspstore = (unsigned long *) child_regs->ar_bspstore;
316 krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
317 if (laddr >= bspstore && laddr <= ia64_rse_rnat_addr(urbs_end)) {
319 * Attempt to read the RBS in an area that's actually on the kernel RBS =>
320 * read the corresponding bits in the kernel RBS.
322 rnat_addr = ia64_rse_rnat_addr(laddr);
323 ret = get_rnat(child_regs, child_stack, krbs, rnat_addr);
325 if (laddr == rnat_addr) {
326 /* return NaT collection word itself */
331 if (((1UL << ia64_rse_slot_num(laddr)) & ret) != 0) {
333 * It is implementation dependent whether the data portion of a
334 * NaT value gets saved on a st8.spill or RSE spill (e.g., see
335 * EAS 2.6, 4.4.4.6 Register Spill and Fill). To get consistent
336 * behavior across all possible IA-64 implementations, we return
343 if (laddr < urbs_end) {
344 /* the desired word is on the kernel RBS and is not a NaT */
345 regnum = ia64_rse_num_regs(bspstore, laddr);
346 *val = *ia64_rse_skip_regs(krbs, regnum);
350 copied = access_process_vm(child, addr, &ret, sizeof(ret), 0);
351 if (copied != sizeof(ret))
358 ia64_poke (struct task_struct *child, struct switch_stack *child_stack, unsigned long user_rbs_end,
359 unsigned long addr, long val)
361 unsigned long *bspstore, *krbs, regnum, *laddr, *urbs_end = (long *) user_rbs_end;
362 struct pt_regs *child_regs;
364 laddr = (unsigned long *) addr;
365 child_regs = ia64_task_regs(child);
366 bspstore = (unsigned long *) child_regs->ar_bspstore;
367 krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
368 if (laddr >= bspstore && laddr <= ia64_rse_rnat_addr(urbs_end)) {
370 * Attempt to write the RBS in an area that's actually on the kernel RBS
371 * => write the corresponding bits in the kernel RBS.
373 if (ia64_rse_is_rnat_slot(laddr))
374 put_rnat(child_regs, child_stack, krbs, laddr, val);
376 if (laddr < urbs_end) {
377 regnum = ia64_rse_num_regs(bspstore, laddr);
378 *ia64_rse_skip_regs(krbs, regnum) = val;
381 } else if (access_process_vm(child, addr, &val, sizeof(val), 1) != sizeof(val)) {
388 * Calculate the address of the end of the user-level register backing store. This is the
389 * address that would have been stored in ar.bsp if the user had executed a "cover"
390 * instruction right before entering the kernel. If CFMP is not NULL, it is used to
391 * return the "current frame mask" that was active at the time the kernel was entered.
394 ia64_get_user_rbs_end (struct task_struct *child, struct pt_regs *pt, unsigned long *cfmp)
396 unsigned long *krbs, *bspstore, cfm;
397 struct unw_frame_info info;
400 krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
401 bspstore = (unsigned long *) pt->ar_bspstore;
402 ndirty = ia64_rse_num_regs(krbs, krbs + (pt->loadrs >> 19));
403 cfm = pt->cr_ifs & ~(1UL << 63);
405 if ((long) pt->cr_ifs >= 0) {
407 * If bit 63 of cr.ifs is cleared, the kernel was entered via a system
408 * call and we need to recover the CFM that existed on entry to the
409 * kernel by unwinding the kernel stack.
411 unw_init_from_blocked_task(&info, child);
412 if (unw_unwind_to_user(&info) == 0) {
413 unw_get_cfm(&info, &cfm);
414 ndirty += (cfm & 0x7f);
419 return (unsigned long) ia64_rse_skip_regs(bspstore, ndirty);
423 * Synchronize (i.e, write) the RSE backing store living in kernel space to the VM of the
424 * CHILD task. SW and PT are the pointers to the switch_stack and pt_regs structures,
425 * respectively. USER_RBS_END is the user-level address at which the backing store ends.
428 ia64_sync_user_rbs (struct task_struct *child, struct switch_stack *sw,
429 unsigned long user_rbs_start, unsigned long user_rbs_end)
431 unsigned long addr, val;
434 /* now copy word for word from kernel rbs to user rbs: */
435 for (addr = user_rbs_start; addr < user_rbs_end; addr += 8) {
436 ret = ia64_peek(child, sw, user_rbs_end, addr, &val);
439 if (access_process_vm(child, addr, &val, sizeof(val), 1) != sizeof(val))
446 * Simulate user-level "flushrs". Note: we can't just add pt->loadrs>>16 to
447 * pt->ar_bspstore because the kernel backing store and the user-level backing store may
448 * have different alignments (and therefore a different number of intervening rnat slots).
451 user_flushrs (struct task_struct *task, struct pt_regs *pt)
456 krbs = (unsigned long *) task + IA64_RBS_OFFSET/8;
457 ndirty = ia64_rse_num_regs(krbs, krbs + (pt->loadrs >> 19));
459 pt->ar_bspstore = (unsigned long) ia64_rse_skip_regs((unsigned long *) pt->ar_bspstore,
465 sync_user_rbs_one_thread (struct task_struct *p, int make_writable)
467 struct switch_stack *sw;
468 unsigned long urbs_end;
471 sw = (struct switch_stack *) (p->thread.ksp + 16);
472 pt = ia64_task_regs(p);
473 urbs_end = ia64_get_user_rbs_end(p, pt, NULL);
474 ia64_sync_user_rbs(p, sw, pt->ar_bspstore, urbs_end);
480 struct task_list *next;
481 struct task_struct *task;
487 collect_task (struct task_list **listp, struct task_struct *p, int make_writable)
491 e = kmalloc(sizeof(*e), GFP_KERNEL);
493 /* oops, can't collect more: finish at least what we collected so far... */
502 static inline struct task_list *
503 finish_task (struct task_list *list, int make_writable)
505 struct task_list *next = list->next;
507 sync_user_rbs_one_thread(list->task, make_writable);
508 put_task_struct(list->task);
514 # define collect_task(list, p, make_writable) sync_user_rbs_one_thread(p, make_writable)
515 # define finish_task(list, make_writable) (NULL)
519 * Synchronize the RSE backing store of CHILD and all tasks that share the address space
520 * with it. CHILD_URBS_END is the address of the end of the register backing store of
521 * CHILD. If MAKE_WRITABLE is set, a user-level "flushrs" is simulated such that the VM
522 * can be written via ptrace() and the tasks will pick up the newly written values. It
523 * would be OK to unconditionally simulate a "flushrs", but this would be more intrusive
524 * than strictly necessary (e.g., it would make it impossible to obtain the original value
528 threads_sync_user_rbs (struct task_struct *child, unsigned long child_urbs_end, int make_writable)
530 struct switch_stack *sw;
531 struct task_struct *g, *p;
532 struct mm_struct *mm;
539 multi_threaded = mm && (atomic_read(&mm->mm_users) > 1);
543 if (!multi_threaded) {
544 sw = (struct switch_stack *) (child->thread.ksp + 16);
545 pt = ia64_task_regs(child);
546 ia64_sync_user_rbs(child, sw, pt->ar_bspstore, child_urbs_end);
548 user_flushrs(child, pt);
551 * Note: we can't call ia64_sync_user_rbs() while holding the
552 * tasklist_lock because that may cause a dead-lock: ia64_sync_user_rbs()
553 * may indirectly call tlb_flush_all(), which triggers an IPI.
554 * Furthermore, tasklist_lock is acquired by fork() with interrupts
555 * disabled, so with the right timing, the IPI never completes, hence
556 * tasklist_lock never gets released, hence fork() never completes...
558 struct task_list *list = NULL;
560 read_lock(&tasklist_lock);
562 do_each_thread(g, p) {
563 if (p->mm == mm && p->state != TASK_RUNNING)
564 collect_task(&list, p, make_writable);
565 } while_each_thread(g, p);
567 read_unlock(&tasklist_lock);
570 list = finish_task(list, make_writable);
572 child->thread.flags |= IA64_THREAD_KRBS_SYNCED; /* set the flag in the child thread only */
576 * Write f32-f127 back to task->thread.fph if it has been modified.
579 ia64_flush_fph (struct task_struct *task)
581 struct ia64_psr *psr = ia64_psr(ia64_task_regs(task));
583 struct task_struct *fpu_owner = current;
585 struct task_struct *fpu_owner = ia64_get_fpu_owner();
588 if (task == fpu_owner && psr->mfh) {
590 ia64_save_fpu(&task->thread.fph[0]);
591 task->thread.flags |= IA64_THREAD_FPH_VALID;
596 * Sync the fph state of the task so that it can be manipulated
597 * through thread.fph. If necessary, f32-f127 are written back to
598 * thread.fph or, if the fph state hasn't been used before, thread.fph
599 * is cleared to zeroes. Also, access to f32-f127 is disabled to
600 * ensure that the task picks up the state from thread.fph when it
604 ia64_sync_fph (struct task_struct *task)
606 struct ia64_psr *psr = ia64_psr(ia64_task_regs(task));
608 ia64_flush_fph(task);
609 if (!(task->thread.flags & IA64_THREAD_FPH_VALID)) {
610 task->thread.flags |= IA64_THREAD_FPH_VALID;
611 memset(&task->thread.fph, 0, sizeof(task->thread.fph));
614 if (ia64_get_fpu_owner() == task)
615 ia64_set_fpu_owner(0);
621 access_fr (struct unw_frame_info *info, int regnum, int hi, unsigned long *data, int write_access)
623 struct ia64_fpreg fpval;
626 ret = unw_get_fr(info, regnum, &fpval);
631 fpval.u.bits[hi] = *data;
632 ret = unw_set_fr(info, regnum, fpval);
634 *data = fpval.u.bits[hi];
639 access_uarea (struct task_struct *child, unsigned long addr, unsigned long *data, int write_access)
641 unsigned long *ptr, regnum, urbs_end, rnat_addr;
642 struct switch_stack *sw;
643 struct unw_frame_info info;
646 pt = ia64_task_regs(child);
647 sw = (struct switch_stack *) (child->thread.ksp + 16);
649 if ((addr & 0x7) != 0) {
650 dprintk("ptrace: unaligned register address 0x%lx\n", addr);
654 if (addr < PT_F127 + 16) {
657 ia64_sync_fph(child);
659 ia64_flush_fph(child);
660 ptr = (unsigned long *) ((unsigned long) &child->thread.fph + addr);
661 } else if (addr >= PT_F10 && addr < PT_F15 + 16) {
662 /* scratch registers untouched by kernel (saved in switch_stack) */
663 ptr = (unsigned long *) ((long) sw + addr - PT_NAT_BITS);
664 } else if (addr < PT_AR_LC + 8) {
665 /* preserved state: */
666 unsigned long nat_bits, scratch_unat, dummy = 0;
667 struct unw_frame_info info;
671 unw_init_from_blocked_task(&info, child);
672 if (unw_unwind_to_user(&info) < 0)
679 scratch_unat = ia64_put_scratch_nat_bits(pt, nat_bits);
680 if (unw_set_ar(&info, UNW_AR_UNAT, scratch_unat) < 0) {
681 dprintk("ptrace: failed to set ar.unat\n");
684 for (regnum = 4; regnum <= 7; ++regnum) {
685 unw_get_gr(&info, regnum, &dummy, &nat);
686 unw_set_gr(&info, regnum, dummy, (nat_bits >> regnum) & 1);
689 if (unw_get_ar(&info, UNW_AR_UNAT, &scratch_unat) < 0) {
690 dprintk("ptrace: failed to read ar.unat\n");
693 nat_bits = ia64_get_scratch_nat_bits(pt, scratch_unat);
694 for (regnum = 4; regnum <= 7; ++regnum) {
695 unw_get_gr(&info, regnum, &dummy, &nat);
696 nat_bits |= (nat != 0) << regnum;
702 case PT_R4: case PT_R5: case PT_R6: case PT_R7:
704 /* read NaT bit first: */
705 ret = unw_get_gr(&info, (addr - PT_R4)/8 + 4, data, &nat);
709 return unw_access_gr(&info, (addr - PT_R4)/8 + 4, data, &nat,
712 case PT_B1: case PT_B2: case PT_B3: case PT_B4: case PT_B5:
713 return unw_access_br(&info, (addr - PT_B1)/8 + 1, data, write_access);
716 return unw_access_ar(&info, UNW_AR_EC, data, write_access);
719 return unw_access_ar(&info, UNW_AR_LC, data, write_access);
722 if (addr >= PT_F2 && addr < PT_F5 + 16)
723 return access_fr(&info, (addr - PT_F2)/16 + 2, (addr & 8) != 0,
725 else if (addr >= PT_F16 && addr < PT_F31 + 16)
726 return access_fr(&info, (addr - PT_F16)/16 + 16, (addr & 8) != 0,
729 dprintk("ptrace: rejecting access to register address 0x%lx\n",
734 } else if (addr < PT_F9+16) {
739 * By convention, we use PT_AR_BSP to refer to the end of the user-level
740 * backing store. Use ia64_rse_skip_regs(PT_AR_BSP, -CFM.sof) to get
741 * the real value of ar.bsp at the time the kernel was entered.
743 urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
745 if (*data != urbs_end) {
746 if (ia64_sync_user_rbs(child, sw,
747 pt->ar_bspstore, urbs_end) < 0)
749 /* simulate user-level write of ar.bsp: */
751 pt->ar_bspstore = *data;
758 if ((long) pt->cr_ifs < 0) {
760 pt->cr_ifs = ((pt->cr_ifs & ~0x3fffffffffUL)
761 | (*data & 0x3fffffffffUL));
763 *data = pt->cr_ifs & 0x3fffffffffUL;
765 /* kernel was entered through a system call */
768 unw_init_from_blocked_task(&info, child);
769 if (unw_unwind_to_user(&info) < 0)
772 unw_get_cfm(&info, &cfm);
774 unw_set_cfm(&info, ((cfm & ~0x3fffffffffU)
775 | (*data & 0x3fffffffffUL)));
783 pt->cr_ipsr = ((*data & IPSR_WRITE_MASK)
784 | (pt->cr_ipsr & ~IPSR_WRITE_MASK));
786 *data = (pt->cr_ipsr & IPSR_READ_MASK);
790 urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
791 rnat_addr = (long) ia64_rse_rnat_addr((long *) urbs_end);
793 return ia64_poke(child, sw, urbs_end, rnat_addr, *data);
795 return ia64_peek(child, sw, urbs_end, rnat_addr, data);
797 case PT_R1: case PT_R2: case PT_R3:
798 case PT_R8: case PT_R9: case PT_R10: case PT_R11:
799 case PT_R12: case PT_R13: case PT_R14: case PT_R15:
800 case PT_R16: case PT_R17: case PT_R18: case PT_R19:
801 case PT_R20: case PT_R21: case PT_R22: case PT_R23:
802 case PT_R24: case PT_R25: case PT_R26: case PT_R27:
803 case PT_R28: case PT_R29: case PT_R30: case PT_R31:
804 case PT_B0: case PT_B6: case PT_B7:
805 case PT_F6: case PT_F6+8: case PT_F7: case PT_F7+8:
806 case PT_F8: case PT_F8+8: case PT_F9: case PT_F9+8:
808 case PT_AR_RSC: case PT_AR_UNAT: case PT_AR_PFS:
809 case PT_AR_CCV: case PT_AR_FPSR: case PT_CR_IIP: case PT_PR:
810 /* scratch register */
811 ptr = (unsigned long *) ((long) pt + addr - PT_CR_IPSR);
815 /* disallow accessing anything else... */
816 dprintk("ptrace: rejecting access to register address 0x%lx\n",
821 /* access debug registers */
823 if (addr >= PT_IBR) {
824 regnum = (addr - PT_IBR) >> 3;
825 ptr = &child->thread.ibr[0];
827 regnum = (addr - PT_DBR) >> 3;
828 ptr = &child->thread.dbr[0];
832 dprintk("ptrace: rejecting access to register address 0x%lx\n", addr);
835 #ifdef CONFIG_PERFMON
837 * Check if debug registers are used by perfmon. This test must be done
838 * once we know that we can do the operation, i.e. the arguments are all
839 * valid, but before we start modifying the state.
841 * Perfmon needs to keep a count of how many processes are trying to
842 * modify the debug registers for system wide monitoring sessions.
844 * We also include read access here, because they may cause the
845 * PMU-installed debug register state (dbr[], ibr[]) to be reset. The two
846 * arrays are also used by perfmon, but we do not use
847 * IA64_THREAD_DBG_VALID. The registers are restored by the PMU context
850 if (pfm_use_debug_registers(child)) return -1;
853 if (!(child->thread.flags & IA64_THREAD_DBG_VALID)) {
854 child->thread.flags |= IA64_THREAD_DBG_VALID;
855 memset(child->thread.dbr, 0, sizeof(child->thread.dbr));
856 memset(child->thread.ibr, 0, sizeof(child->thread.ibr));
862 /* don't let the user set kernel-level breakpoints... */
863 *ptr = *data & ~(7UL << 56);
876 ptrace_getregs (struct task_struct *child, struct pt_all_user_regs *ppr)
878 struct switch_stack *sw;
881 struct unw_frame_info info;
885 retval = verify_area(VERIFY_WRITE, ppr, sizeof(struct pt_all_user_regs));
890 pt = ia64_task_regs(child);
891 sw = (struct switch_stack *) (child->thread.ksp + 16);
892 unw_init_from_blocked_task(&info, child);
893 if (unw_unwind_to_user(&info) < 0) {
897 if (((unsigned long) ppr & 0x7) != 0) {
898 dprintk("ptrace:unaligned register address %p\n", ppr);
906 retval |= __put_user(pt->cr_iip, &ppr->cr_iip);
907 retval |= access_uarea(child, PT_CR_IPSR, &ppr->cr_ipsr, 0);
911 retval |= __put_user(pt->ar_pfs, &ppr->ar[PT_AUR_PFS]);
912 retval |= __put_user(pt->ar_rsc, &ppr->ar[PT_AUR_RSC]);
913 retval |= __put_user(pt->ar_bspstore, &ppr->ar[PT_AUR_BSPSTORE]);
914 retval |= __put_user(pt->ar_unat, &ppr->ar[PT_AUR_UNAT]);
915 retval |= __put_user(pt->ar_ccv, &ppr->ar[PT_AUR_CCV]);
916 retval |= __put_user(pt->ar_fpsr, &ppr->ar[PT_AUR_FPSR]);
918 retval |= access_uarea(child, PT_AR_EC, &ppr->ar[PT_AUR_EC], 0);
919 retval |= access_uarea(child, PT_AR_LC, &ppr->ar[PT_AUR_LC], 0);
920 retval |= access_uarea(child, PT_AR_RNAT, &ppr->ar[PT_AUR_RNAT], 0);
921 retval |= access_uarea(child, PT_AR_BSP, &ppr->ar[PT_AUR_BSP], 0);
922 retval |= access_uarea(child, PT_CFM, &ppr->cfm, 0);
926 retval |= __copy_to_user(&ppr->gr[1], &pt->r1, sizeof(long) * 3);
930 for (i = 4; i < 8; i++) {
931 retval |= unw_access_gr(&info, i, &ppr->gr[i], &nat, 0);
936 retval |= __copy_to_user(&ppr->gr[8], &pt->r8, sizeof(long) * 4);
940 retval |= __copy_to_user(&ppr->gr[12], &pt->r12, sizeof(long) * 4);
944 retval |= __copy_to_user(&ppr->gr[16], &pt->r16, sizeof(long) * 16);
948 retval |= __put_user(pt->b0, &ppr->br[0]);
952 for (i = 1; i < 6; i++) {
953 retval |= unw_access_br(&info, i, &ppr->br[i], 0);
958 retval |= __put_user(pt->b6, &ppr->br[6]);
959 retval |= __put_user(pt->b7, &ppr->br[7]);
963 for (i = 2; i < 6; i++) {
964 retval |= access_fr(&info, i, 0, (unsigned long *) &ppr->fr[i], 0);
965 retval |= access_fr(&info, i, 1, (unsigned long *) &ppr->fr[i] + 1, 0);
970 retval |= __copy_to_user(&ppr->fr[6], &pt->f6, sizeof(struct ia64_fpreg) * 4);
972 /* fp scratch regs(10-15) */
974 retval |= __copy_to_user(&ppr->fr[10], &sw->f10, sizeof(struct ia64_fpreg) * 6);
978 for (i = 16; i < 32; i++) {
979 retval |= access_fr(&info, i, 0, (unsigned long *) &ppr->fr[i], 0);
980 retval |= access_fr(&info, i, 1, (unsigned long *) &ppr->fr[i] + 1, 0);
985 ia64_flush_fph(child);
986 retval |= __copy_to_user(&ppr->fr[32], &child->thread.fph, sizeof(ppr->fr[32]) * 96);
990 retval |= __put_user(pt->pr, &ppr->pr);
994 retval |= access_uarea(child, PT_NAT_BITS, &ppr->nat, 0);
996 ret = retval ? -EIO : 0;
1001 ptrace_setregs (struct task_struct *child, struct pt_all_user_regs *ppr)
1003 struct switch_stack *sw;
1006 struct unw_frame_info info;
1010 retval = verify_area(VERIFY_READ, ppr, sizeof(struct pt_all_user_regs));
1015 pt = ia64_task_regs(child);
1016 sw = (struct switch_stack *) (child->thread.ksp + 16);
1017 unw_init_from_blocked_task(&info, child);
1018 if (unw_unwind_to_user(&info) < 0) {
1022 if (((unsigned long) ppr & 0x7) != 0) {
1023 dprintk("ptrace:unaligned register address %p\n", ppr);
1031 retval |= __get_user(pt->cr_iip, &ppr->cr_iip);
1032 retval |= access_uarea(child, PT_CR_IPSR, &ppr->cr_ipsr, 1);
1036 retval |= __get_user(pt->ar_pfs, &ppr->ar[PT_AUR_PFS]);
1037 retval |= __get_user(pt->ar_rsc, &ppr->ar[PT_AUR_RSC]);
1038 retval |= __get_user(pt->ar_bspstore, &ppr->ar[PT_AUR_BSPSTORE]);
1039 retval |= __get_user(pt->ar_unat, &ppr->ar[PT_AUR_UNAT]);
1040 retval |= __get_user(pt->ar_ccv, &ppr->ar[PT_AUR_CCV]);
1041 retval |= __get_user(pt->ar_fpsr, &ppr->ar[PT_AUR_FPSR]);
1043 retval |= access_uarea(child, PT_AR_EC, &ppr->ar[PT_AUR_EC], 1);
1044 retval |= access_uarea(child, PT_AR_LC, &ppr->ar[PT_AUR_LC], 1);
1045 retval |= access_uarea(child, PT_AR_RNAT, &ppr->ar[PT_AUR_RNAT], 1);
1046 retval |= access_uarea(child, PT_AR_BSP, &ppr->ar[PT_AUR_BSP], 1);
1047 retval |= access_uarea(child, PT_CFM, &ppr->cfm, 1);
1051 retval |= __copy_from_user(&pt->r1, &ppr->gr[1], sizeof(long) * 3);
1055 for (i = 4; i < 8; i++) {
1056 long ret = unw_get_gr(&info, i, &ppr->gr[i], &nat);
1060 retval |= unw_access_gr(&info, i, &ppr->gr[i], &nat, 1);
1065 retval |= __copy_from_user(&pt->r8, &ppr->gr[8], sizeof(long) * 4);
1069 retval |= __copy_from_user(&pt->r12, &ppr->gr[12], sizeof(long) * 4);
1073 retval |= __copy_from_user(&pt->r16, &ppr->gr[16], sizeof(long) * 16);
1077 retval |= __get_user(pt->b0, &ppr->br[0]);
1081 for (i = 1; i < 6; i++) {
1082 retval |= unw_access_br(&info, i, &ppr->br[i], 1);
1087 retval |= __get_user(pt->b6, &ppr->br[6]);
1088 retval |= __get_user(pt->b7, &ppr->br[7]);
1092 for (i = 2; i < 6; i++) {
1093 retval |= access_fr(&info, i, 0, (unsigned long *) &ppr->fr[i], 1);
1094 retval |= access_fr(&info, i, 1, (unsigned long *) &ppr->fr[i] + 1, 1);
1099 retval |= __copy_from_user(&pt->f6, &ppr->fr[6], sizeof(ppr->fr[6]) * 4);
1101 /* fp scratch regs(10-15) */
1103 retval |= __copy_from_user(&sw->f10, &ppr->fr[10], sizeof(ppr->fr[10]) * 6);
1107 for (i = 16; i < 32; i++) {
1108 retval |= access_fr(&info, i, 0, (unsigned long *) &ppr->fr[i], 1);
1109 retval |= access_fr(&info, i, 1, (unsigned long *) &ppr->fr[i] + 1, 1);
1114 ia64_sync_fph(child);
1115 retval |= __copy_from_user(&child->thread.fph, &ppr->fr[32], sizeof(ppr->fr[32]) * 96);
1119 retval |= __get_user(pt->pr, &ppr->pr);
1123 retval |= access_uarea(child, PT_NAT_BITS, &ppr->nat, 1);
1125 ret = retval ? -EIO : 0;
1130 * Called by kernel/ptrace.c when detaching..
1132 * Make sure the single step bit is not set.
1135 ptrace_disable (struct task_struct *child)
1137 struct ia64_psr *child_psr = ia64_psr(ia64_task_regs(child));
1139 /* make sure the single step/take-branch tra bits are not set: */
1143 /* Turn off flag indicating that the KRBS is sync'd with child's VM: */
1144 child->thread.flags &= ~IA64_THREAD_KRBS_SYNCED;
1148 sys_ptrace (long request, pid_t pid, unsigned long addr, unsigned long data,
1149 long arg4, long arg5, long arg6, long arg7, long stack)
1151 struct pt_regs *pt, *regs = (struct pt_regs *) &stack;
1152 unsigned long urbs_end;
1153 struct task_struct *child;
1154 struct switch_stack *sw;
1159 if (request == PTRACE_TRACEME) {
1160 /* are we already being traced? */
1161 if (current->ptrace & PT_PTRACED)
1163 ret = security_ptrace(current->parent, current);
1166 current->ptrace |= PT_PTRACED;
1172 read_lock(&tasklist_lock);
1174 child = find_task_by_pid(pid);
1176 get_task_struct(child);
1178 read_unlock(&tasklist_lock);
1182 if (pid == 1) /* no messing around with init! */
1185 if (request == PTRACE_ATTACH) {
1186 ret = ptrace_attach(child);
1190 ret = ptrace_check_attach(child, request == PTRACE_KILL);
1194 pt = ia64_task_regs(child);
1195 sw = (struct switch_stack *) (child->thread.ksp + 16);
1198 case PTRACE_PEEKTEXT:
1199 case PTRACE_PEEKDATA: /* read word at location addr */
1200 urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
1202 if (!(child->thread.flags & IA64_THREAD_KRBS_SYNCED))
1203 threads_sync_user_rbs(child, urbs_end, 0);
1205 ret = ia64_peek(child, sw, urbs_end, addr, &data);
1208 regs->r8 = 0; /* ensure "ret" is not mistaken as an error code */
1212 case PTRACE_POKETEXT:
1213 case PTRACE_POKEDATA: /* write the word at location addr */
1214 urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
1215 if (!(child->thread.flags & IA64_THREAD_KRBS_SYNCED))
1216 threads_sync_user_rbs(child, urbs_end, 1);
1218 ret = ia64_poke(child, sw, urbs_end, addr, data);
1221 case PTRACE_PEEKUSR: /* read the word at addr in the USER area */
1222 if (access_uarea(child, addr, &data, 0) < 0) {
1227 regs->r8 = 0; /* ensure "ret" is not mistaken as an error code */
1230 case PTRACE_POKEUSR: /* write the word at addr in the USER area */
1231 if (access_uarea(child, addr, &data, 1) < 0) {
1238 case PTRACE_OLD_GETSIGINFO: /* for backwards-compatibility */
1239 ret = ptrace_request(child, PTRACE_GETSIGINFO, addr, data);
1242 case PTRACE_OLD_SETSIGINFO: /* for backwards-compatibility */
1243 ret = ptrace_request(child, PTRACE_SETSIGINFO, addr, data);
1246 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
1247 case PTRACE_CONT: /* restart after signal. */
1251 if (request == PTRACE_SYSCALL)
1252 set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
1254 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
1255 child->exit_code = data;
1257 /* make sure the single step/taken-branch trap bits are not set: */
1258 ia64_psr(pt)->ss = 0;
1259 ia64_psr(pt)->tb = 0;
1261 /* Turn off flag indicating that the KRBS is sync'd with child's VM: */
1262 child->thread.flags &= ~IA64_THREAD_KRBS_SYNCED;
1264 wake_up_process(child);
1270 * Make the child exit. Best I can do is send it a
1271 * sigkill. Perhaps it should be put in the status
1272 * that it wants to exit.
1274 if (child->state == TASK_ZOMBIE) /* already dead */
1276 child->exit_code = SIGKILL;
1278 /* make sure the single step/take-branch tra bits are not set: */
1279 ia64_psr(pt)->ss = 0;
1280 ia64_psr(pt)->tb = 0;
1282 /* Turn off flag indicating that the KRBS is sync'd with child's VM: */
1283 child->thread.flags &= ~IA64_THREAD_KRBS_SYNCED;
1285 wake_up_process(child);
1289 case PTRACE_SINGLESTEP: /* let child execute for one instruction */
1290 case PTRACE_SINGLEBLOCK:
1295 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
1296 if (request == PTRACE_SINGLESTEP) {
1297 ia64_psr(pt)->ss = 1;
1299 ia64_psr(pt)->tb = 1;
1301 child->exit_code = data;
1303 /* Turn off flag indicating that the KRBS is sync'd with child's VM: */
1304 child->thread.flags &= ~IA64_THREAD_KRBS_SYNCED;
1306 /* give it a chance to run. */
1307 wake_up_process(child);
1311 case PTRACE_DETACH: /* detach a process that was attached. */
1312 ret = ptrace_detach(child, data);
1315 case PTRACE_GETREGS:
1316 ret = ptrace_getregs(child, (struct pt_all_user_regs*) data);
1319 case PTRACE_SETREGS:
1320 ret = ptrace_setregs(child, (struct pt_all_user_regs*) data);
1324 ret = ptrace_request(child, request, addr, data);
1328 put_task_struct(child);
1335 syscall_trace (void)
1337 if (!test_thread_flag(TIF_SYSCALL_TRACE))
1339 if (!(current->ptrace & PT_PTRACED))
1342 * The 0x80 provides a way for the tracing parent to distinguish between a syscall
1343 * stop and SIGTRAP delivery.
1345 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ? 0x80 : 0));
1348 * This isn't the same as continuing with a signal, but it will do for normal use.
1349 * strace only continues with a signal if the stopping signal is not SIGTRAP.
1352 if (current->exit_code) {
1353 send_sig(current->exit_code, current, 1);
1354 current->exit_code = 0;