drivers/media/video/s5p-fimc/fimc-core.c

   1 /*
   2  * Samsung S5P/EXYNOS4 SoC series camera interface (video postprocessor) driver
   3  *
   4  * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
   5  * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published
   9  * by the Free Software Foundation, either version 2 of the License,
  10  * or (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/types.h>
  16 #include <linux/errno.h>
  17 #include <linux/bug.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/list.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25 #include <linux/clk.h>
  26 #include <media/v4l2-ioctl.h>
  27 #include <media/videobuf2-core.h>
  28 #include <media/videobuf2-dma-contig.h>
  29
  30 #include "fimc-core.h"
  31 #include "fimc-mdevice.h"
  32
  33 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
  34         "sclk_fimc", "fimc"
  35 };
  36
  37 static struct fimc_fmt fimc_formats[] = {
  38         {
  39                 .name           = "RGB565",
  40                 .fourcc         = V4L2_PIX_FMT_RGB565,
  41                 .depth          = { 16 },
  42                 .color          = S5P_FIMC_RGB565,
  43                 .memplanes      = 1,
  44                 .colplanes      = 1,
  45                 .flags          = FMT_FLAGS_M2M,
  46         }, {
  47                 .name           = "BGR666",
  48                 .fourcc         = V4L2_PIX_FMT_BGR666,
  49                 .depth          = { 32 },
  50                 .color          = S5P_FIMC_RGB666,
  51                 .memplanes      = 1,
  52                 .colplanes      = 1,
  53                 .flags          = FMT_FLAGS_M2M,
  54         }, {
  55                 .name           = "ARGB8888, 32 bpp",
  56                 .fourcc         = V4L2_PIX_FMT_RGB32,
  57                 .depth          = { 32 },
  58                 .color          = S5P_FIMC_RGB888,
  59                 .memplanes      = 1,
  60                 .colplanes      = 1,
  61                 .flags          = FMT_FLAGS_M2M | FMT_HAS_ALPHA,
  62         }, {
  63                 .name           = "ARGB1555",
  64                 .fourcc         = V4L2_PIX_FMT_RGB555,
  65                 .depth          = { 16 },
  66                 .color          = S5P_FIMC_RGB555,
  67                 .memplanes      = 1,
  68                 .colplanes      = 1,
  69                 .flags          = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
  70         }, {
  71                 .name           = "ARGB4444",
  72                 .fourcc         = V4L2_PIX_FMT_RGB444,
  73                 .depth          = { 16 },
  74                 .color          = S5P_FIMC_RGB444,
  75                 .memplanes      = 1,
  76                 .colplanes      = 1,
  77                 .flags          = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
  78         }, {
  79                 .name           = "YUV 4:2:2 packed, YCbYCr",
  80                 .fourcc         = V4L2_PIX_FMT_YUYV,
  81                 .depth          = { 16 },
  82                 .color          = S5P_FIMC_YCBYCR422,
  83                 .memplanes      = 1,
  84                 .colplanes      = 1,
  85                 .mbus_code      = V4L2_MBUS_FMT_YUYV8_2X8,
  86                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  87         }, {
  88                 .name           = "YUV 4:2:2 packed, CbYCrY",
  89                 .fourcc         = V4L2_PIX_FMT_UYVY,
  90                 .depth          = { 16 },
  91                 .color          = S5P_FIMC_CBYCRY422,
  92                 .memplanes      = 1,
  93                 .colplanes      = 1,
  94                 .mbus_code      = V4L2_MBUS_FMT_UYVY8_2X8,
  95                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  96         }, {
  97                 .name           = "YUV 4:2:2 packed, CrYCbY",
  98                 .fourcc         = V4L2_PIX_FMT_VYUY,
  99                 .depth          = { 16 },
 100                 .color          = S5P_FIMC_CRYCBY422,
 101                 .memplanes      = 1,
 102                 .colplanes      = 1,
 103                 .mbus_code      = V4L2_MBUS_FMT_VYUY8_2X8,
 104                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
 105         }, {
 106                 .name           = "YUV 4:2:2 packed, YCrYCb",
 107                 .fourcc         = V4L2_PIX_FMT_YVYU,
 108                 .depth          = { 16 },
 109                 .color          = S5P_FIMC_YCRYCB422,
 110                 .memplanes      = 1,
 111                 .colplanes      = 1,
 112                 .mbus_code      = V4L2_MBUS_FMT_YVYU8_2X8,
 113                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
 114         }, {
 115                 .name           = "YUV 4:2:2 planar, Y/Cb/Cr",
 116                 .fourcc         = V4L2_PIX_FMT_YUV422P,
 117                 .depth          = { 12 },
 118                 .color          = S5P_FIMC_YCBYCR422,
 119                 .memplanes      = 1,
 120                 .colplanes      = 3,
 121                 .flags          = FMT_FLAGS_M2M,
 122         }, {
 123                 .name           = "YUV 4:2:2 planar, Y/CbCr",
 124                 .fourcc         = V4L2_PIX_FMT_NV16,
 125                 .depth          = { 16 },
 126                 .color          = S5P_FIMC_YCBYCR422,
 127                 .memplanes      = 1,
 128                 .colplanes      = 2,
 129                 .flags          = FMT_FLAGS_M2M,
 130         }, {
 131                 .name           = "YUV 4:2:2 planar, Y/CrCb",
 132                 .fourcc         = V4L2_PIX_FMT_NV61,
 133                 .depth          = { 16 },
 134                 .color          = S5P_FIMC_YCRYCB422,
 135                 .memplanes      = 1,
 136                 .colplanes      = 2,
 137                 .flags          = FMT_FLAGS_M2M,
 138         }, {
 139                 .name           = "YUV 4:2:0 planar, YCbCr",
 140                 .fourcc         = V4L2_PIX_FMT_YUV420,
 141                 .depth          = { 12 },
 142                 .color          = S5P_FIMC_YCBCR420,
 143                 .memplanes      = 1,
 144                 .colplanes      = 3,
 145                 .flags          = FMT_FLAGS_M2M,
 146         }, {
 147                 .name           = "YUV 4:2:0 planar, Y/CbCr",
 148                 .fourcc         = V4L2_PIX_FMT_NV12,
 149                 .depth          = { 12 },
 150                 .color          = S5P_FIMC_YCBCR420,
 151                 .memplanes      = 1,
 152                 .colplanes      = 2,
 153                 .flags          = FMT_FLAGS_M2M,
 154         }, {
 155                 .name           = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
 156                 .fourcc         = V4L2_PIX_FMT_NV12M,
 157                 .color          = S5P_FIMC_YCBCR420,
 158                 .depth          = { 8, 4 },
 159                 .memplanes      = 2,
 160                 .colplanes      = 2,
 161                 .flags          = FMT_FLAGS_M2M,
 162         }, {
 163                 .name           = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
 164                 .fourcc         = V4L2_PIX_FMT_YUV420M,
 165                 .color          = S5P_FIMC_YCBCR420,
 166                 .depth          = { 8, 2, 2 },
 167                 .memplanes      = 3,
 168                 .colplanes      = 3,
 169                 .flags          = FMT_FLAGS_M2M,
 170         }, {
 171                 .name           = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
 172                 .fourcc         = V4L2_PIX_FMT_NV12MT,
 173                 .color          = S5P_FIMC_YCBCR420,
 174                 .depth          = { 8, 4 },
 175                 .memplanes      = 2,
 176                 .colplanes      = 2,
 177                 .flags          = FMT_FLAGS_M2M,
 178         }, {
 179                 .name           = "JPEG encoded data",
 180                 .fourcc         = V4L2_PIX_FMT_JPEG,
 181                 .color          = S5P_FIMC_JPEG,
 182                 .depth          = { 8 },
 183                 .memplanes      = 1,
 184                 .colplanes      = 1,
 185                 .mbus_code      = V4L2_MBUS_FMT_JPEG_1X8,
 186                 .flags          = FMT_FLAGS_CAM,
 187         },
 188 };
 189
 190 static unsigned int get_m2m_fmt_flags(unsigned int stream_type)
 191 {
 192         if (stream_type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
 193                 return FMT_FLAGS_M2M_IN;
 194         else
 195                 return FMT_FLAGS_M2M_OUT;
 196 }
 197
 198 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
 199                             int dw, int dh, int rotation)
 200 {
 201         if (rotation == 90 || rotation == 270)
 202                 swap(dw, dh);
 203
 204         if (!ctx->scaler.enabled)
 205                 return (sw == dw && sh == dh) ? 0 : -EINVAL;
 206
 207         if ((sw >= SCALER_MAX_HRATIO * dw) || (sh >= SCALER_MAX_VRATIO * dh))
 208                 return -EINVAL;
 209
 210         return 0;
 211 }
 212
 213 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
 214 {
 215         u32 sh = 6;
 216
 217         if (src >= 64 * tar)
 218                 return -EINVAL;
 219
 220         while (sh--) {
 221                 u32 tmp = 1 << sh;
 222                 if (src >= tar * tmp) {
 223                         *shift = sh, *ratio = tmp;
 224                         return 0;
 225                 }
 226         }
 227         *shift = 0, *ratio = 1;
 228         return 0;
 229 }
 230
 231 int fimc_set_scaler_info(struct fimc_ctx *ctx)
 232 {
 233         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
 234         struct device *dev = &ctx->fimc_dev->pdev->dev;
 235         struct fimc_scaler *sc = &ctx->scaler;
 236         struct fimc_frame *s_frame = &ctx->s_frame;
 237         struct fimc_frame *d_frame = &ctx->d_frame;
 238         int tx, ty, sx, sy;
 239         int ret;
 240
 241         if (ctx->rotation == 90 || ctx->rotation == 270) {
 242                 ty = d_frame->width;
 243                 tx = d_frame->height;
 244         } else {
 245                 tx = d_frame->width;
 246                 ty = d_frame->height;
 247         }
 248         if (tx <= 0 || ty <= 0) {
 249                 dev_err(dev, "Invalid target size: %dx%d", tx, ty);
 250                 return -EINVAL;
 251         }
 252
 253         sx = s_frame->width;
 254         sy = s_frame->height;
 255         if (sx <= 0 || sy <= 0) {
 256                 dev_err(dev, "Invalid source size: %dx%d", sx, sy);
 257                 return -EINVAL;
 258         }
 259         sc->real_width = sx;
 260         sc->real_height = sy;
 261
 262         ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
 263         if (ret)
 264                 return ret;
 265
 266         ret = fimc_get_scaler_factor(sy, ty,  &sc->pre_vratio, &sc->vfactor);
 267         if (ret)
 268                 return ret;
 269
 270         sc->pre_dst_width = sx / sc->pre_hratio;
 271         sc->pre_dst_height = sy / sc->pre_vratio;
 272
 273         if (variant->has_mainscaler_ext) {
 274                 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
 275                 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
 276         } else {
 277                 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
 278                 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
 279
 280         }
 281
 282         sc->scaleup_h = (tx >= sx) ? 1 : 0;
 283         sc->scaleup_v = (ty >= sy) ? 1 : 0;
 284
 285         /* check to see if input and output size/format differ */
 286         if (s_frame->fmt->color == d_frame->fmt->color
 287                 && s_frame->width == d_frame->width
 288                 && s_frame->height == d_frame->height)
 289                 sc->copy_mode = 1;
 290         else
 291                 sc->copy_mode = 0;
 292
 293         return 0;
 294 }
 295
 296 static void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state)
 297 {
 298         struct vb2_buffer *src_vb, *dst_vb;
 299
 300         if (!ctx || !ctx->m2m_ctx)
 301                 return;
 302
 303         src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
 304         dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
 305
 306         if (src_vb && dst_vb) {
 307                 v4l2_m2m_buf_done(src_vb, vb_state);
 308                 v4l2_m2m_buf_done(dst_vb, vb_state);
 309                 v4l2_m2m_job_finish(ctx->fimc_dev->m2m.m2m_dev,
 310                                     ctx->m2m_ctx);
 311         }
 312 }
 313
 314 /* Complete the transaction which has been scheduled for execution. */
 315 static int fimc_m2m_shutdown(struct fimc_ctx *ctx)
 316 {
 317         struct fimc_dev *fimc = ctx->fimc_dev;
 318         int ret;
 319
 320         if (!fimc_m2m_pending(fimc))
 321                 return 0;
 322
 323         fimc_ctx_state_lock_set(FIMC_CTX_SHUT, ctx);
 324
 325         ret = wait_event_timeout(fimc->irq_queue,
 326                            !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
 327                            FIMC_SHUTDOWN_TIMEOUT);
 328
 329         return ret == 0 ? -ETIMEDOUT : ret;
 330 }
 331
 332 static int start_streaming(struct vb2_queue *q, unsigned int count)
 333 {
 334         struct fimc_ctx *ctx = q->drv_priv;
 335         int ret;
 336
 337         ret = pm_runtime_get_sync(&ctx->fimc_dev->pdev->dev);
 338         return ret > 0 ? 0 : ret;
 339 }
 340
 341 static int stop_streaming(struct vb2_queue *q)
 342 {
 343         struct fimc_ctx *ctx = q->drv_priv;
 344         int ret;
 345
 346         ret = fimc_m2m_shutdown(ctx);
 347         if (ret == -ETIMEDOUT)
 348                 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
 349
 350         pm_runtime_put(&ctx->fimc_dev->pdev->dev);
 351         return 0;
 352 }
 353
 354 void fimc_capture_irq_handler(struct fimc_dev *fimc, bool final)
 355 {
 356         struct fimc_vid_cap *cap = &fimc->vid_cap;
 357         struct fimc_vid_buffer *v_buf;
 358         struct timeval *tv;
 359         struct timespec ts;
 360
 361         if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
 362                 wake_up(&fimc->irq_queue);
 363                 return;
 364         }
 365
 366         if (!list_empty(&cap->active_buf_q) &&
 367             test_bit(ST_CAPT_RUN, &fimc->state) && final) {
 368                 ktime_get_real_ts(&ts);
 369
 370                 v_buf = fimc_active_queue_pop(cap);
 371
 372                 tv = &v_buf->vb.v4l2_buf.timestamp;
 373                 tv->tv_sec = ts.tv_sec;
 374                 tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
 375                 v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
 376
 377                 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
 378         }
 379
 380         if (!list_empty(&cap->pending_buf_q)) {
 381
 382                 v_buf = fimc_pending_queue_pop(cap);
 383                 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
 384                 v_buf->index = cap->buf_index;
 385
 386                 /* Move the buffer to the capture active queue */
 387                 fimc_active_queue_add(cap, v_buf);
 388
 389                 dbg("next frame: %d, done frame: %d",
 390                     fimc_hw_get_frame_index(fimc), v_buf->index);
 391
 392                 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
 393                         cap->buf_index = 0;
 394         }
 395
 396         if (cap->active_buf_cnt == 0) {
 397                 if (final)
 398                         clear_bit(ST_CAPT_RUN, &fimc->state);
 399
 400                 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
 401                         cap->buf_index = 0;
 402         } else {
 403                 set_bit(ST_CAPT_RUN, &fimc->state);
 404         }
 405
 406         fimc_capture_config_update(cap->ctx);
 407
 408         dbg("frame: %d, active_buf_cnt: %d",
 409             fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
 410 }
 411
 412 static irqreturn_t fimc_irq_handler(int irq, void *priv)
 413 {
 414         struct fimc_dev *fimc = priv;
 415         struct fimc_vid_cap *cap = &fimc->vid_cap;
 416         struct fimc_ctx *ctx;
 417
 418         fimc_hw_clear_irq(fimc);
 419
 420         spin_lock(&fimc->slock);
 421
 422         if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
 423                 if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) {
 424                         set_bit(ST_M2M_SUSPENDED, &fimc->state);
 425                         wake_up(&fimc->irq_queue);
 426                         goto out;
 427                 }
 428                 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
 429                 if (ctx != NULL) {
 430                         spin_unlock(&fimc->slock);
 431                         fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
 432
 433                         spin_lock(&ctx->slock);
 434                         if (ctx->state & FIMC_CTX_SHUT) {
 435                                 ctx->state &= ~FIMC_CTX_SHUT;
 436                                 wake_up(&fimc->irq_queue);
 437                         }
 438                         spin_unlock(&ctx->slock);
 439                 }
 440                 return IRQ_HANDLED;
 441         } else if (test_bit(ST_CAPT_PEND, &fimc->state)) {
 442                 fimc_capture_irq_handler(fimc,
 443                                  !test_bit(ST_CAPT_JPEG, &fimc->state));
 444                 if (cap->active_buf_cnt == 1) {
 445                         fimc_deactivate_capture(fimc);
 446                         clear_bit(ST_CAPT_STREAM, &fimc->state);
 447                 }
 448         }
 449 out:
 450         spin_unlock(&fimc->slock);
 451         return IRQ_HANDLED;
 452 }
 453
 454 /* The color format (colplanes, memplanes) must be already configured. */
 455 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 456                       struct fimc_frame *frame, struct fimc_addr *paddr)
 457 {
 458         int ret = 0;
 459         u32 pix_size;
 460
 461         if (vb == NULL || frame == NULL)
 462                 return -EINVAL;
 463
 464         pix_size = frame->width * frame->height;
 465
 466         dbg("memplanes= %d, colplanes= %d, pix_size= %d",
 467                 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
 468
 469         paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
 470
 471         if (frame->fmt->memplanes == 1) {
 472                 switch (frame->fmt->colplanes) {
 473                 case 1:
 474                         paddr->cb = 0;
 475                         paddr->cr = 0;
 476                         break;
 477                 case 2:
 478                         /* decompose Y into Y/Cb */
 479                         paddr->cb = (u32)(paddr->y + pix_size);
 480                         paddr->cr = 0;
 481                         break;
 482                 case 3:
 483                         paddr->cb = (u32)(paddr->y + pix_size);
 484                         /* decompose Y into Y/Cb/Cr */
 485                         if (S5P_FIMC_YCBCR420 == frame->fmt->color)
 486                                 paddr->cr = (u32)(paddr->cb
 487                                                 + (pix_size >> 2));
 488                         else /* 422 */
 489                                 paddr->cr = (u32)(paddr->cb
 490                                                 + (pix_size >> 1));
 491                         break;
 492                 default:
 493                         return -EINVAL;
 494                 }
 495         } else {
 496                 if (frame->fmt->memplanes >= 2)
 497                         paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
 498
 499                 if (frame->fmt->memplanes == 3)
 500                         paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
 501         }
 502
 503         dbg("PHYS_ADDR: y= 0x%X  cb= 0x%X cr= 0x%X ret= %d",
 504             paddr->y, paddr->cb, paddr->cr, ret);
 505
 506         return ret;
 507 }
 508
 509 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
 510 void fimc_set_yuv_order(struct fimc_ctx *ctx)
 511 {
 512         /* The one only mode supported in SoC. */
 513         ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
 514         ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
 515
 516         /* Set order for 1 plane input formats. */
 517         switch (ctx->s_frame.fmt->color) {
 518         case S5P_FIMC_YCRYCB422:
 519                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
 520                 break;
 521         case S5P_FIMC_CBYCRY422:
 522                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
 523                 break;
 524         case S5P_FIMC_CRYCBY422:
 525                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
 526                 break;
 527         case S5P_FIMC_YCBYCR422:
 528         default:
 529                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
 530                 break;
 531         }
 532         dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
 533
 534         switch (ctx->d_frame.fmt->color) {
 535         case S5P_FIMC_YCRYCB422:
 536                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
 537                 break;
 538         case S5P_FIMC_CBYCRY422:
 539                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
 540                 break;
 541         case S5P_FIMC_CRYCBY422:
 542                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
 543                 break;
 544         case S5P_FIMC_YCBYCR422:
 545         default:
 546                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
 547                 break;
 548         }
 549         dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
 550 }
 551
 552 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
 553 {
 554         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
 555         u32 i, depth = 0;
 556
 557         for (i = 0; i < f->fmt->colplanes; i++)
 558                 depth += f->fmt->depth[i];
 559
 560         f->dma_offset.y_h = f->offs_h;
 561         if (!variant->pix_hoff)
 562                 f->dma_offset.y_h *= (depth >> 3);
 563
 564         f->dma_offset.y_v = f->offs_v;
 565
 566         f->dma_offset.cb_h = f->offs_h;
 567         f->dma_offset.cb_v = f->offs_v;
 568
 569         f->dma_offset.cr_h = f->offs_h;
 570         f->dma_offset.cr_v = f->offs_v;
 571
 572         if (!variant->pix_hoff) {
 573                 if (f->fmt->colplanes == 3) {
 574                         f->dma_offset.cb_h >>= 1;
 575                         f->dma_offset.cr_h >>= 1;
 576                 }
 577                 if (f->fmt->color == S5P_FIMC_YCBCR420) {
 578                         f->dma_offset.cb_v >>= 1;
 579                         f->dma_offset.cr_v >>= 1;
 580                 }
 581         }
 582
 583         dbg("in_offset: color= %d, y_h= %d, y_v= %d",
 584             f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
 585 }
 586
 587 /**
 588  * fimc_prepare_config - check dimensions, operation and color mode
 589  *                       and pre-calculate offset and the scaling coefficients.
 590  *
 591  * @ctx: hardware context information
 592  * @flags: flags indicating which parameters to check/update
 593  *
 594  * Return: 0 if dimensions are valid or non zero otherwise.
 595  */
 596 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
 597 {
 598         struct fimc_frame *s_frame, *d_frame;
 599         struct vb2_buffer *vb = NULL;
 600         int ret = 0;
 601
 602         s_frame = &ctx->s_frame;
 603         d_frame = &ctx->d_frame;
 604
 605         if (flags & FIMC_PARAMS) {
 606                 /* Prepare the DMA offset ratios for scaler. */
 607                 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
 608                 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
 609
 610                 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
 611                     s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
 612                         err("out of scaler range");
 613                         return -EINVAL;
 614                 }
 615                 fimc_set_yuv_order(ctx);
 616         }
 617
 618         if (flags & FIMC_SRC_ADDR) {
 619                 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
 620                 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
 621                 if (ret)
 622                         return ret;
 623         }
 624
 625         if (flags & FIMC_DST_ADDR) {
 626                 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
 627                 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
 628         }
 629
 630         return ret;
 631 }
 632
 633 static void fimc_dma_run(void *priv)
 634 {
 635         struct fimc_ctx *ctx = priv;
 636         struct fimc_dev *fimc;
 637         unsigned long flags;
 638         u32 ret;
 639
 640         if (WARN(!ctx, "null hardware context\n"))
 641                 return;
 642
 643         fimc = ctx->fimc_dev;
 644         spin_lock_irqsave(&fimc->slock, flags);
 645         set_bit(ST_M2M_PEND, &fimc->state);
 646
 647         spin_lock(&ctx->slock);
 648         ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
 649         ret = fimc_prepare_config(ctx, ctx->state);
 650         if (ret)
 651                 goto dma_unlock;
 652
 653         /* Reconfigure hardware if the context has changed. */
 654         if (fimc->m2m.ctx != ctx) {
 655                 ctx->state |= FIMC_PARAMS;
 656                 fimc->m2m.ctx = ctx;
 657         }
 658         fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
 659
 660         if (ctx->state & FIMC_PARAMS) {
 661                 fimc_hw_set_input_path(ctx);
 662                 fimc_hw_set_in_dma(ctx);
 663                 ret = fimc_set_scaler_info(ctx);
 664                 if (ret) {
 665                         spin_unlock(&fimc->slock);
 666                         goto dma_unlock;
 667                 }
 668                 fimc_hw_set_prescaler(ctx);
 669                 fimc_hw_set_mainscaler(ctx);
 670                 fimc_hw_set_target_format(ctx);
 671                 fimc_hw_set_rotation(ctx);
 672                 fimc_hw_set_effect(ctx, false);
 673         }
 674
 675         fimc_hw_set_output_path(ctx);
 676         if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
 677                 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
 678
 679         if (ctx->state & FIMC_PARAMS) {
 680                 fimc_hw_set_out_dma(ctx);
 681                 if (fimc->variant->has_alpha)
 682                         fimc_hw_set_rgb_alpha(ctx);
 683         }
 684
 685         fimc_activate_capture(ctx);
 686
 687         ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
 688                        FIMC_SRC_FMT | FIMC_DST_FMT);
 689         fimc_hw_activate_input_dma(fimc, true);
 690 dma_unlock:
 691         spin_unlock(&ctx->slock);
 692         spin_unlock_irqrestore(&fimc->slock, flags);
 693 }
 694
 695 static void fimc_job_abort(void *priv)
 696 {
 697         fimc_m2m_shutdown(priv);
 698 }
 699
 700 static int fimc_queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt,
 701                             unsigned int *num_buffers, unsigned int *num_planes,
 702                             unsigned int sizes[], void *allocators[])
 703 {
 704         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 705         struct fimc_frame *f;
 706         int i;
 707
 708         f = ctx_get_frame(ctx, vq->type);
 709         if (IS_ERR(f))
 710                 return PTR_ERR(f);
 711         /*
 712          * Return number of non-contigous planes (plane buffers)
 713          * depending on the configured color format.
 714          */
 715         if (!f->fmt)
 716                 return -EINVAL;
 717
 718         *num_planes = f->fmt->memplanes;
 719         for (i = 0; i < f->fmt->memplanes; i++) {
 720                 sizes[i] = (f->f_width * f->f_height * f->fmt->depth[i]) / 8;
 721                 allocators[i] = ctx->fimc_dev->alloc_ctx;
 722         }
 723         return 0;
 724 }
 725
 726 static int fimc_buf_prepare(struct vb2_buffer *vb)
 727 {
 728         struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
 729         struct fimc_frame *frame;
 730         int i;
 731
 732         frame = ctx_get_frame(ctx, vb->vb2_queue->type);
 733         if (IS_ERR(frame))
 734                 return PTR_ERR(frame);
 735
 736         for (i = 0; i < frame->fmt->memplanes; i++)
 737                 vb2_set_plane_payload(vb, i, frame->payload[i]);
 738
 739         return 0;
 740 }
 741
 742 static void fimc_buf_queue(struct vb2_buffer *vb)
 743 {
 744         struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
 745
 746         dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
 747
 748         if (ctx->m2m_ctx)
 749                 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
 750 }
 751
 752 static void fimc_lock(struct vb2_queue *vq)
 753 {
 754         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 755         mutex_lock(&ctx->fimc_dev->lock);
 756 }
 757
 758 static void fimc_unlock(struct vb2_queue *vq)
 759 {
 760         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 761         mutex_unlock(&ctx->fimc_dev->lock);
 762 }
 763
 764 static struct vb2_ops fimc_qops = {
 765         .queue_setup     = fimc_queue_setup,
 766         .buf_prepare     = fimc_buf_prepare,
 767         .buf_queue       = fimc_buf_queue,
 768         .wait_prepare    = fimc_unlock,
 769         .wait_finish     = fimc_lock,
 770         .stop_streaming  = stop_streaming,
 771         .start_streaming = start_streaming,
 772 };
 773
 774 /*
 775  * V4L2 controls handling
 776  */
 777 #define ctrl_to_ctx(__ctrl) \
 778         container_of((__ctrl)->handler, struct fimc_ctx, ctrl_handler)
 779
 780 static int __fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_ctrl *ctrl)
 781 {
 782         struct fimc_dev *fimc = ctx->fimc_dev;
 783         struct samsung_fimc_variant *variant = fimc->variant;
 784         unsigned int flags = FIMC_DST_FMT | FIMC_SRC_FMT;
 785         int ret = 0;
 786
 787         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
 788                 return 0;
 789
 790         switch (ctrl->id) {
 791         case V4L2_CID_HFLIP:
 792                 ctx->hflip = ctrl->val;
 793                 break;
 794
 795         case V4L2_CID_VFLIP:
 796                 ctx->vflip = ctrl->val;
 797                 break;
 798
 799         case V4L2_CID_ROTATE:
 800                 if (fimc_capture_pending(fimc) ||
 801                     (ctx->state & flags) == flags) {
 802                         ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
 803                                         ctx->s_frame.height, ctx->d_frame.width,
 804                                         ctx->d_frame.height, ctrl->val);
 805                         if (ret)
 806                                 return -EINVAL;
 807                 }
 808                 if ((ctrl->val == 90 || ctrl->val == 270) &&
 809                     !variant->has_out_rot)
 810                         return -EINVAL;
 811
 812                 ctx->rotation = ctrl->val;
 813                 break;
 814
 815         case V4L2_CID_ALPHA_COMPONENT:
 816                 ctx->d_frame.alpha = ctrl->val;
 817                 break;
 818         }
 819         ctx->state |= FIMC_PARAMS;
 820         set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
 821         return 0;
 822 }
 823
 824 static int fimc_s_ctrl(struct v4l2_ctrl *ctrl)
 825 {
 826         struct fimc_ctx *ctx = ctrl_to_ctx(ctrl);
 827         unsigned long flags;
 828         int ret;
 829
 830         spin_lock_irqsave(&ctx->slock, flags);
 831         ret = __fimc_s_ctrl(ctx, ctrl);
 832         spin_unlock_irqrestore(&ctx->slock, flags);
 833
 834         return ret;
 835 }
 836
 837 static const struct v4l2_ctrl_ops fimc_ctrl_ops = {
 838         .s_ctrl = fimc_s_ctrl,
 839 };
 840
 841 int fimc_ctrls_create(struct fimc_ctx *ctx)
 842 {
 843         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
 844         unsigned int max_alpha = fimc_get_alpha_mask(ctx->d_frame.fmt);
 845
 846         if (ctx->ctrls_rdy)
 847                 return 0;
 848         v4l2_ctrl_handler_init(&ctx->ctrl_handler, 4);
 849
 850         ctx->ctrl_rotate = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
 851                                         V4L2_CID_ROTATE, 0, 270, 90, 0);
 852         ctx->ctrl_hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
 853                                         V4L2_CID_HFLIP, 0, 1, 1, 0);
 854         ctx->ctrl_vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
 855                                         V4L2_CID_VFLIP, 0, 1, 1, 0);
 856         if (variant->has_alpha)
 857                 ctx->ctrl_alpha = v4l2_ctrl_new_std(&ctx->ctrl_handler,
 858                                     &fimc_ctrl_ops, V4L2_CID_ALPHA_COMPONENT,
 859                                     0, max_alpha, 1, 0);
 860         else
 861                 ctx->ctrl_alpha = NULL;
 862
 863         ctx->ctrls_rdy = ctx->ctrl_handler.error == 0;
 864
 865         return ctx->ctrl_handler.error;
 866 }
 867
 868 void fimc_ctrls_delete(struct fimc_ctx *ctx)
 869 {
 870         if (ctx->ctrls_rdy) {
 871                 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
 872                 ctx->ctrls_rdy = false;
 873                 ctx->ctrl_alpha = NULL;
 874         }
 875 }
 876
 877 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active)
 878 {
 879         unsigned int has_alpha = ctx->d_frame.fmt->flags & FMT_HAS_ALPHA;
 880
 881         if (!ctx->ctrls_rdy)
 882                 return;
 883
 884         mutex_lock(&ctx->ctrl_handler.lock);
 885         v4l2_ctrl_activate(ctx->ctrl_rotate, active);
 886         v4l2_ctrl_activate(ctx->ctrl_hflip, active);
 887         v4l2_ctrl_activate(ctx->ctrl_vflip, active);
 888         if (ctx->ctrl_alpha)
 889                 v4l2_ctrl_activate(ctx->ctrl_alpha, active && has_alpha);
 890
 891         if (active) {
 892                 ctx->rotation = ctx->ctrl_rotate->val;
 893                 ctx->hflip    = ctx->ctrl_hflip->val;
 894                 ctx->vflip    = ctx->ctrl_vflip->val;
 895         } else {
 896                 ctx->rotation = 0;
 897                 ctx->hflip    = 0;
 898                 ctx->vflip    = 0;
 899         }
 900         mutex_unlock(&ctx->ctrl_handler.lock);
 901 }
 902
 903 /* Update maximum value of the alpha color control */
 904 void fimc_alpha_ctrl_update(struct fimc_ctx *ctx)
 905 {
 906         struct fimc_dev *fimc = ctx->fimc_dev;
 907         struct v4l2_ctrl *ctrl = ctx->ctrl_alpha;
 908
 909         if (ctrl == NULL || !fimc->variant->has_alpha)
 910                 return;
 911
 912         v4l2_ctrl_lock(ctrl);
 913         ctrl->maximum = fimc_get_alpha_mask(ctx->d_frame.fmt);
 914
 915         if (ctrl->cur.val > ctrl->maximum)
 916                 ctrl->cur.val = ctrl->maximum;
 917
 918         v4l2_ctrl_unlock(ctrl);
 919 }
 920
 921 /*
 922  * V4L2 ioctl handlers
 923  */
 924 static int fimc_m2m_querycap(struct file *file, void *fh,
 925                              struct v4l2_capability *cap)
 926 {
 927         struct fimc_ctx *ctx = fh_to_ctx(fh);
 928         struct fimc_dev *fimc = ctx->fimc_dev;
 929
 930         strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
 931         strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
 932         cap->bus_info[0] = 0;
 933         cap->capabilities = V4L2_CAP_STREAMING |
 934                 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
 935
 936         return 0;
 937 }
 938
 939 static int fimc_m2m_enum_fmt_mplane(struct file *file, void *priv,
 940                                     struct v4l2_fmtdesc *f)
 941 {
 942         struct fimc_fmt *fmt;
 943
 944         fmt = fimc_find_format(NULL, NULL, get_m2m_fmt_flags(f->type),
 945                                f->index);
 946         if (!fmt)
 947                 return -EINVAL;
 948
 949         strncpy(f->description, fmt->name, sizeof(f->description) - 1);
 950         f->pixelformat = fmt->fourcc;
 951         return 0;
 952 }
 953
 954 int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f)
 955 {
 956         struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
 957         int i;
 958
 959         pixm->width = frame->o_width;
 960         pixm->height = frame->o_height;
 961         pixm->field = V4L2_FIELD_NONE;
 962         pixm->pixelformat = frame->fmt->fourcc;
 963         pixm->colorspace = V4L2_COLORSPACE_JPEG;
 964         pixm->num_planes = frame->fmt->memplanes;
 965
 966         for (i = 0; i < pixm->num_planes; ++i) {
 967                 int bpl = frame->f_width;
 968                 if (frame->fmt->colplanes == 1) /* packed formats */
 969                         bpl = (bpl * frame->fmt->depth[0]) / 8;
 970                 pixm->plane_fmt[i].bytesperline = bpl;
 971                 pixm->plane_fmt[i].sizeimage = (frame->o_width *
 972                         frame->o_height * frame->fmt->depth[i]) / 8;
 973         }
 974         return 0;
 975 }
 976
 977 void fimc_fill_frame(struct fimc_frame *frame, struct v4l2_format *f)
 978 {
 979         struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
 980
 981         frame->f_width  = pixm->plane_fmt[0].bytesperline;
 982         if (frame->fmt->colplanes == 1)
 983                 frame->f_width = (frame->f_width * 8) / frame->fmt->depth[0];
 984         frame->f_height = pixm->height;
 985         frame->width    = pixm->width;
 986         frame->height   = pixm->height;
 987         frame->o_width  = pixm->width;
 988         frame->o_height = pixm->height;
 989         frame->offs_h   = 0;
 990         frame->offs_v   = 0;
 991 }
 992
 993 /**
 994  * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane
 995  * @fmt: fimc pixel format description (input)
 996  * @width: requested pixel width
 997  * @height: requested pixel height
 998  * @pix: multi-plane format to adjust
 999  */
1000 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
1001                                struct v4l2_pix_format_mplane *pix)
1002 {
1003         u32 bytesperline = 0;
1004         int i;
1005
1006         pix->colorspace = V4L2_COLORSPACE_JPEG;
1007         pix->field = V4L2_FIELD_NONE;
1008         pix->num_planes = fmt->memplanes;
1009         pix->pixelformat = fmt->fourcc;
1010         pix->height = height;
1011         pix->width = width;
1012
1013         for (i = 0; i < pix->num_planes; ++i) {
1014                 u32 bpl = pix->plane_fmt[i].bytesperline;
1015                 u32 *sizeimage = &pix->plane_fmt[i].sizeimage;
1016
1017                 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
1018                         bpl = pix->width; /* Planar */
1019
1020                 if (fmt->colplanes == 1 && /* Packed */
1021                     (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
1022                         bpl = (pix->width * fmt->depth[0]) / 8;
1023
1024                 if (i == 0) /* Same bytesperline for each plane. */
1025                         bytesperline = bpl;
1026
1027                 pix->plane_fmt[i].bytesperline = bytesperline;
1028                 *sizeimage = (pix->width * pix->height * fmt->depth[i]) / 8;
1029         }
1030 }
1031
1032 static int fimc_m2m_g_fmt_mplane(struct file *file, void *fh,
1033                                  struct v4l2_format *f)
1034 {
1035         struct fimc_ctx *ctx = fh_to_ctx(fh);
1036         struct fimc_frame *frame = ctx_get_frame(ctx, f->type);
1037
1038         if (IS_ERR(frame))
1039                 return PTR_ERR(frame);
1040
1041         return fimc_fill_format(frame, f);
1042 }
1043
1044 /**
1045  * fimc_find_format - lookup fimc color format by fourcc or media bus format
1046  * @pixelformat: fourcc to match, ignored if null
1047  * @mbus_code: media bus code to match, ignored if null
1048  * @mask: the color flags to match
1049  * @index: offset in the fimc_formats array, ignored if negative
1050  */
1051 struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code,
1052                                   unsigned int mask, int index)
1053 {
1054         struct fimc_fmt *fmt, *def_fmt = NULL;
1055         unsigned int i;
1056         int id = 0;
1057
1058         if (index >= (int)ARRAY_SIZE(fimc_formats))
1059                 return NULL;
1060
1061         for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
1062                 fmt = &fimc_formats[i];
1063                 if (!(fmt->flags & mask))
1064                         continue;
1065                 if (pixelformat && fmt->fourcc == *pixelformat)
1066                         return fmt;
1067                 if (mbus_code && fmt->mbus_code == *mbus_code)
1068                         return fmt;
1069                 if (index == id)
1070                         def_fmt = fmt;
1071                 id++;
1072         }
1073         return def_fmt;
1074 }
1075
1076 static int fimc_try_fmt_mplane(struct fimc_ctx *ctx, struct v4l2_format *f)
1077 {
1078         struct fimc_dev *fimc = ctx->fimc_dev;
1079         struct samsung_fimc_variant *variant = fimc->variant;
1080         struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1081         struct fimc_fmt *fmt;
1082         u32 max_w, mod_x, mod_y;
1083
1084         if (!IS_M2M(f->type))
1085                 return -EINVAL;
1086
1087         dbg("w: %d, h: %d", pix->width, pix->height);
1088
1089         fmt = fimc_find_format(&pix->pixelformat, NULL,
1090                                get_m2m_fmt_flags(f->type), 0);
1091         if (WARN(fmt == NULL, "Pixel format lookup failed"))
1092                 return -EINVAL;
1093
1094         if (pix->field == V4L2_FIELD_ANY)
1095                 pix->field = V4L2_FIELD_NONE;
1096         else if (pix->field != V4L2_FIELD_NONE)
1097                 return -EINVAL;
1098
1099         if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1100                 max_w = variant->pix_limit->scaler_dis_w;
1101                 mod_x = ffs(variant->min_inp_pixsize) - 1;
1102         } else {
1103                 max_w = variant->pix_limit->out_rot_dis_w;
1104                 mod_x = ffs(variant->min_out_pixsize) - 1;
1105         }
1106
1107         if (tiled_fmt(fmt)) {
1108                 mod_x = 6; /* 64 x 32 pixels tile */
1109                 mod_y = 5;
1110         } else {
1111                 if (variant->min_vsize_align == 1)
1112                         mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
1113                 else
1114                         mod_y = ffs(variant->min_vsize_align) - 1;
1115         }
1116
1117         v4l_bound_align_image(&pix->width, 16, max_w, mod_x,
1118                 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
1119
1120         fimc_adjust_mplane_format(fmt, pix->width, pix->height, &f->fmt.pix_mp);
1121         return 0;
1122 }
1123
1124 static int fimc_m2m_try_fmt_mplane(struct file *file, void *fh,
1125                                    struct v4l2_format *f)
1126 {
1127         struct fimc_ctx *ctx = fh_to_ctx(fh);
1128
1129         return fimc_try_fmt_mplane(ctx, f);
1130 }
1131
1132 static int fimc_m2m_s_fmt_mplane(struct file *file, void *fh,
1133                                  struct v4l2_format *f)
1134 {
1135         struct fimc_ctx *ctx = fh_to_ctx(fh);
1136         struct fimc_dev *fimc = ctx->fimc_dev;
1137         struct vb2_queue *vq;
1138         struct fimc_frame *frame;
1139         struct v4l2_pix_format_mplane *pix;
1140         int i, ret = 0;
1141
1142         ret = fimc_try_fmt_mplane(ctx, f);
1143         if (ret)
1144                 return ret;
1145
1146         vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
1147
1148         if (vb2_is_busy(vq)) {
1149                 v4l2_err(fimc->m2m.vfd, "queue (%d) busy\n", f->type);
1150                 return -EBUSY;
1151         }
1152
1153         if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1154                 frame = &ctx->s_frame;
1155         else
1156                 frame = &ctx->d_frame;
1157
1158         pix = &f->fmt.pix_mp;
1159         frame->fmt = fimc_find_format(&pix->pixelformat, NULL,
1160                                       get_m2m_fmt_flags(f->type), 0);
1161         if (!frame->fmt)
1162                 return -EINVAL;
1163
1164         /* Update RGB Alpha control state and value range */
1165         fimc_alpha_ctrl_update(ctx);
1166
1167         for (i = 0; i < frame->fmt->colplanes; i++) {
1168                 frame->payload[i] =
1169                         (pix->width * pix->height * frame->fmt->depth[i]) / 8;
1170         }
1171
1172         fimc_fill_frame(frame, f);
1173
1174         ctx->scaler.enabled = 1;
1175
1176         if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1177                 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
1178         else
1179                 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
1180
1181         dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
1182
1183         return 0;
1184 }
1185
1186 static int fimc_m2m_reqbufs(struct file *file, void *fh,
1187                             struct v4l2_requestbuffers *reqbufs)
1188 {
1189         struct fimc_ctx *ctx = fh_to_ctx(fh);
1190
1191         return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1192 }
1193
1194 static int fimc_m2m_querybuf(struct file *file, void *fh,
1195                              struct v4l2_buffer *buf)
1196 {
1197         struct fimc_ctx *ctx = fh_to_ctx(fh);
1198
1199         return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1200 }
1201
1202 static int fimc_m2m_qbuf(struct file *file, void *fh,
1203                          struct v4l2_buffer *buf)
1204 {
1205         struct fimc_ctx *ctx = fh_to_ctx(fh);
1206
1207         return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1208 }
1209
1210 static int fimc_m2m_dqbuf(struct file *file, void *fh,
1211                           struct v4l2_buffer *buf)
1212 {
1213         struct fimc_ctx *ctx = fh_to_ctx(fh);
1214
1215         return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1216 }
1217
1218 static int fimc_m2m_streamon(struct file *file, void *fh,
1219                              enum v4l2_buf_type type)
1220 {
1221         struct fimc_ctx *ctx = fh_to_ctx(fh);
1222
1223         /* The source and target color format need to be set */
1224         if (V4L2_TYPE_IS_OUTPUT(type)) {
1225                 if (!fimc_ctx_state_is_set(FIMC_SRC_FMT, ctx))
1226                         return -EINVAL;
1227         } else if (!fimc_ctx_state_is_set(FIMC_DST_FMT, ctx)) {
1228                 return -EINVAL;
1229         }
1230
1231         return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1232 }
1233
1234 static int fimc_m2m_streamoff(struct file *file, void *fh,
1235                             enum v4l2_buf_type type)
1236 {
1237         struct fimc_ctx *ctx = fh_to_ctx(fh);
1238
1239         return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1240 }
1241
1242 static int fimc_m2m_cropcap(struct file *file, void *fh,
1243                             struct v4l2_cropcap *cr)
1244 {
1245         struct fimc_ctx *ctx = fh_to_ctx(fh);
1246         struct fimc_frame *frame;
1247
1248         frame = ctx_get_frame(ctx, cr->type);
1249         if (IS_ERR(frame))
1250                 return PTR_ERR(frame);
1251
1252         cr->bounds.left         = 0;
1253         cr->bounds.top          = 0;
1254         cr->bounds.width        = frame->o_width;
1255         cr->bounds.height       = frame->o_height;
1256         cr->defrect             = cr->bounds;
1257
1258         return 0;
1259 }
1260
1261 static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1262 {
1263         struct fimc_ctx *ctx = fh_to_ctx(fh);
1264         struct fimc_frame *frame;
1265
1266         frame = ctx_get_frame(ctx, cr->type);
1267         if (IS_ERR(frame))
1268                 return PTR_ERR(frame);
1269
1270         cr->c.left = frame->offs_h;
1271         cr->c.top = frame->offs_v;
1272         cr->c.width = frame->width;
1273         cr->c.height = frame->height;
1274
1275         return 0;
1276 }
1277
1278 static int fimc_m2m_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1279 {
1280         struct fimc_dev *fimc = ctx->fimc_dev;
1281         struct fimc_frame *f;
1282         u32 min_size, halign, depth = 0;
1283         int i;
1284
1285         if (cr->c.top < 0 || cr->c.left < 0) {
1286                 v4l2_err(fimc->m2m.vfd,
1287                         "doesn't support negative values for top & left\n");
1288                 return -EINVAL;
1289         }
1290         if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1291                 f = &ctx->d_frame;
1292         else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1293                 f = &ctx->s_frame;
1294         else
1295                 return -EINVAL;
1296
1297         min_size = (f == &ctx->s_frame) ?
1298                 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1299
1300         /* Get pixel alignment constraints. */
1301         if (fimc->variant->min_vsize_align == 1)
1302                 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1303         else
1304                 halign = ffs(fimc->variant->min_vsize_align) - 1;
1305
1306         for (i = 0; i < f->fmt->colplanes; i++)
1307                 depth += f->fmt->depth[i];
1308
1309         v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1310                               ffs(min_size) - 1,
1311                               &cr->c.height, min_size, f->o_height,
1312                               halign, 64/(ALIGN(depth, 8)));
1313
1314         /* adjust left/top if cropping rectangle is out of bounds */
1315         if (cr->c.left + cr->c.width > f->o_width)
1316                 cr->c.left = f->o_width - cr->c.width;
1317         if (cr->c.top + cr->c.height > f->o_height)
1318                 cr->c.top = f->o_height - cr->c.height;
1319
1320         cr->c.left = round_down(cr->c.left, min_size);
1321         cr->c.top  = round_down(cr->c.top, fimc->variant->hor_offs_align);
1322
1323         dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1324             cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1325             f->f_width, f->f_height);
1326
1327         return 0;
1328 }
1329
1330 static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1331 {
1332         struct fimc_ctx *ctx = fh_to_ctx(fh);
1333         struct fimc_dev *fimc = ctx->fimc_dev;
1334         struct fimc_frame *f;
1335         int ret;
1336
1337         ret = fimc_m2m_try_crop(ctx, cr);
1338         if (ret)
1339                 return ret;
1340
1341         f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1342                 &ctx->s_frame : &ctx->d_frame;
1343
1344         /* Check to see if scaling ratio is within supported range */
1345         if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1346                 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1347                         ret = fimc_check_scaler_ratio(ctx, cr->c.width,
1348                                         cr->c.height, ctx->d_frame.width,
1349                                         ctx->d_frame.height, ctx->rotation);
1350                 } else {
1351                         ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
1352                                         ctx->s_frame.height, cr->c.width,
1353                                         cr->c.height, ctx->rotation);
1354                 }
1355                 if (ret) {
1356                         v4l2_err(fimc->m2m.vfd, "Out of scaler range\n");
1357                         return -EINVAL;
1358                 }
1359         }
1360
1361         f->offs_h = cr->c.left;
1362         f->offs_v = cr->c.top;
1363         f->width  = cr->c.width;
1364         f->height = cr->c.height;
1365
1366         fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1367
1368         return 0;
1369 }
1370
1371 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1372         .vidioc_querycap                = fimc_m2m_querycap,
1373
1374         .vidioc_enum_fmt_vid_cap_mplane = fimc_m2m_enum_fmt_mplane,
1375         .vidioc_enum_fmt_vid_out_mplane = fimc_m2m_enum_fmt_mplane,
1376
1377         .vidioc_g_fmt_vid_cap_mplane    = fimc_m2m_g_fmt_mplane,
1378         .vidioc_g_fmt_vid_out_mplane    = fimc_m2m_g_fmt_mplane,
1379
1380         .vidioc_try_fmt_vid_cap_mplane  = fimc_m2m_try_fmt_mplane,
1381         .vidioc_try_fmt_vid_out_mplane  = fimc_m2m_try_fmt_mplane,
1382
1383         .vidioc_s_fmt_vid_cap_mplane    = fimc_m2m_s_fmt_mplane,
1384         .vidioc_s_fmt_vid_out_mplane    = fimc_m2m_s_fmt_mplane,
1385
1386         .vidioc_reqbufs                 = fimc_m2m_reqbufs,
1387         .vidioc_querybuf                = fimc_m2m_querybuf,
1388
1389         .vidioc_qbuf                    = fimc_m2m_qbuf,
1390         .vidioc_dqbuf                   = fimc_m2m_dqbuf,
1391
1392         .vidioc_streamon                = fimc_m2m_streamon,
1393         .vidioc_streamoff               = fimc_m2m_streamoff,
1394
1395         .vidioc_g_crop                  = fimc_m2m_g_crop,
1396         .vidioc_s_crop                  = fimc_m2m_s_crop,
1397         .vidioc_cropcap                 = fimc_m2m_cropcap
1398
1399 };
1400
1401 static int queue_init(void *priv, struct vb2_queue *src_vq,
1402                       struct vb2_queue *dst_vq)
1403 {
1404         struct fimc_ctx *ctx = priv;
1405         int ret;
1406
1407         memset(src_vq, 0, sizeof(*src_vq));
1408         src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1409         src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1410         src_vq->drv_priv = ctx;
1411         src_vq->ops = &fimc_qops;
1412         src_vq->mem_ops = &vb2_dma_contig_memops;
1413         src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1414
1415         ret = vb2_queue_init(src_vq);
1416         if (ret)
1417                 return ret;
1418
1419         memset(dst_vq, 0, sizeof(*dst_vq));
1420         dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1421         dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1422         dst_vq->drv_priv = ctx;
1423         dst_vq->ops = &fimc_qops;
1424         dst_vq->mem_ops = &vb2_dma_contig_memops;
1425         dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1426
1427         return vb2_queue_init(dst_vq);
1428 }
1429
1430 static int fimc_m2m_open(struct file *file)
1431 {
1432         struct fimc_dev *fimc = video_drvdata(file);
1433         struct fimc_ctx *ctx;
1434         int ret;
1435
1436         dbg("pid: %d, state: 0x%lx, refcnt: %d",
1437                 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1438
1439         /*
1440          * Return if the corresponding video capture node
1441          * is already opened.
1442          */
1443         if (fimc->vid_cap.refcnt > 0)
1444                 return -EBUSY;
1445
1446         ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1447         if (!ctx)
1448                 return -ENOMEM;
1449         v4l2_fh_init(&ctx->fh, fimc->m2m.vfd);
1450         ctx->fimc_dev = fimc;
1451
1452         /* Default color format */
1453         ctx->s_frame.fmt = &fimc_formats[0];
1454         ctx->d_frame.fmt = &fimc_formats[0];
1455
1456         ret = fimc_ctrls_create(ctx);
1457         if (ret)
1458                 goto error_fh;
1459
1460         /* Use separate control handler per file handle */
1461         ctx->fh.ctrl_handler = &ctx->ctrl_handler;
1462         file->private_data = &ctx->fh;
1463         v4l2_fh_add(&ctx->fh);
1464
1465         /* Setup the device context for memory-to-memory mode */
1466         ctx->state = FIMC_CTX_M2M;
1467         ctx->flags = 0;
1468         ctx->in_path = FIMC_DMA;
1469         ctx->out_path = FIMC_DMA;
1470         spin_lock_init(&ctx->slock);
1471
1472         ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1473         if (IS_ERR(ctx->m2m_ctx)) {
1474                 ret = PTR_ERR(ctx->m2m_ctx);
1475                 goto error_c;
1476         }
1477
1478         if (fimc->m2m.refcnt++ == 0)
1479                 set_bit(ST_M2M_RUN, &fimc->state);
1480         return 0;
1481
1482 error_c:
1483         fimc_ctrls_delete(ctx);
1484 error_fh:
1485         v4l2_fh_del(&ctx->fh);
1486         v4l2_fh_exit(&ctx->fh);
1487         kfree(ctx);
1488         return ret;
1489 }
1490
1491 static int fimc_m2m_release(struct file *file)
1492 {
1493         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1494         struct fimc_dev *fimc = ctx->fimc_dev;
1495
1496         dbg("pid: %d, state: 0x%lx, refcnt= %d",
1497                 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1498
1499         v4l2_m2m_ctx_release(ctx->m2m_ctx);
1500         fimc_ctrls_delete(ctx);
1501         v4l2_fh_del(&ctx->fh);
1502         v4l2_fh_exit(&ctx->fh);
1503
1504         if (--fimc->m2m.refcnt <= 0)
1505                 clear_bit(ST_M2M_RUN, &fimc->state);
1506         kfree(ctx);
1507         return 0;
1508 }
1509
1510 static unsigned int fimc_m2m_poll(struct file *file,
1511                                   struct poll_table_struct *wait)
1512 {
1513         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1514
1515         return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1516 }
1517
1518
1519 static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1520 {
1521         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1522
1523         return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1524 }
1525
1526 static const struct v4l2_file_operations fimc_m2m_fops = {
1527         .owner          = THIS_MODULE,
1528         .open           = fimc_m2m_open,
1529         .release        = fimc_m2m_release,
1530         .poll           = fimc_m2m_poll,
1531         .unlocked_ioctl = video_ioctl2,
1532         .mmap           = fimc_m2m_mmap,
1533 };
1534
1535 static struct v4l2_m2m_ops m2m_ops = {
1536         .device_run     = fimc_dma_run,
1537         .job_abort      = fimc_job_abort,
1538 };
1539
1540 int fimc_register_m2m_device(struct fimc_dev *fimc,
1541                              struct v4l2_device *v4l2_dev)
1542 {
1543         struct video_device *vfd;
1544         struct platform_device *pdev;
1545         int ret = 0;
1546
1547         if (!fimc)
1548                 return -ENODEV;
1549
1550         pdev = fimc->pdev;
1551         fimc->v4l2_dev = v4l2_dev;
1552
1553         vfd = video_device_alloc();
1554         if (!vfd) {
1555                 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1556                 return -ENOMEM;
1557         }
1558
1559         vfd->fops       = &fimc_m2m_fops;
1560         vfd->ioctl_ops  = &fimc_m2m_ioctl_ops;
1561         vfd->v4l2_dev   = v4l2_dev;
1562         vfd->minor      = -1;
1563         vfd->release    = video_device_release;
1564         vfd->lock       = &fimc->lock;
1565
1566         snprintf(vfd->name, sizeof(vfd->name), "%s.m2m", dev_name(&pdev->dev));
1567         video_set_drvdata(vfd, fimc);
1568
1569         fimc->m2m.vfd = vfd;
1570         fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1571         if (IS_ERR(fimc->m2m.m2m_dev)) {
1572                 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1573                 ret = PTR_ERR(fimc->m2m.m2m_dev);
1574                 goto err_init;
1575         }
1576
1577         ret = media_entity_init(&vfd->entity, 0, NULL, 0);
1578         if (!ret)
1579                 return 0;
1580
1581         v4l2_m2m_release(fimc->m2m.m2m_dev);
1582 err_init:
1583         video_device_release(fimc->m2m.vfd);
1584         return ret;
1585 }
1586
1587 void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1588 {
1589         if (!fimc)
1590                 return;
1591
1592         if (fimc->m2m.m2m_dev)
1593                 v4l2_m2m_release(fimc->m2m.m2m_dev);
1594         if (fimc->m2m.vfd) {
1595                 media_entity_cleanup(&fimc->m2m.vfd->entity);
1596                 /* Can also be called if video device wasn't registered */
1597                 video_unregister_device(fimc->m2m.vfd);
1598         }
1599 }
1600
1601 static void fimc_clk_put(struct fimc_dev *fimc)
1602 {
1603         int i;
1604         for (i = 0; i < fimc->num_clocks; i++) {
1605                 if (IS_ERR_OR_NULL(fimc->clock[i]))
1606                         continue;
1607                 clk_unprepare(fimc->clock[i]);
1608                 clk_put(fimc->clock[i]);
1609                 fimc->clock[i] = NULL;
1610         }
1611 }
1612
1613 static int fimc_clk_get(struct fimc_dev *fimc)
1614 {
1615         int i, ret;
1616
1617         for (i = 0; i < fimc->num_clocks; i++) {
1618                 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1619                 if (IS_ERR(fimc->clock[i]))
1620                         goto err;
1621                 ret = clk_prepare(fimc->clock[i]);
1622                 if (ret < 0) {
1623                         clk_put(fimc->clock[i]);
1624                         fimc->clock[i] = NULL;
1625                         goto err;
1626                 }
1627         }
1628         return 0;
1629 err:
1630         fimc_clk_put(fimc);
1631         dev_err(&fimc->pdev->dev, "failed to get clock: %s\n",
1632                 fimc_clocks[i]);
1633         return -ENXIO;
1634 }
1635
1636 static int fimc_m2m_suspend(struct fimc_dev *fimc)
1637 {
1638         unsigned long flags;
1639         int timeout;
1640
1641         spin_lock_irqsave(&fimc->slock, flags);
1642         if (!fimc_m2m_pending(fimc)) {
1643                 spin_unlock_irqrestore(&fimc->slock, flags);
1644                 return 0;
1645         }
1646         clear_bit(ST_M2M_SUSPENDED, &fimc->state);
1647         set_bit(ST_M2M_SUSPENDING, &fimc->state);
1648         spin_unlock_irqrestore(&fimc->slock, flags);
1649
1650         timeout = wait_event_timeout(fimc->irq_queue,
1651                              test_bit(ST_M2M_SUSPENDED, &fimc->state),
1652                              FIMC_SHUTDOWN_TIMEOUT);
1653
1654         clear_bit(ST_M2M_SUSPENDING, &fimc->state);
1655         return timeout == 0 ? -EAGAIN : 0;
1656 }
1657
1658 static int fimc_m2m_resume(struct fimc_dev *fimc)
1659 {
1660         unsigned long flags;
1661
1662         spin_lock_irqsave(&fimc->slock, flags);
1663         /* Clear for full H/W setup in first run after resume */
1664         fimc->m2m.ctx = NULL;
1665         spin_unlock_irqrestore(&fimc->slock, flags);
1666
1667         if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state))
1668                 fimc_m2m_job_finish(fimc->m2m.ctx,
1669                                     VB2_BUF_STATE_ERROR);
1670         return 0;
1671 }
1672
1673 static int fimc_probe(struct platform_device *pdev)
1674 {
1675         struct fimc_dev *fimc;
1676         struct resource *res;
1677         struct samsung_fimc_driverdata *drv_data;
1678         struct s5p_platform_fimc *pdata;
1679         int ret = 0;
1680
1681         drv_data = (struct samsung_fimc_driverdata *)
1682                 platform_get_device_id(pdev)->driver_data;
1683
1684         if (pdev->id >= drv_data->num_entities) {
1685                 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1686                         pdev->id);
1687                 return -EINVAL;
1688         }
1689
1690         fimc = devm_kzalloc(&pdev->dev, sizeof(*fimc), GFP_KERNEL);
1691         if (!fimc)
1692                 return -ENOMEM;
1693
1694         fimc->id = pdev->id;
1695
1696         fimc->variant = drv_data->variant[fimc->id];
1697         fimc->pdev = pdev;
1698         pdata = pdev->dev.platform_data;
1699         fimc->pdata = pdata;
1700
1701         init_waitqueue_head(&fimc->irq_queue);
1702         spin_lock_init(&fimc->slock);
1703         mutex_init(&fimc->lock);
1704
1705         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1706         fimc->regs = devm_request_and_ioremap(&pdev->dev, res);
1707         if (fimc->regs == NULL) {
1708                 dev_err(&pdev->dev, "Failed to obtain io memory\n");
1709                 return -ENOENT;
1710         }
1711
1712         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1713         if (res == NULL) {
1714                 dev_err(&pdev->dev, "Failed to get IRQ resource\n");
1715                 return -ENXIO;
1716         }
1717         fimc->irq = res->start;
1718
1719         fimc->num_clocks = MAX_FIMC_CLOCKS;
1720         ret = fimc_clk_get(fimc);
1721         if (ret)
1722                 return ret;
1723         clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1724         clk_enable(fimc->clock[CLK_BUS]);
1725
1726         platform_set_drvdata(pdev, fimc);
1727
1728         ret = devm_request_irq(&pdev->dev, fimc->irq, fimc_irq_handler,
1729                                0, pdev->name, fimc);
1730         if (ret) {
1731                 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1732                 goto err_clk;
1733         }
1734
1735         pm_runtime_enable(&pdev->dev);
1736         ret = pm_runtime_get_sync(&pdev->dev);
1737         if (ret < 0)
1738                 goto err_clk;
1739         /* Initialize contiguous memory allocator */
1740         fimc->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1741         if (IS_ERR(fimc->alloc_ctx)) {
1742                 ret = PTR_ERR(fimc->alloc_ctx);
1743                 goto err_pm;
1744         }
1745
1746         dev_dbg(&pdev->dev, "FIMC.%d registered successfully\n", fimc->id);
1747
1748         pm_runtime_put(&pdev->dev);
1749         return 0;
1750
1751 err_pm:
1752         pm_runtime_put(&pdev->dev);
1753 err_clk:
1754         fimc_clk_put(fimc);
1755         return ret;
1756 }
1757
1758 static int fimc_runtime_resume(struct device *dev)
1759 {
1760         struct fimc_dev *fimc = dev_get_drvdata(dev);
1761
1762         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1763
1764         /* Enable clocks and perform basic initalization */
1765         clk_enable(fimc->clock[CLK_GATE]);
1766         fimc_hw_reset(fimc);
1767
1768         /* Resume the capture or mem-to-mem device */
1769         if (fimc_capture_busy(fimc))
1770                 return fimc_capture_resume(fimc);
1771
1772         return fimc_m2m_resume(fimc);
1773 }
1774
1775 static int fimc_runtime_suspend(struct device *dev)
1776 {
1777         struct fimc_dev *fimc = dev_get_drvdata(dev);
1778         int ret = 0;
1779
1780         if (fimc_capture_busy(fimc))
1781                 ret = fimc_capture_suspend(fimc);
1782         else
1783                 ret = fimc_m2m_suspend(fimc);
1784         if (!ret)
1785                 clk_disable(fimc->clock[CLK_GATE]);
1786
1787         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1788         return ret;
1789 }
1790
1791 #ifdef CONFIG_PM_SLEEP
1792 static int fimc_resume(struct device *dev)
1793 {
1794         struct fimc_dev *fimc = dev_get_drvdata(dev);
1795         unsigned long flags;
1796
1797         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1798
1799         /* Do not resume if the device was idle before system suspend */
1800         spin_lock_irqsave(&fimc->slock, flags);
1801         if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
1802             (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) {
1803                 spin_unlock_irqrestore(&fimc->slock, flags);
1804                 return 0;
1805         }
1806         fimc_hw_reset(fimc);
1807         spin_unlock_irqrestore(&fimc->slock, flags);
1808
1809         if (fimc_capture_busy(fimc))
1810                 return fimc_capture_resume(fimc);
1811
1812         return fimc_m2m_resume(fimc);
1813 }
1814
1815 static int fimc_suspend(struct device *dev)
1816 {
1817         struct fimc_dev *fimc = dev_get_drvdata(dev);
1818
1819         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1820
1821         if (test_and_set_bit(ST_LPM, &fimc->state))
1822                 return 0;
1823         if (fimc_capture_busy(fimc))
1824                 return fimc_capture_suspend(fimc);
1825
1826         return fimc_m2m_suspend(fimc);
1827 }
1828 #endif /* CONFIG_PM_SLEEP */
1829
1830 static int __devexit fimc_remove(struct platform_device *pdev)
1831 {
1832         struct fimc_dev *fimc = platform_get_drvdata(pdev);
1833
1834         pm_runtime_disable(&pdev->dev);
1835         pm_runtime_set_suspended(&pdev->dev);
1836
1837         vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1838
1839         clk_disable(fimc->clock[CLK_BUS]);
1840         fimc_clk_put(fimc);
1841
1842         dev_info(&pdev->dev, "driver unloaded\n");
1843         return 0;
1844 }
1845
1846 /* Image pixel limits, similar across several FIMC HW revisions. */
1847 static struct fimc_pix_limit s5p_pix_limit[4] = {
1848         [0] = {
1849                 .scaler_en_w    = 3264,
1850                 .scaler_dis_w   = 8192,
1851                 .in_rot_en_h    = 1920,
1852                 .in_rot_dis_w   = 8192,
1853                 .out_rot_en_w   = 1920,
1854                 .out_rot_dis_w  = 4224,
1855         },
1856         [1] = {
1857                 .scaler_en_w    = 4224,
1858                 .scaler_dis_w   = 8192,
1859                 .in_rot_en_h    = 1920,
1860                 .in_rot_dis_w   = 8192,
1861                 .out_rot_en_w   = 1920,
1862                 .out_rot_dis_w  = 4224,
1863         },
1864         [2] = {
1865                 .scaler_en_w    = 1920,
1866                 .scaler_dis_w   = 8192,
1867                 .in_rot_en_h    = 1280,
1868                 .in_rot_dis_w   = 8192,
1869                 .out_rot_en_w   = 1280,
1870                 .out_rot_dis_w  = 1920,
1871         },
1872         [3] = {
1873                 .scaler_en_w    = 1920,
1874                 .scaler_dis_w   = 8192,
1875                 .in_rot_en_h    = 1366,
1876                 .in_rot_dis_w   = 8192,
1877                 .out_rot_en_w   = 1366,
1878                 .out_rot_dis_w  = 1920,
1879         },
1880 };
1881
1882 static struct samsung_fimc_variant fimc0_variant_s5p = {
1883         .has_inp_rot     = 1,
1884         .has_out_rot     = 1,
1885         .has_cam_if      = 1,
1886         .min_inp_pixsize = 16,
1887         .min_out_pixsize = 16,
1888         .hor_offs_align  = 8,
1889         .min_vsize_align = 16,
1890         .out_buf_count   = 4,
1891         .pix_limit       = &s5p_pix_limit[0],
1892 };
1893
1894 static struct samsung_fimc_variant fimc2_variant_s5p = {
1895         .has_cam_if      = 1,
1896         .min_inp_pixsize = 16,
1897         .min_out_pixsize = 16,
1898         .hor_offs_align  = 8,
1899         .min_vsize_align = 16,
1900         .out_buf_count   = 4,
1901         .pix_limit = &s5p_pix_limit[1],
1902 };
1903
1904 static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1905         .pix_hoff        = 1,
1906         .has_inp_rot     = 1,
1907         .has_out_rot     = 1,
1908         .has_cam_if      = 1,
1909         .min_inp_pixsize = 16,
1910         .min_out_pixsize = 16,
1911         .hor_offs_align  = 8,
1912         .min_vsize_align = 16,
1913         .out_buf_count   = 4,
1914         .pix_limit       = &s5p_pix_limit[1],
1915 };
1916
1917 static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1918         .pix_hoff        = 1,
1919         .has_inp_rot     = 1,
1920         .has_out_rot     = 1,
1921         .has_cam_if      = 1,
1922         .has_mainscaler_ext = 1,
1923         .min_inp_pixsize = 16,
1924         .min_out_pixsize = 16,
1925         .hor_offs_align  = 1,
1926         .min_vsize_align = 1,
1927         .out_buf_count   = 4,
1928         .pix_limit       = &s5p_pix_limit[2],
1929 };
1930
1931 static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1932         .has_cam_if      = 1,
1933         .pix_hoff        = 1,
1934         .min_inp_pixsize = 16,
1935         .min_out_pixsize = 16,
1936         .hor_offs_align  = 8,
1937         .min_vsize_align = 16,
1938         .out_buf_count   = 4,
1939         .pix_limit       = &s5p_pix_limit[2],
1940 };
1941
1942 static struct samsung_fimc_variant fimc0_variant_exynos4 = {
1943         .pix_hoff        = 1,
1944         .has_inp_rot     = 1,
1945         .has_out_rot     = 1,
1946         .has_cam_if      = 1,
1947         .has_cistatus2   = 1,
1948         .has_mainscaler_ext = 1,
1949         .has_alpha       = 1,
1950         .min_inp_pixsize = 16,
1951         .min_out_pixsize = 16,
1952         .hor_offs_align  = 2,
1953         .min_vsize_align = 1,
1954         .out_buf_count   = 32,
1955         .pix_limit       = &s5p_pix_limit[1],
1956 };
1957
1958 static struct samsung_fimc_variant fimc3_variant_exynos4 = {
1959         .pix_hoff        = 1,
1960         .has_cam_if      = 1,
1961         .has_cistatus2   = 1,
1962         .has_mainscaler_ext = 1,
1963         .has_alpha       = 1,
1964         .min_inp_pixsize = 16,
1965         .min_out_pixsize = 16,
1966         .hor_offs_align  = 2,
1967         .min_vsize_align = 1,
1968         .out_buf_count   = 32,
1969         .pix_limit       = &s5p_pix_limit[3],
1970 };
1971
1972 /* S5PC100 */
1973 static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1974         .variant = {
1975                 [0] = &fimc0_variant_s5p,
1976                 [1] = &fimc0_variant_s5p,
1977                 [2] = &fimc2_variant_s5p,
1978         },
1979         .num_entities = 3,
1980         .lclk_frequency = 133000000UL,
1981 };
1982
1983 /* S5PV210, S5PC110 */
1984 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1985         .variant = {
1986                 [0] = &fimc0_variant_s5pv210,
1987                 [1] = &fimc1_variant_s5pv210,
1988                 [2] = &fimc2_variant_s5pv210,
1989         },
1990         .num_entities = 3,
1991         .lclk_frequency = 166000000UL,
1992 };
1993
1994 /* S5PV310, S5PC210 */
1995 static struct samsung_fimc_driverdata fimc_drvdata_exynos4 = {
1996         .variant = {
1997                 [0] = &fimc0_variant_exynos4,
1998                 [1] = &fimc0_variant_exynos4,
1999                 [2] = &fimc0_variant_exynos4,
2000                 [3] = &fimc3_variant_exynos4,
2001         },
2002         .num_entities = 4,
2003         .lclk_frequency = 166000000UL,
2004 };
2005
2006 static struct platform_device_id fimc_driver_ids[] = {
2007         {
2008                 .name           = "s5p-fimc",
2009                 .driver_data    = (unsigned long)&fimc_drvdata_s5p,
2010         }, {
2011                 .name           = "s5pv210-fimc",
2012                 .driver_data    = (unsigned long)&fimc_drvdata_s5pv210,
2013         }, {
2014                 .name           = "exynos4-fimc",
2015                 .driver_data    = (unsigned long)&fimc_drvdata_exynos4,
2016         },
2017         {},
2018 };
2019 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
2020
2021 static const struct dev_pm_ops fimc_pm_ops = {
2022         SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
2023         SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
2024 };
2025
2026 static struct platform_driver fimc_driver = {
2027         .probe          = fimc_probe,
2028         .remove         = __devexit_p(fimc_remove),
2029         .id_table       = fimc_driver_ids,
2030         .driver = {
2031                 .name   = FIMC_MODULE_NAME,
2032                 .owner  = THIS_MODULE,
2033                 .pm     = &fimc_pm_ops,
2034         }
2035 };
2036
2037 int __init fimc_register_driver(void)
2038 {
2039         return platform_driver_probe(&fimc_driver, fimc_probe);
2040 }
2041
2042 void __exit fimc_unregister_driver(void)
2043 {
2044         platform_driver_unregister(&fimc_driver);
2045 }