drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "drm_fb_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "../../../platform/x86/intel_ips.h"
  38 #include <linux/pci.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/acpi.h>
  41 #include <linux/pnp.h>
  42 #include <linux/vga_switcheroo.h>
  43 #include <linux/slab.h>
  44 #include <linux/module.h>
  45 #include <acpi/video.h>
  46
  47 static void i915_write_hws_pga(struct drm_device *dev)
  48 {
  49         drm_i915_private_t *dev_priv = dev->dev_private;
  50         u32 addr;
  51
  52         addr = dev_priv->status_page_dmah->busaddr;
  53         if (INTEL_INFO(dev)->gen >= 4)
  54                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  55         I915_WRITE(HWS_PGA, addr);
  56 }
  57
  58 /**
  59  * Sets up the hardware status page for devices that need a physical address
  60  * in the register.
  61  */
  62 static int i915_init_phys_hws(struct drm_device *dev)
  63 {
  64         drm_i915_private_t *dev_priv = dev->dev_private;
  65
  66         /* Program Hardware Status Page */
  67         dev_priv->status_page_dmah =
  68                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  69
  70         if (!dev_priv->status_page_dmah) {
  71                 DRM_ERROR("Can not allocate hardware status page\n");
  72                 return -ENOMEM;
  73         }
  74
  75         memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr,
  76                   0, PAGE_SIZE);
  77
  78         i915_write_hws_pga(dev);
  79
  80         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  81         return 0;
  82 }
  83
  84 /**
  85  * Frees the hardware status page, whether it's a physical address or a virtual
  86  * address set up by the X Server.
  87  */
  88 static void i915_free_hws(struct drm_device *dev)
  89 {
  90         drm_i915_private_t *dev_priv = dev->dev_private;
  91         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  92
  93         if (dev_priv->status_page_dmah) {
  94                 drm_pci_free(dev, dev_priv->status_page_dmah);
  95                 dev_priv->status_page_dmah = NULL;
  96         }
  97
  98         if (ring->status_page.gfx_addr) {
  99                 ring->status_page.gfx_addr = 0;
 100                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 101         }
 102
 103         /* Need to rewrite hardware status page */
 104         I915_WRITE(HWS_PGA, 0x1ffff000);
 105 }
 106
 107 void i915_kernel_lost_context(struct drm_device * dev)
 108 {
 109         drm_i915_private_t *dev_priv = dev->dev_private;
 110         struct drm_i915_master_private *master_priv;
 111         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 112
 113         /*
 114          * We should never lose context on the ring with modesetting
 115          * as we don't expose it to userspace
 116          */
 117         if (drm_core_check_feature(dev, DRIVER_MODESET))
 118                 return;
 119
 120         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 121         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 122         ring->space = ring->head - (ring->tail + 8);
 123         if (ring->space < 0)
 124                 ring->space += ring->size;
 125
 126         if (!dev->primary->master)
 127                 return;
 128
 129         master_priv = dev->primary->master->driver_priv;
 130         if (ring->head == ring->tail && master_priv->sarea_priv)
 131                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 132 }
 133
 134 static int i915_dma_cleanup(struct drm_device * dev)
 135 {
 136         drm_i915_private_t *dev_priv = dev->dev_private;
 137         int i;
 138
 139         /* Make sure interrupts are disabled here because the uninstall ioctl
 140          * may not have been called from userspace and after dev_private
 141          * is freed, it's too late.
 142          */
 143         if (dev->irq_enabled)
 144                 drm_irq_uninstall(dev);
 145
 146         mutex_lock(&dev->struct_mutex);
 147         for (i = 0; i < I915_NUM_RINGS; i++)
 148                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 149         mutex_unlock(&dev->struct_mutex);
 150
 151         /* Clear the HWS virtual address at teardown */
 152         if (I915_NEED_GFX_HWS(dev))
 153                 i915_free_hws(dev);
 154
 155         return 0;
 156 }
 157
 158 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 159 {
 160         drm_i915_private_t *dev_priv = dev->dev_private;
 161         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 162         int ret;
 163
 164         master_priv->sarea = drm_getsarea(dev);
 165         if (master_priv->sarea) {
 166                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 167                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 168         } else {
 169                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 170         }
 171
 172         if (init->ring_size != 0) {
 173                 if (LP_RING(dev_priv)->obj != NULL) {
 174                         i915_dma_cleanup(dev);
 175                         DRM_ERROR("Client tried to initialize ringbuffer in "
 176                                   "GEM mode\n");
 177                         return -EINVAL;
 178                 }
 179
 180                 ret = intel_render_ring_init_dri(dev,
 181                                                  init->ring_start,
 182                                                  init->ring_size);
 183                 if (ret) {
 184                         i915_dma_cleanup(dev);
 185                         return ret;
 186                 }
 187         }
 188
 189         dev_priv->cpp = init->cpp;
 190         dev_priv->back_offset = init->back_offset;
 191         dev_priv->front_offset = init->front_offset;
 192         dev_priv->current_page = 0;
 193         if (master_priv->sarea_priv)
 194                 master_priv->sarea_priv->pf_current_page = 0;
 195
 196         /* Allow hardware batchbuffers unless told otherwise.
 197          */
 198         dev_priv->allow_batchbuffer = 1;
 199
 200         return 0;
 201 }
 202
 203 static int i915_dma_resume(struct drm_device * dev)
 204 {
 205         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 206         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 207
 208         DRM_DEBUG_DRIVER("%s\n", __func__);
 209
 210         if (ring->map.handle == NULL) {
 211                 DRM_ERROR("can not ioremap virtual address for"
 212                           " ring buffer\n");
 213                 return -ENOMEM;
 214         }
 215
 216         /* Program Hardware Status Page */
 217         if (!ring->status_page.page_addr) {
 218                 DRM_ERROR("Can not find hardware status page\n");
 219                 return -EINVAL;
 220         }
 221         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 222                                 ring->status_page.page_addr);
 223         if (ring->status_page.gfx_addr != 0)
 224                 intel_ring_setup_status_page(ring);
 225         else
 226                 i915_write_hws_pga(dev);
 227
 228         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 229
 230         return 0;
 231 }
 232
 233 static int i915_dma_init(struct drm_device *dev, void *data,
 234                          struct drm_file *file_priv)
 235 {
 236         drm_i915_init_t *init = data;
 237         int retcode = 0;
 238
 239         switch (init->func) {
 240         case I915_INIT_DMA:
 241                 retcode = i915_initialize(dev, init);
 242                 break;
 243         case I915_CLEANUP_DMA:
 244                 retcode = i915_dma_cleanup(dev);
 245                 break;
 246         case I915_RESUME_DMA:
 247                 retcode = i915_dma_resume(dev);
 248                 break;
 249         default:
 250                 retcode = -EINVAL;
 251                 break;
 252         }
 253
 254         return retcode;
 255 }
 256
 257 /* Implement basically the same security restrictions as hardware does
 258  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 259  *
 260  * Most of the calculations below involve calculating the size of a
 261  * particular instruction.  It's important to get the size right as
 262  * that tells us where the next instruction to check is.  Any illegal
 263  * instruction detected will be given a size of zero, which is a
 264  * signal to abort the rest of the buffer.
 265  */
 266 static int validate_cmd(int cmd)
 267 {
 268         switch (((cmd >> 29) & 0x7)) {
 269         case 0x0:
 270                 switch ((cmd >> 23) & 0x3f) {
 271                 case 0x0:
 272                         return 1;       /* MI_NOOP */
 273                 case 0x4:
 274                         return 1;       /* MI_FLUSH */
 275                 default:
 276                         return 0;       /* disallow everything else */
 277                 }
 278                 break;
 279         case 0x1:
 280                 return 0;       /* reserved */
 281         case 0x2:
 282                 return (cmd & 0xff) + 2;        /* 2d commands */
 283         case 0x3:
 284                 if (((cmd >> 24) & 0x1f) <= 0x18)
 285                         return 1;
 286
 287                 switch ((cmd >> 24) & 0x1f) {
 288                 case 0x1c:
 289                         return 1;
 290                 case 0x1d:
 291                         switch ((cmd >> 16) & 0xff) {
 292                         case 0x3:
 293                                 return (cmd & 0x1f) + 2;
 294                         case 0x4:
 295                                 return (cmd & 0xf) + 2;
 296                         default:
 297                                 return (cmd & 0xffff) + 2;
 298                         }
 299                 case 0x1e:
 300                         if (cmd & (1 << 23))
 301                                 return (cmd & 0xffff) + 1;
 302                         else
 303                                 return 1;
 304                 case 0x1f:
 305                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 306                                 return (cmd & 0x1ffff) + 2;
 307                         else if (cmd & (1 << 17))       /* indirect random */
 308                                 if ((cmd & 0xffff) == 0)
 309                                         return 0;       /* unknown length, too hard */
 310                                 else
 311                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 312                         else
 313                                 return 2;       /* indirect sequential */
 314                 default:
 315                         return 0;
 316                 }
 317         default:
 318                 return 0;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 325 {
 326         drm_i915_private_t *dev_priv = dev->dev_private;
 327         int i, ret;
 328
 329         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 330                 return -EINVAL;
 331
 332         for (i = 0; i < dwords;) {
 333                 int sz = validate_cmd(buffer[i]);
 334                 if (sz == 0 || i + sz > dwords)
 335                         return -EINVAL;
 336                 i += sz;
 337         }
 338
 339         ret = BEGIN_LP_RING((dwords+1)&~1);
 340         if (ret)
 341                 return ret;
 342
 343         for (i = 0; i < dwords; i++)
 344                 OUT_RING(buffer[i]);
 345         if (dwords & 1)
 346                 OUT_RING(0);
 347
 348         ADVANCE_LP_RING();
 349
 350         return 0;
 351 }
 352
 353 int
 354 i915_emit_box(struct drm_device *dev,
 355               struct drm_clip_rect *box,
 356               int DR1, int DR4)
 357 {
 358         struct drm_i915_private *dev_priv = dev->dev_private;
 359         int ret;
 360
 361         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 362             box->y2 <= 0 || box->x2 <= 0) {
 363                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 364                           box->x1, box->y1, box->x2, box->y2);
 365                 return -EINVAL;
 366         }
 367
 368         if (INTEL_INFO(dev)->gen >= 4) {
 369                 ret = BEGIN_LP_RING(4);
 370                 if (ret)
 371                         return ret;
 372
 373                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 374                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 375                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 376                 OUT_RING(DR4);
 377         } else {
 378                 ret = BEGIN_LP_RING(6);
 379                 if (ret)
 380                         return ret;
 381
 382                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 383                 OUT_RING(DR1);
 384                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 385                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 386                 OUT_RING(DR4);
 387                 OUT_RING(0);
 388         }
 389         ADVANCE_LP_RING();
 390
 391         return 0;
 392 }
 393
 394 /* XXX: Emitting the counter should really be moved to part of the IRQ
 395  * emit. For now, do it in both places:
 396  */
 397
 398 static void i915_emit_breadcrumb(struct drm_device *dev)
 399 {
 400         drm_i915_private_t *dev_priv = dev->dev_private;
 401         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 402
 403         dev_priv->counter++;
 404         if (dev_priv->counter > 0x7FFFFFFFUL)
 405                 dev_priv->counter = 0;
 406         if (master_priv->sarea_priv)
 407                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 408
 409         if (BEGIN_LP_RING(4) == 0) {
 410                 OUT_RING(MI_STORE_DWORD_INDEX);
 411                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 412                 OUT_RING(dev_priv->counter);
 413                 OUT_RING(0);
 414                 ADVANCE_LP_RING();
 415         }
 416 }
 417
 418 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 419                                    drm_i915_cmdbuffer_t *cmd,
 420                                    struct drm_clip_rect *cliprects,
 421                                    void *cmdbuf)
 422 {
 423         int nbox = cmd->num_cliprects;
 424         int i = 0, count, ret;
 425
 426         if (cmd->sz & 0x3) {
 427                 DRM_ERROR("alignment");
 428                 return -EINVAL;
 429         }
 430
 431         i915_kernel_lost_context(dev);
 432
 433         count = nbox ? nbox : 1;
 434
 435         for (i = 0; i < count; i++) {
 436                 if (i < nbox) {
 437                         ret = i915_emit_box(dev, &cliprects[i],
 438                                             cmd->DR1, cmd->DR4);
 439                         if (ret)
 440                                 return ret;
 441                 }
 442
 443                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 444                 if (ret)
 445                         return ret;
 446         }
 447
 448         i915_emit_breadcrumb(dev);
 449         return 0;
 450 }
 451
 452 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 453                                      drm_i915_batchbuffer_t * batch,
 454                                      struct drm_clip_rect *cliprects)
 455 {
 456         struct drm_i915_private *dev_priv = dev->dev_private;
 457         int nbox = batch->num_cliprects;
 458         int i, count, ret;
 459
 460         if ((batch->start | batch->used) & 0x7) {
 461                 DRM_ERROR("alignment");
 462                 return -EINVAL;
 463         }
 464
 465         i915_kernel_lost_context(dev);
 466
 467         count = nbox ? nbox : 1;
 468         for (i = 0; i < count; i++) {
 469                 if (i < nbox) {
 470                         ret = i915_emit_box(dev, &cliprects[i],
 471                                             batch->DR1, batch->DR4);
 472                         if (ret)
 473                                 return ret;
 474                 }
 475
 476                 if (!IS_I830(dev) && !IS_845G(dev)) {
 477                         ret = BEGIN_LP_RING(2);
 478                         if (ret)
 479                                 return ret;
 480
 481                         if (INTEL_INFO(dev)->gen >= 4) {
 482                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 483                                 OUT_RING(batch->start);
 484                         } else {
 485                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 486                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 487                         }
 488                 } else {
 489                         ret = BEGIN_LP_RING(4);
 490                         if (ret)
 491                                 return ret;
 492
 493                         OUT_RING(MI_BATCH_BUFFER);
 494                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 495                         OUT_RING(batch->start + batch->used - 4);
 496                         OUT_RING(0);
 497                 }
 498                 ADVANCE_LP_RING();
 499         }
 500
 501
 502         if (IS_G4X(dev) || IS_GEN5(dev)) {
 503                 if (BEGIN_LP_RING(2) == 0) {
 504                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 505                         OUT_RING(MI_NOOP);
 506                         ADVANCE_LP_RING();
 507                 }
 508         }
 509
 510         i915_emit_breadcrumb(dev);
 511         return 0;
 512 }
 513
 514 static int i915_dispatch_flip(struct drm_device * dev)
 515 {
 516         drm_i915_private_t *dev_priv = dev->dev_private;
 517         struct drm_i915_master_private *master_priv =
 518                 dev->primary->master->driver_priv;
 519         int ret;
 520
 521         if (!master_priv->sarea_priv)
 522                 return -EINVAL;
 523
 524         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 525                           __func__,
 526                          dev_priv->current_page,
 527                          master_priv->sarea_priv->pf_current_page);
 528
 529         i915_kernel_lost_context(dev);
 530
 531         ret = BEGIN_LP_RING(10);
 532         if (ret)
 533                 return ret;
 534
 535         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 536         OUT_RING(0);
 537
 538         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 539         OUT_RING(0);
 540         if (dev_priv->current_page == 0) {
 541                 OUT_RING(dev_priv->back_offset);
 542                 dev_priv->current_page = 1;
 543         } else {
 544                 OUT_RING(dev_priv->front_offset);
 545                 dev_priv->current_page = 0;
 546         }
 547         OUT_RING(0);
 548
 549         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 550         OUT_RING(0);
 551
 552         ADVANCE_LP_RING();
 553
 554         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 555
 556         if (BEGIN_LP_RING(4) == 0) {
 557                 OUT_RING(MI_STORE_DWORD_INDEX);
 558                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 559                 OUT_RING(dev_priv->counter);
 560                 OUT_RING(0);
 561                 ADVANCE_LP_RING();
 562         }
 563
 564         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 565         return 0;
 566 }
 567
 568 static int i915_quiescent(struct drm_device *dev)
 569 {
 570         struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
 571
 572         i915_kernel_lost_context(dev);
 573         return intel_wait_ring_idle(ring);
 574 }
 575
 576 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 577                             struct drm_file *file_priv)
 578 {
 579         int ret;
 580
 581         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 582
 583         mutex_lock(&dev->struct_mutex);
 584         ret = i915_quiescent(dev);
 585         mutex_unlock(&dev->struct_mutex);
 586
 587         return ret;
 588 }
 589
 590 static int i915_batchbuffer(struct drm_device *dev, void *data,
 591                             struct drm_file *file_priv)
 592 {
 593         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 594         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 595         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 596             master_priv->sarea_priv;
 597         drm_i915_batchbuffer_t *batch = data;
 598         int ret;
 599         struct drm_clip_rect *cliprects = NULL;
 600
 601         if (!dev_priv->allow_batchbuffer) {
 602                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 603                 return -EINVAL;
 604         }
 605
 606         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 607                         batch->start, batch->used, batch->num_cliprects);
 608
 609         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 610
 611         if (batch->num_cliprects < 0)
 612                 return -EINVAL;
 613
 614         if (batch->num_cliprects) {
 615                 cliprects = kcalloc(batch->num_cliprects,
 616                                     sizeof(struct drm_clip_rect),
 617                                     GFP_KERNEL);
 618                 if (cliprects == NULL)
 619                         return -ENOMEM;
 620
 621                 ret = copy_from_user(cliprects, batch->cliprects,
 622                                      batch->num_cliprects *
 623                                      sizeof(struct drm_clip_rect));
 624                 if (ret != 0) {
 625                         ret = -EFAULT;
 626                         goto fail_free;
 627                 }
 628         }
 629
 630         mutex_lock(&dev->struct_mutex);
 631         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 632         mutex_unlock(&dev->struct_mutex);
 633
 634         if (sarea_priv)
 635                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 636
 637 fail_free:
 638         kfree(cliprects);
 639
 640         return ret;
 641 }
 642
 643 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 644                           struct drm_file *file_priv)
 645 {
 646         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 647         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 648         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 649             master_priv->sarea_priv;
 650         drm_i915_cmdbuffer_t *cmdbuf = data;
 651         struct drm_clip_rect *cliprects = NULL;
 652         void *batch_data;
 653         int ret;
 654
 655         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 656                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 657
 658         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 659
 660         if (cmdbuf->num_cliprects < 0)
 661                 return -EINVAL;
 662
 663         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 664         if (batch_data == NULL)
 665                 return -ENOMEM;
 666
 667         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 668         if (ret != 0) {
 669                 ret = -EFAULT;
 670                 goto fail_batch_free;
 671         }
 672
 673         if (cmdbuf->num_cliprects) {
 674                 cliprects = kcalloc(cmdbuf->num_cliprects,
 675                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 676                 if (cliprects == NULL) {
 677                         ret = -ENOMEM;
 678                         goto fail_batch_free;
 679                 }
 680
 681                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 682                                      cmdbuf->num_cliprects *
 683                                      sizeof(struct drm_clip_rect));
 684                 if (ret != 0) {
 685                         ret = -EFAULT;
 686                         goto fail_clip_free;
 687                 }
 688         }
 689
 690         mutex_lock(&dev->struct_mutex);
 691         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 692         mutex_unlock(&dev->struct_mutex);
 693         if (ret) {
 694                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 695                 goto fail_clip_free;
 696         }
 697
 698         if (sarea_priv)
 699                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 700
 701 fail_clip_free:
 702         kfree(cliprects);
 703 fail_batch_free:
 704         kfree(batch_data);
 705
 706         return ret;
 707 }
 708
 709 static int i915_flip_bufs(struct drm_device *dev, void *data,
 710                           struct drm_file *file_priv)
 711 {
 712         int ret;
 713
 714         DRM_DEBUG_DRIVER("%s\n", __func__);
 715
 716         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 717
 718         mutex_lock(&dev->struct_mutex);
 719         ret = i915_dispatch_flip(dev);
 720         mutex_unlock(&dev->struct_mutex);
 721
 722         return ret;
 723 }
 724
 725 static int i915_getparam(struct drm_device *dev, void *data,
 726                          struct drm_file *file_priv)
 727 {
 728         drm_i915_private_t *dev_priv = dev->dev_private;
 729         drm_i915_getparam_t *param = data;
 730         int value;
 731
 732         if (!dev_priv) {
 733                 DRM_ERROR("called with no initialization\n");
 734                 return -EINVAL;
 735         }
 736
 737         switch (param->param) {
 738         case I915_PARAM_IRQ_ACTIVE:
 739                 value = dev->pdev->irq ? 1 : 0;
 740                 break;
 741         case I915_PARAM_ALLOW_BATCHBUFFER:
 742                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 743                 break;
 744         case I915_PARAM_LAST_DISPATCH:
 745                 value = READ_BREADCRUMB(dev_priv);
 746                 break;
 747         case I915_PARAM_CHIPSET_ID:
 748                 value = dev->pci_device;
 749                 break;
 750         case I915_PARAM_HAS_GEM:
 751                 value = dev_priv->has_gem;
 752                 break;
 753         case I915_PARAM_NUM_FENCES_AVAIL:
 754                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 755                 break;
 756         case I915_PARAM_HAS_OVERLAY:
 757                 value = dev_priv->overlay ? 1 : 0;
 758                 break;
 759         case I915_PARAM_HAS_PAGEFLIPPING:
 760                 value = 1;
 761                 break;
 762         case I915_PARAM_HAS_EXECBUF2:
 763                 /* depends on GEM */
 764                 value = dev_priv->has_gem;
 765                 break;
 766         case I915_PARAM_HAS_BSD:
 767                 value = HAS_BSD(dev);
 768                 break;
 769         case I915_PARAM_HAS_BLT:
 770                 value = HAS_BLT(dev);
 771                 break;
 772         case I915_PARAM_HAS_RELAXED_FENCING:
 773                 value = 1;
 774                 break;
 775         case I915_PARAM_HAS_COHERENT_RINGS:
 776                 value = 1;
 777                 break;
 778         case I915_PARAM_HAS_EXEC_CONSTANTS:
 779                 value = INTEL_INFO(dev)->gen >= 4;
 780                 break;
 781         case I915_PARAM_HAS_RELAXED_DELTA:
 782                 value = 1;
 783                 break;
 784         case I915_PARAM_HAS_GEN7_SOL_RESET:
 785                 value = 1;
 786                 break;
 787         case I915_PARAM_HAS_LLC:
 788                 value = HAS_LLC(dev);
 789                 break;
 790         default:
 791                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 792                                  param->param);
 793                 return -EINVAL;
 794         }
 795
 796         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 797                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 798                 return -EFAULT;
 799         }
 800
 801         return 0;
 802 }
 803
 804 static int i915_setparam(struct drm_device *dev, void *data,
 805                          struct drm_file *file_priv)
 806 {
 807         drm_i915_private_t *dev_priv = dev->dev_private;
 808         drm_i915_setparam_t *param = data;
 809
 810         if (!dev_priv) {
 811                 DRM_ERROR("called with no initialization\n");
 812                 return -EINVAL;
 813         }
 814
 815         switch (param->param) {
 816         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 817                 break;
 818         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 819                 dev_priv->tex_lru_log_granularity = param->value;
 820                 break;
 821         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 822                 dev_priv->allow_batchbuffer = param->value;
 823                 break;
 824         case I915_SETPARAM_NUM_USED_FENCES:
 825                 if (param->value > dev_priv->num_fence_regs ||
 826                     param->value < 0)
 827                         return -EINVAL;
 828                 /* Userspace can use first N regs */
 829                 dev_priv->fence_reg_start = param->value;
 830                 break;
 831         default:
 832                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 833                                         param->param);
 834                 return -EINVAL;
 835         }
 836
 837         return 0;
 838 }
 839
 840 static int i915_set_status_page(struct drm_device *dev, void *data,
 841                                 struct drm_file *file_priv)
 842 {
 843         drm_i915_private_t *dev_priv = dev->dev_private;
 844         drm_i915_hws_addr_t *hws = data;
 845         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 846
 847         if (!I915_NEED_GFX_HWS(dev))
 848                 return -EINVAL;
 849
 850         if (!dev_priv) {
 851                 DRM_ERROR("called with no initialization\n");
 852                 return -EINVAL;
 853         }
 854
 855         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 856                 WARN(1, "tried to set status page when mode setting active\n");
 857                 return 0;
 858         }
 859
 860         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 861
 862         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
 863
 864         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 865         dev_priv->hws_map.size = 4*1024;
 866         dev_priv->hws_map.type = 0;
 867         dev_priv->hws_map.flags = 0;
 868         dev_priv->hws_map.mtrr = 0;
 869
 870         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 871         if (dev_priv->hws_map.handle == NULL) {
 872                 i915_dma_cleanup(dev);
 873                 ring->status_page.gfx_addr = 0;
 874                 DRM_ERROR("can not ioremap virtual address for"
 875                                 " G33 hw status page\n");
 876                 return -ENOMEM;
 877         }
 878         ring->status_page.page_addr =
 879                 (void __force __iomem *)dev_priv->hws_map.handle;
 880         memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
 881         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 882
 883         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 884                          ring->status_page.gfx_addr);
 885         DRM_DEBUG_DRIVER("load hws at %p\n",
 886                          ring->status_page.page_addr);
 887         return 0;
 888 }
 889
 890 static int i915_get_bridge_dev(struct drm_device *dev)
 891 {
 892         struct drm_i915_private *dev_priv = dev->dev_private;
 893
 894         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 895         if (!dev_priv->bridge_dev) {
 896                 DRM_ERROR("bridge device not found\n");
 897                 return -1;
 898         }
 899         return 0;
 900 }
 901
 902 #define MCHBAR_I915 0x44
 903 #define MCHBAR_I965 0x48
 904 #define MCHBAR_SIZE (4*4096)
 905
 906 #define DEVEN_REG 0x54
 907 #define   DEVEN_MCHBAR_EN (1 << 28)
 908
 909 /* Allocate space for the MCH regs if needed, return nonzero on error */
 910 static int
 911 intel_alloc_mchbar_resource(struct drm_device *dev)
 912 {
 913         drm_i915_private_t *dev_priv = dev->dev_private;
 914         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 915         u32 temp_lo, temp_hi = 0;
 916         u64 mchbar_addr;
 917         int ret;
 918
 919         if (INTEL_INFO(dev)->gen >= 4)
 920                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 921         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 922         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 923
 924         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 925 #ifdef CONFIG_PNP
 926         if (mchbar_addr &&
 927             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 928                 return 0;
 929 #endif
 930
 931         /* Get some space for it */
 932         dev_priv->mch_res.name = "i915 MCHBAR";
 933         dev_priv->mch_res.flags = IORESOURCE_MEM;
 934         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 935                                      &dev_priv->mch_res,
 936                                      MCHBAR_SIZE, MCHBAR_SIZE,
 937                                      PCIBIOS_MIN_MEM,
 938                                      0, pcibios_align_resource,
 939                                      dev_priv->bridge_dev);
 940         if (ret) {
 941                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 942                 dev_priv->mch_res.start = 0;
 943                 return ret;
 944         }
 945
 946         if (INTEL_INFO(dev)->gen >= 4)
 947                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 948                                        upper_32_bits(dev_priv->mch_res.start));
 949
 950         pci_write_config_dword(dev_priv->bridge_dev, reg,
 951                                lower_32_bits(dev_priv->mch_res.start));
 952         return 0;
 953 }
 954
 955 /* Setup MCHBAR if possible, return true if we should disable it again */
 956 static void
 957 intel_setup_mchbar(struct drm_device *dev)
 958 {
 959         drm_i915_private_t *dev_priv = dev->dev_private;
 960         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 961         u32 temp;
 962         bool enabled;
 963
 964         dev_priv->mchbar_need_disable = false;
 965
 966         if (IS_I915G(dev) || IS_I915GM(dev)) {
 967                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 968                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 969         } else {
 970                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 971                 enabled = temp & 1;
 972         }
 973
 974         /* If it's already enabled, don't have to do anything */
 975         if (enabled)
 976                 return;
 977
 978         if (intel_alloc_mchbar_resource(dev))
 979                 return;
 980
 981         dev_priv->mchbar_need_disable = true;
 982
 983         /* Space is allocated or reserved, so enable it. */
 984         if (IS_I915G(dev) || IS_I915GM(dev)) {
 985                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 986                                        temp | DEVEN_MCHBAR_EN);
 987         } else {
 988                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 989                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 990         }
 991 }
 992
 993 static void
 994 intel_teardown_mchbar(struct drm_device *dev)
 995 {
 996         drm_i915_private_t *dev_priv = dev->dev_private;
 997         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 998         u32 temp;
 999
1000         if (dev_priv->mchbar_need_disable) {
1001                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1002                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1003                         temp &= ~DEVEN_MCHBAR_EN;
1004                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1005                 } else {
1006                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1007                         temp &= ~1;
1008                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1009                 }
1010         }
1011
1012         if (dev_priv->mch_res.start)
1013                 release_resource(&dev_priv->mch_res);
1014 }
1015
1016 #define PTE_ADDRESS_MASK                0xfffff000
1017 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1018 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1019 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1020 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1021 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1022 #define PTE_VALID                       (1 << 0)
1023
1024 /**
1025  * i915_stolen_to_phys - take an offset into stolen memory and turn it into
1026  *                       a physical one
1027  * @dev: drm device
1028  * @offset: address to translate
1029  *
1030  * Some chip functions require allocations from stolen space and need the
1031  * physical address of the memory in question.
1032  */
1033 static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
1034 {
1035         struct drm_i915_private *dev_priv = dev->dev_private;
1036         struct pci_dev *pdev = dev_priv->bridge_dev;
1037         u32 base;
1038
1039 #if 0
1040         /* On the machines I have tested the Graphics Base of Stolen Memory
1041          * is unreliable, so compute the base by subtracting the stolen memory
1042          * from the Top of Low Usable DRAM which is where the BIOS places
1043          * the graphics stolen memory.
1044          */
1045         if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1046                 /* top 32bits are reserved = 0 */
1047                 pci_read_config_dword(pdev, 0xA4, &base);
1048         } else {
1049                 /* XXX presume 8xx is the same as i915 */
1050                 pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base);
1051         }
1052 #else
1053         if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1054                 u16 val;
1055                 pci_read_config_word(pdev, 0xb0, &val);
1056                 base = val >> 4 << 20;
1057         } else {
1058                 u8 val;
1059                 pci_read_config_byte(pdev, 0x9c, &val);
1060                 base = val >> 3 << 27;
1061         }
1062         base -= dev_priv->mm.gtt->stolen_size;
1063 #endif
1064
1065         return base + offset;
1066 }
1067
1068 static void i915_warn_stolen(struct drm_device *dev)
1069 {
1070         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1071         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1072 }
1073
1074 static void i915_setup_compression(struct drm_device *dev, int size)
1075 {
1076         struct drm_i915_private *dev_priv = dev->dev_private;
1077         struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1078         unsigned long cfb_base;
1079         unsigned long ll_base = 0;
1080
1081         /* Just in case the BIOS is doing something questionable. */
1082         intel_disable_fbc(dev);
1083
1084         compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0);
1085         if (compressed_fb)
1086                 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1087         if (!compressed_fb)
1088                 goto err;
1089
1090         cfb_base = i915_stolen_to_phys(dev, compressed_fb->start);
1091         if (!cfb_base)
1092                 goto err_fb;
1093
1094         if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) {
1095                 compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen,
1096                                                     4096, 4096, 0);
1097                 if (compressed_llb)
1098                         compressed_llb = drm_mm_get_block(compressed_llb,
1099                                                           4096, 4096);
1100                 if (!compressed_llb)
1101                         goto err_fb;
1102
1103                 ll_base = i915_stolen_to_phys(dev, compressed_llb->start);
1104                 if (!ll_base)
1105                         goto err_llb;
1106         }
1107
1108         dev_priv->cfb_size = size;
1109
1110         dev_priv->compressed_fb = compressed_fb;
1111         if (HAS_PCH_SPLIT(dev))
1112                 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1113         else if (IS_GM45(dev)) {
1114                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1115         } else {
1116                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1117                 I915_WRITE(FBC_LL_BASE, ll_base);
1118                 dev_priv->compressed_llb = compressed_llb;
1119         }
1120
1121         DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n",
1122                       cfb_base, ll_base, size >> 20);
1123         return;
1124
1125 err_llb:
1126         drm_mm_put_block(compressed_llb);
1127 err_fb:
1128         drm_mm_put_block(compressed_fb);
1129 err:
1130         dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1131         i915_warn_stolen(dev);
1132 }
1133
1134 static void i915_cleanup_compression(struct drm_device *dev)
1135 {
1136         struct drm_i915_private *dev_priv = dev->dev_private;
1137
1138         drm_mm_put_block(dev_priv->compressed_fb);
1139         if (dev_priv->compressed_llb)
1140                 drm_mm_put_block(dev_priv->compressed_llb);
1141 }
1142
1143 /* true = enable decode, false = disable decoder */
1144 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1145 {
1146         struct drm_device *dev = cookie;
1147
1148         intel_modeset_vga_set_state(dev, state);
1149         if (state)
1150                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1151                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1152         else
1153                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1154 }
1155
1156 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1157 {
1158         struct drm_device *dev = pci_get_drvdata(pdev);
1159         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1160         if (state == VGA_SWITCHEROO_ON) {
1161                 printk(KERN_INFO "i915: switched on\n");
1162                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1163                 /* i915 resume handler doesn't set to D0 */
1164                 pci_set_power_state(dev->pdev, PCI_D0);
1165                 i915_resume(dev);
1166                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1167         } else {
1168                 printk(KERN_ERR "i915: switched off\n");
1169                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1170                 i915_suspend(dev, pmm);
1171                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1172         }
1173 }
1174
1175 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1176 {
1177         struct drm_device *dev = pci_get_drvdata(pdev);
1178         bool can_switch;
1179
1180         spin_lock(&dev->count_lock);
1181         can_switch = (dev->open_count == 0);
1182         spin_unlock(&dev->count_lock);
1183         return can_switch;
1184 }
1185
1186 static bool
1187 intel_enable_ppgtt(struct drm_device *dev)
1188 {
1189         if (i915_enable_ppgtt >= 0)
1190                 return i915_enable_ppgtt;
1191
1192 #ifdef CONFIG_INTEL_IOMMU
1193         /* Disable ppgtt on SNB if VT-d is on. */
1194         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
1195                 return false;
1196 #endif
1197
1198         return true;
1199 }
1200
1201 static int i915_load_gem_init(struct drm_device *dev)
1202 {
1203         struct drm_i915_private *dev_priv = dev->dev_private;
1204         unsigned long prealloc_size, gtt_size, mappable_size;
1205         int ret;
1206
1207         prealloc_size = dev_priv->mm.gtt->stolen_size;
1208         gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
1209         mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1210
1211         /* Basic memrange allocator for stolen space */
1212         drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
1213
1214         mutex_lock(&dev->struct_mutex);
1215         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
1216                 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
1217                  * aperture accordingly when using aliasing ppgtt. */
1218                 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
1219                 /* For paranoia keep the guard page in between. */
1220                 gtt_size -= PAGE_SIZE;
1221
1222                 i915_gem_do_init(dev, 0, mappable_size, gtt_size);
1223
1224                 ret = i915_gem_init_aliasing_ppgtt(dev);
1225                 if (ret) {
1226                         mutex_unlock(&dev->struct_mutex);
1227                         return ret;
1228                 }
1229         } else {
1230                 /* Let GEM Manage all of the aperture.
1231                  *
1232                  * However, leave one page at the end still bound to the scratch
1233                  * page.  There are a number of places where the hardware
1234                  * apparently prefetches past the end of the object, and we've
1235                  * seen multiple hangs with the GPU head pointer stuck in a
1236                  * batchbuffer bound at the last page of the aperture.  One page
1237                  * should be enough to keep any prefetching inside of the
1238                  * aperture.
1239                  */
1240                 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
1241         }
1242
1243         ret = i915_gem_init_hw(dev);
1244         mutex_unlock(&dev->struct_mutex);
1245         if (ret) {
1246                 i915_gem_cleanup_aliasing_ppgtt(dev);
1247                 return ret;
1248         }
1249
1250         /* Try to set up FBC with a reasonable compressed buffer size */
1251         if (I915_HAS_FBC(dev) && i915_powersave) {
1252                 int cfb_size;
1253
1254                 /* Leave 1M for line length buffer & misc. */
1255
1256                 /* Try to get a 32M buffer... */
1257                 if (prealloc_size > (36*1024*1024))
1258                         cfb_size = 32*1024*1024;
1259                 else /* fall back to 7/8 of the stolen space */
1260                         cfb_size = prealloc_size * 7 / 8;
1261                 i915_setup_compression(dev, cfb_size);
1262         }
1263
1264         /* Allow hardware batchbuffers unless told otherwise. */
1265         dev_priv->allow_batchbuffer = 1;
1266         return 0;
1267 }
1268
1269 static int i915_load_modeset_init(struct drm_device *dev)
1270 {
1271         struct drm_i915_private *dev_priv = dev->dev_private;
1272         int ret;
1273
1274         ret = intel_parse_bios(dev);
1275         if (ret)
1276                 DRM_INFO("failed to find VBIOS tables\n");
1277
1278         /* If we have > 1 VGA cards, then we need to arbitrate access
1279          * to the common VGA resources.
1280          *
1281          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1282          * then we do not take part in VGA arbitration and the
1283          * vga_client_register() fails with -ENODEV.
1284          */
1285         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1286         if (ret && ret != -ENODEV)
1287                 goto out;
1288
1289         intel_register_dsm_handler();
1290
1291         ret = vga_switcheroo_register_client(dev->pdev,
1292                                              i915_switcheroo_set_state,
1293                                              NULL,
1294                                              i915_switcheroo_can_switch);
1295         if (ret)
1296                 goto cleanup_vga_client;
1297
1298         /* IIR "flip pending" bit means done if this bit is set */
1299         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1300                 dev_priv->flip_pending_is_done = true;
1301
1302         intel_modeset_init(dev);
1303
1304         ret = i915_load_gem_init(dev);
1305         if (ret)
1306                 goto cleanup_vga_switcheroo;
1307
1308         intel_modeset_gem_init(dev);
1309
1310         ret = drm_irq_install(dev);
1311         if (ret)
1312                 goto cleanup_gem;
1313
1314         /* Always safe in the mode setting case. */
1315         /* FIXME: do pre/post-mode set stuff in core KMS code */
1316         dev->vblank_disable_allowed = 1;
1317
1318         ret = intel_fbdev_init(dev);
1319         if (ret)
1320                 goto cleanup_irq;
1321
1322         drm_kms_helper_poll_init(dev);
1323
1324         /* We're off and running w/KMS */
1325         dev_priv->mm.suspended = 0;
1326
1327         return 0;
1328
1329 cleanup_irq:
1330         drm_irq_uninstall(dev);
1331 cleanup_gem:
1332         mutex_lock(&dev->struct_mutex);
1333         i915_gem_cleanup_ringbuffer(dev);
1334         mutex_unlock(&dev->struct_mutex);
1335         i915_gem_cleanup_aliasing_ppgtt(dev);
1336 cleanup_vga_switcheroo:
1337         vga_switcheroo_unregister_client(dev->pdev);
1338 cleanup_vga_client:
1339         vga_client_register(dev->pdev, NULL, NULL, NULL);
1340 out:
1341         return ret;
1342 }
1343
1344 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1345 {
1346         struct drm_i915_master_private *master_priv;
1347
1348         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1349         if (!master_priv)
1350                 return -ENOMEM;
1351
1352         master->driver_priv = master_priv;
1353         return 0;
1354 }
1355
1356 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1357 {
1358         struct drm_i915_master_private *master_priv = master->driver_priv;
1359
1360         if (!master_priv)
1361                 return;
1362
1363         kfree(master_priv);
1364
1365         master->driver_priv = NULL;
1366 }
1367
1368 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1369 {
1370         drm_i915_private_t *dev_priv = dev->dev_private;
1371         u32 tmp;
1372
1373         tmp = I915_READ(CLKCFG);
1374
1375         switch (tmp & CLKCFG_FSB_MASK) {
1376         case CLKCFG_FSB_533:
1377                 dev_priv->fsb_freq = 533; /* 133*4 */
1378                 break;
1379         case CLKCFG_FSB_800:
1380                 dev_priv->fsb_freq = 800; /* 200*4 */
1381                 break;
1382         case CLKCFG_FSB_667:
1383                 dev_priv->fsb_freq =  667; /* 167*4 */
1384                 break;
1385         case CLKCFG_FSB_400:
1386                 dev_priv->fsb_freq = 400; /* 100*4 */
1387                 break;
1388         }
1389
1390         switch (tmp & CLKCFG_MEM_MASK) {
1391         case CLKCFG_MEM_533:
1392                 dev_priv->mem_freq = 533;
1393                 break;
1394         case CLKCFG_MEM_667:
1395                 dev_priv->mem_freq = 667;
1396                 break;
1397         case CLKCFG_MEM_800:
1398                 dev_priv->mem_freq = 800;
1399                 break;
1400         }
1401
1402         /* detect pineview DDR3 setting */
1403         tmp = I915_READ(CSHRDDR3CTL);
1404         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1405 }
1406
1407 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1408 {
1409         drm_i915_private_t *dev_priv = dev->dev_private;
1410         u16 ddrpll, csipll;
1411
1412         ddrpll = I915_READ16(DDRMPLL1);
1413         csipll = I915_READ16(CSIPLL0);
1414
1415         switch (ddrpll & 0xff) {
1416         case 0xc:
1417                 dev_priv->mem_freq = 800;
1418                 break;
1419         case 0x10:
1420                 dev_priv->mem_freq = 1066;
1421                 break;
1422         case 0x14:
1423                 dev_priv->mem_freq = 1333;
1424                 break;
1425         case 0x18:
1426                 dev_priv->mem_freq = 1600;
1427                 break;
1428         default:
1429                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1430                                  ddrpll & 0xff);
1431                 dev_priv->mem_freq = 0;
1432                 break;
1433         }
1434
1435         dev_priv->r_t = dev_priv->mem_freq;
1436
1437         switch (csipll & 0x3ff) {
1438         case 0x00c:
1439                 dev_priv->fsb_freq = 3200;
1440                 break;
1441         case 0x00e:
1442                 dev_priv->fsb_freq = 3733;
1443                 break;
1444         case 0x010:
1445                 dev_priv->fsb_freq = 4266;
1446                 break;
1447         case 0x012:
1448                 dev_priv->fsb_freq = 4800;
1449                 break;
1450         case 0x014:
1451                 dev_priv->fsb_freq = 5333;
1452                 break;
1453         case 0x016:
1454                 dev_priv->fsb_freq = 5866;
1455                 break;
1456         case 0x018:
1457                 dev_priv->fsb_freq = 6400;
1458                 break;
1459         default:
1460                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1461                                  csipll & 0x3ff);
1462                 dev_priv->fsb_freq = 0;
1463                 break;
1464         }
1465
1466         if (dev_priv->fsb_freq == 3200) {
1467                 dev_priv->c_m = 0;
1468         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1469                 dev_priv->c_m = 1;
1470         } else {
1471                 dev_priv->c_m = 2;
1472         }
1473 }
1474
1475 static const struct cparams {
1476         u16 i;
1477         u16 t;
1478         u16 m;
1479         u16 c;
1480 } cparams[] = {
1481         { 1, 1333, 301, 28664 },
1482         { 1, 1066, 294, 24460 },
1483         { 1, 800, 294, 25192 },
1484         { 0, 1333, 276, 27605 },
1485         { 0, 1066, 276, 27605 },
1486         { 0, 800, 231, 23784 },
1487 };
1488
1489 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1490 {
1491         u64 total_count, diff, ret;
1492         u32 count1, count2, count3, m = 0, c = 0;
1493         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1494         int i;
1495
1496         diff1 = now - dev_priv->last_time1;
1497
1498         /* Prevent division-by-zero if we are asking too fast.
1499          * Also, we don't get interesting results if we are polling
1500          * faster than once in 10ms, so just return the saved value
1501          * in such cases.
1502          */
1503         if (diff1 <= 10)
1504                 return dev_priv->chipset_power;
1505
1506         count1 = I915_READ(DMIEC);
1507         count2 = I915_READ(DDREC);
1508         count3 = I915_READ(CSIEC);
1509
1510         total_count = count1 + count2 + count3;
1511
1512         /* FIXME: handle per-counter overflow */
1513         if (total_count < dev_priv->last_count1) {
1514                 diff = ~0UL - dev_priv->last_count1;
1515                 diff += total_count;
1516         } else {
1517                 diff = total_count - dev_priv->last_count1;
1518         }
1519
1520         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1521                 if (cparams[i].i == dev_priv->c_m &&
1522                     cparams[i].t == dev_priv->r_t) {
1523                         m = cparams[i].m;
1524                         c = cparams[i].c;
1525                         break;
1526                 }
1527         }
1528
1529         diff = div_u64(diff, diff1);
1530         ret = ((m * diff) + c);
1531         ret = div_u64(ret, 10);
1532
1533         dev_priv->last_count1 = total_count;
1534         dev_priv->last_time1 = now;
1535
1536         dev_priv->chipset_power = ret;
1537
1538         return ret;
1539 }
1540
1541 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1542 {
1543         unsigned long m, x, b;
1544         u32 tsfs;
1545
1546         tsfs = I915_READ(TSFS);
1547
1548         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1549         x = I915_READ8(TR1);
1550
1551         b = tsfs & TSFS_INTR_MASK;
1552
1553         return ((m * x) / 127) - b;
1554 }
1555
1556 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1557 {
1558         static const struct v_table {
1559                 u16 vd; /* in .1 mil */
1560                 u16 vm; /* in .1 mil */
1561         } v_table[] = {
1562                 { 0, 0, },
1563                 { 375, 0, },
1564                 { 500, 0, },
1565                 { 625, 0, },
1566                 { 750, 0, },
1567                 { 875, 0, },
1568                 { 1000, 0, },
1569                 { 1125, 0, },
1570                 { 4125, 3000, },
1571                 { 4125, 3000, },
1572                 { 4125, 3000, },
1573                 { 4125, 3000, },
1574                 { 4125, 3000, },
1575                 { 4125, 3000, },
1576                 { 4125, 3000, },
1577                 { 4125, 3000, },
1578                 { 4125, 3000, },
1579                 { 4125, 3000, },
1580                 { 4125, 3000, },
1581                 { 4125, 3000, },
1582                 { 4125, 3000, },
1583                 { 4125, 3000, },
1584                 { 4125, 3000, },
1585                 { 4125, 3000, },
1586                 { 4125, 3000, },
1587                 { 4125, 3000, },
1588                 { 4125, 3000, },
1589                 { 4125, 3000, },
1590                 { 4125, 3000, },
1591                 { 4125, 3000, },
1592                 { 4125, 3000, },
1593                 { 4125, 3000, },
1594                 { 4250, 3125, },
1595                 { 4375, 3250, },
1596                 { 4500, 3375, },
1597                 { 4625, 3500, },
1598                 { 4750, 3625, },
1599                 { 4875, 3750, },
1600                 { 5000, 3875, },
1601                 { 5125, 4000, },
1602                 { 5250, 4125, },
1603                 { 5375, 4250, },
1604                 { 5500, 4375, },
1605                 { 5625, 4500, },
1606                 { 5750, 4625, },
1607                 { 5875, 4750, },
1608                 { 6000, 4875, },
1609                 { 6125, 5000, },
1610                 { 6250, 5125, },
1611                 { 6375, 5250, },
1612                 { 6500, 5375, },
1613                 { 6625, 5500, },
1614                 { 6750, 5625, },
1615                 { 6875, 5750, },
1616                 { 7000, 5875, },
1617                 { 7125, 6000, },
1618                 { 7250, 6125, },
1619                 { 7375, 6250, },
1620                 { 7500, 6375, },
1621                 { 7625, 6500, },
1622                 { 7750, 6625, },
1623                 { 7875, 6750, },
1624                 { 8000, 6875, },
1625                 { 8125, 7000, },
1626                 { 8250, 7125, },
1627                 { 8375, 7250, },
1628                 { 8500, 7375, },
1629                 { 8625, 7500, },
1630                 { 8750, 7625, },
1631                 { 8875, 7750, },
1632                 { 9000, 7875, },
1633                 { 9125, 8000, },
1634                 { 9250, 8125, },
1635                 { 9375, 8250, },
1636                 { 9500, 8375, },
1637                 { 9625, 8500, },
1638                 { 9750, 8625, },
1639                 { 9875, 8750, },
1640                 { 10000, 8875, },
1641                 { 10125, 9000, },
1642                 { 10250, 9125, },
1643                 { 10375, 9250, },
1644                 { 10500, 9375, },
1645                 { 10625, 9500, },
1646                 { 10750, 9625, },
1647                 { 10875, 9750, },
1648                 { 11000, 9875, },
1649                 { 11125, 10000, },
1650                 { 11250, 10125, },
1651                 { 11375, 10250, },
1652                 { 11500, 10375, },
1653                 { 11625, 10500, },
1654                 { 11750, 10625, },
1655                 { 11875, 10750, },
1656                 { 12000, 10875, },
1657                 { 12125, 11000, },
1658                 { 12250, 11125, },
1659                 { 12375, 11250, },
1660                 { 12500, 11375, },
1661                 { 12625, 11500, },
1662                 { 12750, 11625, },
1663                 { 12875, 11750, },
1664                 { 13000, 11875, },
1665                 { 13125, 12000, },
1666                 { 13250, 12125, },
1667                 { 13375, 12250, },
1668                 { 13500, 12375, },
1669                 { 13625, 12500, },
1670                 { 13750, 12625, },
1671                 { 13875, 12750, },
1672                 { 14000, 12875, },
1673                 { 14125, 13000, },
1674                 { 14250, 13125, },
1675                 { 14375, 13250, },
1676                 { 14500, 13375, },
1677                 { 14625, 13500, },
1678                 { 14750, 13625, },
1679                 { 14875, 13750, },
1680                 { 15000, 13875, },
1681                 { 15125, 14000, },
1682                 { 15250, 14125, },
1683                 { 15375, 14250, },
1684                 { 15500, 14375, },
1685                 { 15625, 14500, },
1686                 { 15750, 14625, },
1687                 { 15875, 14750, },
1688                 { 16000, 14875, },
1689                 { 16125, 15000, },
1690         };
1691         if (dev_priv->info->is_mobile)
1692                 return v_table[pxvid].vm;
1693         else
1694                 return v_table[pxvid].vd;
1695 }
1696
1697 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1698 {
1699         struct timespec now, diff1;
1700         u64 diff;
1701         unsigned long diffms;
1702         u32 count;
1703
1704         if (dev_priv->info->gen != 5)
1705                 return;
1706
1707         getrawmonotonic(&now);
1708         diff1 = timespec_sub(now, dev_priv->last_time2);
1709
1710         /* Don't divide by 0 */
1711         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1712         if (!diffms)
1713                 return;
1714
1715         count = I915_READ(GFXEC);
1716
1717         if (count < dev_priv->last_count2) {
1718                 diff = ~0UL - dev_priv->last_count2;
1719                 diff += count;
1720         } else {
1721                 diff = count - dev_priv->last_count2;
1722         }
1723
1724         dev_priv->last_count2 = count;
1725         dev_priv->last_time2 = now;
1726
1727         /* More magic constants... */
1728         diff = diff * 1181;
1729         diff = div_u64(diff, diffms * 10);
1730         dev_priv->gfx_power = diff;
1731 }
1732
1733 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1734 {
1735         unsigned long t, corr, state1, corr2, state2;
1736         u32 pxvid, ext_v;
1737
1738         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1739         pxvid = (pxvid >> 24) & 0x7f;
1740         ext_v = pvid_to_extvid(dev_priv, pxvid);
1741
1742         state1 = ext_v;
1743
1744         t = i915_mch_val(dev_priv);
1745
1746         /* Revel in the empirically derived constants */
1747
1748         /* Correction factor in 1/100000 units */
1749         if (t > 80)
1750                 corr = ((t * 2349) + 135940);
1751         else if (t >= 50)
1752                 corr = ((t * 964) + 29317);
1753         else /* < 50 */
1754                 corr = ((t * 301) + 1004);
1755
1756         corr = corr * ((150142 * state1) / 10000 - 78642);
1757         corr /= 100000;
1758         corr2 = (corr * dev_priv->corr);
1759
1760         state2 = (corr2 * state1) / 10000;
1761         state2 /= 100; /* convert to mW */
1762
1763         i915_update_gfx_val(dev_priv);
1764
1765         return dev_priv->gfx_power + state2;
1766 }
1767
1768 /* Global for IPS driver to get at the current i915 device */
1769 static struct drm_i915_private *i915_mch_dev;
1770 /*
1771  * Lock protecting IPS related data structures
1772  *   - i915_mch_dev
1773  *   - dev_priv->max_delay
1774  *   - dev_priv->min_delay
1775  *   - dev_priv->fmax
1776  *   - dev_priv->gpu_busy
1777  */
1778 static DEFINE_SPINLOCK(mchdev_lock);
1779
1780 /**
1781  * i915_read_mch_val - return value for IPS use
1782  *
1783  * Calculate and return a value for the IPS driver to use when deciding whether
1784  * we have thermal and power headroom to increase CPU or GPU power budget.
1785  */
1786 unsigned long i915_read_mch_val(void)
1787 {
1788         struct drm_i915_private *dev_priv;
1789         unsigned long chipset_val, graphics_val, ret = 0;
1790
1791         spin_lock(&mchdev_lock);
1792         if (!i915_mch_dev)
1793                 goto out_unlock;
1794         dev_priv = i915_mch_dev;
1795
1796         chipset_val = i915_chipset_val(dev_priv);
1797         graphics_val = i915_gfx_val(dev_priv);
1798
1799         ret = chipset_val + graphics_val;
1800
1801 out_unlock:
1802         spin_unlock(&mchdev_lock);
1803
1804         return ret;
1805 }
1806 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1807
1808 /**
1809  * i915_gpu_raise - raise GPU frequency limit
1810  *
1811  * Raise the limit; IPS indicates we have thermal headroom.
1812  */
1813 bool i915_gpu_raise(void)
1814 {
1815         struct drm_i915_private *dev_priv;
1816         bool ret = true;
1817
1818         spin_lock(&mchdev_lock);
1819         if (!i915_mch_dev) {
1820                 ret = false;
1821                 goto out_unlock;
1822         }
1823         dev_priv = i915_mch_dev;
1824
1825         if (dev_priv->max_delay > dev_priv->fmax)
1826                 dev_priv->max_delay--;
1827
1828 out_unlock:
1829         spin_unlock(&mchdev_lock);
1830
1831         return ret;
1832 }
1833 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1834
1835 /**
1836  * i915_gpu_lower - lower GPU frequency limit
1837  *
1838  * IPS indicates we're close to a thermal limit, so throttle back the GPU
1839  * frequency maximum.
1840  */
1841 bool i915_gpu_lower(void)
1842 {
1843         struct drm_i915_private *dev_priv;
1844         bool ret = true;
1845
1846         spin_lock(&mchdev_lock);
1847         if (!i915_mch_dev) {
1848                 ret = false;
1849                 goto out_unlock;
1850         }
1851         dev_priv = i915_mch_dev;
1852
1853         if (dev_priv->max_delay < dev_priv->min_delay)
1854                 dev_priv->max_delay++;
1855
1856 out_unlock:
1857         spin_unlock(&mchdev_lock);
1858
1859         return ret;
1860 }
1861 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1862
1863 /**
1864  * i915_gpu_busy - indicate GPU business to IPS
1865  *
1866  * Tell the IPS driver whether or not the GPU is busy.
1867  */
1868 bool i915_gpu_busy(void)
1869 {
1870         struct drm_i915_private *dev_priv;
1871         bool ret = false;
1872
1873         spin_lock(&mchdev_lock);
1874         if (!i915_mch_dev)
1875                 goto out_unlock;
1876         dev_priv = i915_mch_dev;
1877
1878         ret = dev_priv->busy;
1879
1880 out_unlock:
1881         spin_unlock(&mchdev_lock);
1882
1883         return ret;
1884 }
1885 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1886
1887 /**
1888  * i915_gpu_turbo_disable - disable graphics turbo
1889  *
1890  * Disable graphics turbo by resetting the max frequency and setting the
1891  * current frequency to the default.
1892  */
1893 bool i915_gpu_turbo_disable(void)
1894 {
1895         struct drm_i915_private *dev_priv;
1896         bool ret = true;
1897
1898         spin_lock(&mchdev_lock);
1899         if (!i915_mch_dev) {
1900                 ret = false;
1901                 goto out_unlock;
1902         }
1903         dev_priv = i915_mch_dev;
1904
1905         dev_priv->max_delay = dev_priv->fstart;
1906
1907         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1908                 ret = false;
1909
1910 out_unlock:
1911         spin_unlock(&mchdev_lock);
1912
1913         return ret;
1914 }
1915 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1916
1917 /**
1918  * Tells the intel_ips driver that the i915 driver is now loaded, if
1919  * IPS got loaded first.
1920  *
1921  * This awkward dance is so that neither module has to depend on the
1922  * other in order for IPS to do the appropriate communication of
1923  * GPU turbo limits to i915.
1924  */
1925 static void
1926 ips_ping_for_i915_load(void)
1927 {
1928         void (*link)(void);
1929
1930         link = symbol_get(ips_link_to_i915_driver);
1931         if (link) {
1932                 link();
1933                 symbol_put(ips_link_to_i915_driver);
1934         }
1935 }
1936
1937 /**
1938  * i915_driver_load - setup chip and create an initial config
1939  * @dev: DRM device
1940  * @flags: startup flags
1941  *
1942  * The driver load routine has to do several things:
1943  *   - drive output discovery via intel_modeset_init()
1944  *   - initialize the memory manager
1945  *   - allocate initial config memory
1946  *   - setup the DRM framebuffer with the allocated memory
1947  */
1948 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1949 {
1950         struct drm_i915_private *dev_priv;
1951         int ret = 0, mmio_bar;
1952         uint32_t agp_size;
1953
1954         /* i915 has 4 more counters */
1955         dev->counters += 4;
1956         dev->types[6] = _DRM_STAT_IRQ;
1957         dev->types[7] = _DRM_STAT_PRIMARY;
1958         dev->types[8] = _DRM_STAT_SECONDARY;
1959         dev->types[9] = _DRM_STAT_DMA;
1960
1961         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1962         if (dev_priv == NULL)
1963                 return -ENOMEM;
1964
1965         dev->dev_private = (void *)dev_priv;
1966         dev_priv->dev = dev;
1967         dev_priv->info = (struct intel_device_info *) flags;
1968
1969         if (i915_get_bridge_dev(dev)) {
1970                 ret = -EIO;
1971                 goto free_priv;
1972         }
1973
1974         pci_set_master(dev->pdev);
1975
1976         /* overlay on gen2 is broken and can't address above 1G */
1977         if (IS_GEN2(dev))
1978                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1979
1980         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1981          * using 32bit addressing, overwriting memory if HWS is located
1982          * above 4GB.
1983          *
1984          * The documentation also mentions an issue with undefined
1985          * behaviour if any general state is accessed within a page above 4GB,
1986          * which also needs to be handled carefully.
1987          */
1988         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1989                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1990
1991         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1992         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
1993         if (!dev_priv->regs) {
1994                 DRM_ERROR("failed to map registers\n");
1995                 ret = -EIO;
1996                 goto put_bridge;
1997         }
1998
1999         dev_priv->mm.gtt = intel_gtt_get();
2000         if (!dev_priv->mm.gtt) {
2001                 DRM_ERROR("Failed to initialize GTT\n");
2002                 ret = -ENODEV;
2003                 goto out_rmmap;
2004         }
2005
2006         agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
2007
2008         dev_priv->mm.gtt_mapping =
2009                 io_mapping_create_wc(dev->agp->base, agp_size);
2010         if (dev_priv->mm.gtt_mapping == NULL) {
2011                 ret = -EIO;
2012                 goto out_rmmap;
2013         }
2014
2015         /* Set up a WC MTRR for non-PAT systems.  This is more common than
2016          * one would think, because the kernel disables PAT on first
2017          * generation Core chips because WC PAT gets overridden by a UC
2018          * MTRR if present.  Even if a UC MTRR isn't present.
2019          */
2020         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
2021                                          agp_size,
2022                                          MTRR_TYPE_WRCOMB, 1);
2023         if (dev_priv->mm.gtt_mtrr < 0) {
2024                 DRM_INFO("MTRR allocation failed.  Graphics "
2025                          "performance may suffer.\n");
2026         }
2027
2028         /* The i915 workqueue is primarily used for batched retirement of
2029          * requests (and thus managing bo) once the task has been completed
2030          * by the GPU. i915_gem_retire_requests() is called directly when we
2031          * need high-priority retirement, such as waiting for an explicit
2032          * bo.
2033          *
2034          * It is also used for periodic low-priority events, such as
2035          * idle-timers and recording error state.
2036          *
2037          * All tasks on the workqueue are expected to acquire the dev mutex
2038          * so there is no point in running more than one instance of the
2039          * workqueue at any time: max_active = 1 and NON_REENTRANT.
2040          */
2041         dev_priv->wq = alloc_workqueue("i915",
2042                                        WQ_UNBOUND | WQ_NON_REENTRANT,
2043                                        1);
2044         if (dev_priv->wq == NULL) {
2045                 DRM_ERROR("Failed to create our workqueue.\n");
2046                 ret = -ENOMEM;
2047                 goto out_mtrrfree;
2048         }
2049
2050         /* enable GEM by default */
2051         dev_priv->has_gem = 1;
2052
2053         intel_irq_init(dev);
2054
2055         /* Try to make sure MCHBAR is enabled before poking at it */
2056         intel_setup_mchbar(dev);
2057         intel_setup_gmbus(dev);
2058         intel_opregion_setup(dev);
2059
2060         /* Make sure the bios did its job and set up vital registers */
2061         intel_setup_bios(dev);
2062
2063         i915_gem_load(dev);
2064
2065         /* Init HWS */
2066         if (!I915_NEED_GFX_HWS(dev)) {
2067                 ret = i915_init_phys_hws(dev);
2068                 if (ret)
2069                         goto out_gem_unload;
2070         }
2071
2072         if (IS_PINEVIEW(dev))
2073                 i915_pineview_get_mem_freq(dev);
2074         else if (IS_GEN5(dev))
2075                 i915_ironlake_get_mem_freq(dev);
2076
2077         /* On the 945G/GM, the chipset reports the MSI capability on the
2078          * integrated graphics even though the support isn't actually there
2079          * according to the published specs.  It doesn't appear to function
2080          * correctly in testing on 945G.
2081          * This may be a side effect of MSI having been made available for PEG
2082          * and the registers being closely associated.
2083          *
2084          * According to chipset errata, on the 965GM, MSI interrupts may
2085          * be lost or delayed, but we use them anyways to avoid
2086          * stuck interrupts on some machines.
2087          */
2088         if (!IS_I945G(dev) && !IS_I945GM(dev))
2089                 pci_enable_msi(dev->pdev);
2090
2091         spin_lock_init(&dev_priv->gt_lock);
2092         spin_lock_init(&dev_priv->irq_lock);
2093         spin_lock_init(&dev_priv->error_lock);
2094         spin_lock_init(&dev_priv->rps_lock);
2095
2096         if (IS_IVYBRIDGE(dev))
2097                 dev_priv->num_pipe = 3;
2098         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
2099                 dev_priv->num_pipe = 2;
2100         else
2101                 dev_priv->num_pipe = 1;
2102
2103         ret = drm_vblank_init(dev, dev_priv->num_pipe);
2104         if (ret)
2105                 goto out_gem_unload;
2106
2107         /* Start out suspended */
2108         dev_priv->mm.suspended = 1;
2109
2110         intel_detect_pch(dev);
2111
2112         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2113                 ret = i915_load_modeset_init(dev);
2114                 if (ret < 0) {
2115                         DRM_ERROR("failed to init modeset\n");
2116                         goto out_gem_unload;
2117                 }
2118         }
2119
2120         /* Must be done after probing outputs */
2121         intel_opregion_init(dev);
2122         acpi_video_register();
2123
2124         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2125                     (unsigned long) dev);
2126
2127         if (IS_GEN5(dev)) {
2128                 spin_lock(&mchdev_lock);
2129                 i915_mch_dev = dev_priv;
2130                 dev_priv->mchdev_lock = &mchdev_lock;
2131                 spin_unlock(&mchdev_lock);
2132
2133                 ips_ping_for_i915_load();
2134         }
2135
2136         return 0;
2137
2138 out_gem_unload:
2139         if (dev_priv->mm.inactive_shrinker.shrink)
2140                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2141
2142         if (dev->pdev->msi_enabled)
2143                 pci_disable_msi(dev->pdev);
2144
2145         intel_teardown_gmbus(dev);
2146         intel_teardown_mchbar(dev);
2147         destroy_workqueue(dev_priv->wq);
2148 out_mtrrfree:
2149         if (dev_priv->mm.gtt_mtrr >= 0) {
2150                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2151                          dev->agp->agp_info.aper_size * 1024 * 1024);
2152                 dev_priv->mm.gtt_mtrr = -1;
2153         }
2154         io_mapping_free(dev_priv->mm.gtt_mapping);
2155 out_rmmap:
2156         pci_iounmap(dev->pdev, dev_priv->regs);
2157 put_bridge:
2158         pci_dev_put(dev_priv->bridge_dev);
2159 free_priv:
2160         kfree(dev_priv);
2161         return ret;
2162 }
2163
2164 int i915_driver_unload(struct drm_device *dev)
2165 {
2166         struct drm_i915_private *dev_priv = dev->dev_private;
2167         int ret;
2168
2169         spin_lock(&mchdev_lock);
2170         i915_mch_dev = NULL;
2171         spin_unlock(&mchdev_lock);
2172
2173         if (dev_priv->mm.inactive_shrinker.shrink)
2174                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2175
2176         mutex_lock(&dev->struct_mutex);
2177         ret = i915_gpu_idle(dev, true);
2178         if (ret)
2179                 DRM_ERROR("failed to idle hardware: %d\n", ret);
2180         mutex_unlock(&dev->struct_mutex);
2181
2182         /* Cancel the retire work handler, which should be idle now. */
2183         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2184
2185         io_mapping_free(dev_priv->mm.gtt_mapping);
2186         if (dev_priv->mm.gtt_mtrr >= 0) {
2187                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2188                          dev->agp->agp_info.aper_size * 1024 * 1024);
2189                 dev_priv->mm.gtt_mtrr = -1;
2190         }
2191
2192         acpi_video_unregister();
2193
2194         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2195                 intel_fbdev_fini(dev);
2196                 intel_modeset_cleanup(dev);
2197
2198                 /*
2199                  * free the memory space allocated for the child device
2200                  * config parsed from VBT
2201                  */
2202                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2203                         kfree(dev_priv->child_dev);
2204                         dev_priv->child_dev = NULL;
2205                         dev_priv->child_dev_num = 0;
2206                 }
2207
2208                 vga_switcheroo_unregister_client(dev->pdev);
2209                 vga_client_register(dev->pdev, NULL, NULL, NULL);
2210         }
2211
2212         /* Free error state after interrupts are fully disabled. */
2213         del_timer_sync(&dev_priv->hangcheck_timer);
2214         cancel_work_sync(&dev_priv->error_work);
2215         i915_destroy_error_state(dev);
2216
2217         if (dev->pdev->msi_enabled)
2218                 pci_disable_msi(dev->pdev);
2219
2220         intel_opregion_fini(dev);
2221
2222         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2223                 /* Flush any outstanding unpin_work. */
2224                 flush_workqueue(dev_priv->wq);
2225
2226                 mutex_lock(&dev->struct_mutex);
2227                 i915_gem_free_all_phys_object(dev);
2228                 i915_gem_cleanup_ringbuffer(dev);
2229                 mutex_unlock(&dev->struct_mutex);
2230                 i915_gem_cleanup_aliasing_ppgtt(dev);
2231                 if (I915_HAS_FBC(dev) && i915_powersave)
2232                         i915_cleanup_compression(dev);
2233                 drm_mm_takedown(&dev_priv->mm.stolen);
2234
2235                 intel_cleanup_overlay(dev);
2236
2237                 if (!I915_NEED_GFX_HWS(dev))
2238                         i915_free_hws(dev);
2239         }
2240
2241         if (dev_priv->regs != NULL)
2242                 pci_iounmap(dev->pdev, dev_priv->regs);
2243
2244         intel_teardown_gmbus(dev);
2245         intel_teardown_mchbar(dev);
2246
2247         destroy_workqueue(dev_priv->wq);
2248
2249         pci_dev_put(dev_priv->bridge_dev);
2250         kfree(dev->dev_private);
2251
2252         return 0;
2253 }
2254
2255 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2256 {
2257         struct drm_i915_file_private *file_priv;
2258
2259         DRM_DEBUG_DRIVER("\n");
2260         file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2261         if (!file_priv)
2262                 return -ENOMEM;
2263
2264         file->driver_priv = file_priv;
2265
2266         spin_lock_init(&file_priv->mm.lock);
2267         INIT_LIST_HEAD(&file_priv->mm.request_list);
2268
2269         return 0;
2270 }
2271
2272 /**
2273  * i915_driver_lastclose - clean up after all DRM clients have exited
2274  * @dev: DRM device
2275  *
2276  * Take care of cleaning up after all DRM clients have exited.  In the
2277  * mode setting case, we want to restore the kernel's initial mode (just
2278  * in case the last client left us in a bad state).
2279  *
2280  * Additionally, in the non-mode setting case, we'll tear down the AGP
2281  * and DMA structures, since the kernel won't be using them, and clea
2282  * up any GEM state.
2283  */
2284 void i915_driver_lastclose(struct drm_device * dev)
2285 {
2286         drm_i915_private_t *dev_priv = dev->dev_private;
2287
2288         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2289                 intel_fb_restore_mode(dev);
2290                 vga_switcheroo_process_delayed_switch();
2291                 return;
2292         }
2293
2294         i915_gem_lastclose(dev);
2295
2296         i915_dma_cleanup(dev);
2297 }
2298
2299 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2300 {
2301         i915_gem_release(dev, file_priv);
2302 }
2303
2304 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2305 {
2306         struct drm_i915_file_private *file_priv = file->driver_priv;
2307
2308         kfree(file_priv);
2309 }
2310
2311 struct drm_ioctl_desc i915_ioctls[] = {
2312         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2313         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2314         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2315         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2316         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2317         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2318         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2319         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2320         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2321         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2322         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2323         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2324         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2325         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2326         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
2327         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2328         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2329         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2330         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2331         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2332         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2333         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2334         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2335         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2336         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2337         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2338         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2339         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2340         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2341         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2342         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2343         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2344         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2345         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2346         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2347         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2348         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2349         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2350         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2351         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2352         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2353         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2354 };
2355
2356 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2357
2358 /**
2359  * Determine if the device really is AGP or not.
2360  *
2361  * All Intel graphics chipsets are treated as AGP, even if they are really
2362  * PCI-e.
2363  *
2364  * \param dev   The device to be tested.
2365  *
2366  * \returns
2367  * A value of 1 is always retured to indictate every i9x5 is AGP.
2368  */
2369 int i915_driver_device_is_agp(struct drm_device * dev)
2370 {
2371         return 1;
2372 }