2 * PCI Backend - Handles the virtual fields in the configuration space headers.
4 * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
7 #include <linux/kernel.h>
10 #include "conf_space.h"
18 #define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO))
19 #define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER)
21 static int command_read(struct pci_dev *dev, int offset, u16 *value, void *data)
26 ret = xen_pcibk_read_config_word(dev, offset, value, data);
27 if (!pci_is_enabled(dev))
30 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
31 if (dev->resource[i].flags & IORESOURCE_IO)
32 *value |= PCI_COMMAND_IO;
33 if (dev->resource[i].flags & IORESOURCE_MEM)
34 *value |= PCI_COMMAND_MEMORY;
40 static int command_write(struct pci_dev *dev, int offset, u16 value, void *data)
43 struct xen_pcibk_dev_data *dev_data = dev_data = pci_get_drvdata(dev);
47 if (!pci_is_enabled(dev) && is_enable_cmd(value)) {
48 if (unlikely(verbose_request))
49 printk(KERN_DEBUG DRV_NAME ": %s: enable\n",
51 err = pci_enable_device(dev);
56 dev_data->enable_intx = 1;
58 } else if (pci_is_enabled(dev) && !is_enable_cmd(value)) {
59 if (unlikely(verbose_request))
60 printk(KERN_DEBUG DRV_NAME ": %s: disable\n",
62 pci_disable_device(dev);
65 dev_data->enable_intx = 0;
69 if (!dev->is_busmaster && is_master_cmd(value)) {
70 if (unlikely(verbose_request))
71 printk(KERN_DEBUG DRV_NAME ": %s: set bus master\n",
76 if (value & PCI_COMMAND_INVALIDATE) {
77 if (unlikely(verbose_request))
79 DRV_NAME ": %s: enable memory-write-invalidate\n",
81 err = pci_set_mwi(dev);
84 DRV_NAME ": %s: cannot enable "
85 "memory-write-invalidate (%d)\n",
87 value &= ~PCI_COMMAND_INVALIDATE;
91 return pci_write_config_word(dev, offset, value);
94 static int rom_write(struct pci_dev *dev, int offset, u32 value, void *data)
96 struct pci_bar_info *bar = data;
99 printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
101 return XEN_PCI_ERR_op_failed;
104 /* A write to obtain the length must happen as a 32-bit write.
105 * This does not (yet) support writing individual bytes
107 if (value == ~PCI_ROM_ADDRESS_ENABLE)
111 pci_read_config_dword(dev, offset, &tmpval);
112 if (tmpval != bar->val && value == bar->val) {
113 /* Allow restoration of bar value. */
114 pci_write_config_dword(dev, offset, bar->val);
119 /* Do we need to support enabling/disabling the rom address here? */
124 /* For the BARs, only allow writes which write ~0 or
125 * the correct resource information
126 * (Needed for when the driver probes the resource usage)
128 static int bar_write(struct pci_dev *dev, int offset, u32 value, void *data)
130 struct pci_bar_info *bar = data;
132 if (unlikely(!bar)) {
133 printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
135 return XEN_PCI_ERR_op_failed;
138 /* A write to obtain the length must happen as a 32-bit write.
139 * This does not (yet) support writing individual bytes
145 pci_read_config_dword(dev, offset, &tmpval);
146 if (tmpval != bar->val && value == bar->val) {
147 /* Allow restoration of bar value. */
148 pci_write_config_dword(dev, offset, bar->val);
156 static int bar_read(struct pci_dev *dev, int offset, u32 * value, void *data)
158 struct pci_bar_info *bar = data;
160 if (unlikely(!bar)) {
161 printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
163 return XEN_PCI_ERR_op_failed;
166 *value = bar->which ? bar->len_val : bar->val;
171 static inline void read_dev_bar(struct pci_dev *dev,
172 struct pci_bar_info *bar_info, int offset,
176 struct resource *res = dev->resource;
178 if (offset == PCI_ROM_ADDRESS || offset == PCI_ROM_ADDRESS1)
179 pos = PCI_ROM_RESOURCE;
181 pos = (offset - PCI_BASE_ADDRESS_0) / 4;
182 if (pos && ((res[pos - 1].flags & (PCI_BASE_ADDRESS_SPACE |
183 PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
184 (PCI_BASE_ADDRESS_SPACE_MEMORY |
185 PCI_BASE_ADDRESS_MEM_TYPE_64))) {
186 bar_info->val = res[pos - 1].start >> 32;
187 bar_info->len_val = res[pos - 1].end >> 32;
192 bar_info->val = res[pos].start |
193 (res[pos].flags & PCI_REGION_FLAG_MASK);
194 bar_info->len_val = resource_size(&res[pos]);
197 static void *bar_init(struct pci_dev *dev, int offset)
199 struct pci_bar_info *bar = kmalloc(sizeof(*bar), GFP_KERNEL);
202 return ERR_PTR(-ENOMEM);
204 read_dev_bar(dev, bar, offset, ~0);
210 static void *rom_init(struct pci_dev *dev, int offset)
212 struct pci_bar_info *bar = kmalloc(sizeof(*bar), GFP_KERNEL);
215 return ERR_PTR(-ENOMEM);
217 read_dev_bar(dev, bar, offset, ~PCI_ROM_ADDRESS_ENABLE);
223 static void bar_reset(struct pci_dev *dev, int offset, void *data)
225 struct pci_bar_info *bar = data;
230 static void bar_release(struct pci_dev *dev, int offset, void *data)
235 static int xen_pcibk_read_vendor(struct pci_dev *dev, int offset,
236 u16 *value, void *data)
238 *value = dev->vendor;
243 static int xen_pcibk_read_device(struct pci_dev *dev, int offset,
244 u16 *value, void *data)
246 *value = dev->device;
251 static int interrupt_read(struct pci_dev *dev, int offset, u8 * value,
254 *value = (u8) dev->irq;
259 static int bist_write(struct pci_dev *dev, int offset, u8 value, void *data)
264 err = pci_read_config_byte(dev, offset, &cur_value);
268 if ((cur_value & ~PCI_BIST_START) == (value & ~PCI_BIST_START)
269 || value == PCI_BIST_START)
270 err = pci_write_config_byte(dev, offset, value);
276 static const struct config_field header_common[] = {
278 .offset = PCI_VENDOR_ID,
280 .u.w.read = xen_pcibk_read_vendor,
283 .offset = PCI_DEVICE_ID,
285 .u.w.read = xen_pcibk_read_device,
288 .offset = PCI_COMMAND,
290 .u.w.read = command_read,
291 .u.w.write = command_write,
294 .offset = PCI_INTERRUPT_LINE,
296 .u.b.read = interrupt_read,
299 .offset = PCI_INTERRUPT_PIN,
301 .u.b.read = xen_pcibk_read_config_byte,
304 /* Any side effects of letting driver domain control cache line? */
305 .offset = PCI_CACHE_LINE_SIZE,
307 .u.b.read = xen_pcibk_read_config_byte,
308 .u.b.write = xen_pcibk_write_config_byte,
311 .offset = PCI_LATENCY_TIMER,
313 .u.b.read = xen_pcibk_read_config_byte,
318 .u.b.read = xen_pcibk_read_config_byte,
319 .u.b.write = bist_write,
324 #define CFG_FIELD_BAR(reg_offset) \
326 .offset = reg_offset, \
329 .reset = bar_reset, \
330 .release = bar_release, \
331 .u.dw.read = bar_read, \
332 .u.dw.write = bar_write, \
335 #define CFG_FIELD_ROM(reg_offset) \
337 .offset = reg_offset, \
340 .reset = bar_reset, \
341 .release = bar_release, \
342 .u.dw.read = bar_read, \
343 .u.dw.write = rom_write, \
346 static const struct config_field header_0[] = {
347 CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
348 CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
349 CFG_FIELD_BAR(PCI_BASE_ADDRESS_2),
350 CFG_FIELD_BAR(PCI_BASE_ADDRESS_3),
351 CFG_FIELD_BAR(PCI_BASE_ADDRESS_4),
352 CFG_FIELD_BAR(PCI_BASE_ADDRESS_5),
353 CFG_FIELD_ROM(PCI_ROM_ADDRESS),
357 static const struct config_field header_1[] = {
358 CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
359 CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
360 CFG_FIELD_ROM(PCI_ROM_ADDRESS1),
364 int xen_pcibk_config_header_add_fields(struct pci_dev *dev)
368 err = xen_pcibk_config_add_fields(dev, header_common);
372 switch (dev->hdr_type) {
373 case PCI_HEADER_TYPE_NORMAL:
374 err = xen_pcibk_config_add_fields(dev, header_0);
377 case PCI_HEADER_TYPE_BRIDGE:
378 err = xen_pcibk_config_add_fields(dev, header_1);
383 printk(KERN_ERR DRV_NAME ": %s: Unsupported header type %d!\n",
384 pci_name(dev), dev->hdr_type);