2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
4 * Copyright (C) 2011 Don Zickus Red Hat, Inc.
6 * Pentium III FXSR, SSE support
7 * Gareth Hughes <gareth@valinux.com>, May 2000
11 * Handle hardware traps and faults.
13 #include <linux/spinlock.h>
14 #include <linux/kprobes.h>
15 #include <linux/kdebug.h>
16 #include <linux/nmi.h>
17 #include <linux/delay.h>
18 #include <linux/hardirq.h>
19 #include <linux/slab.h>
20 #include <linux/export.h>
22 #include <linux/mca.h>
24 #if defined(CONFIG_EDAC)
25 #include <linux/edac.h>
28 #include <linux/atomic.h>
29 #include <asm/traps.h>
30 #include <asm/mach_traps.h>
32 #include <asm/x86_init.h>
34 #define NMI_MAX_NAMELEN 16
36 struct list_head list;
37 nmi_handler_t handler;
44 struct list_head head;
47 static struct nmi_desc nmi_desc[NMI_MAX] =
50 .lock = __SPIN_LOCK_UNLOCKED(&nmi_desc[0].lock),
51 .head = LIST_HEAD_INIT(nmi_desc[0].head),
54 .lock = __SPIN_LOCK_UNLOCKED(&nmi_desc[1].lock),
55 .head = LIST_HEAD_INIT(nmi_desc[1].head),
63 unsigned int external;
67 static DEFINE_PER_CPU(struct nmi_stats, nmi_stats);
69 static int ignore_nmis;
71 int unknown_nmi_panic;
73 * Prevent NMI reason port (0x61) being accessed simultaneously, can
74 * only be used in NMI handler.
76 static DEFINE_RAW_SPINLOCK(nmi_reason_lock);
78 static int __init setup_unknown_nmi_panic(char *str)
80 unknown_nmi_panic = 1;
83 __setup("unknown_nmi_panic", setup_unknown_nmi_panic);
85 #define nmi_to_desc(type) (&nmi_desc[type])
87 static int notrace __kprobes nmi_handle(unsigned int type, struct pt_regs *regs, bool b2b)
89 struct nmi_desc *desc = nmi_to_desc(type);
96 * NMIs are edge-triggered, which means if you have enough
97 * of them concurrently, you can lose some because only one
98 * can be latched at any given time. Walk the whole list
99 * to handle those situations.
101 list_for_each_entry_rcu(a, &desc->head, list)
102 handled += a->handler(type, regs);
106 /* return total number of NMI events handled */
110 static int __setup_nmi(unsigned int type, struct nmiaction *action)
112 struct nmi_desc *desc = nmi_to_desc(type);
115 spin_lock_irqsave(&desc->lock, flags);
118 * most handlers of type NMI_UNKNOWN never return because
119 * they just assume the NMI is theirs. Just a sanity check
120 * to manage expectations
122 WARN_ON_ONCE(type == NMI_UNKNOWN && !list_empty(&desc->head));
125 * some handlers need to be executed first otherwise a fake
126 * event confuses some handlers (kdump uses this flag)
128 if (action->flags & NMI_FLAG_FIRST)
129 list_add_rcu(&action->list, &desc->head);
131 list_add_tail_rcu(&action->list, &desc->head);
133 spin_unlock_irqrestore(&desc->lock, flags);
137 static struct nmiaction *__free_nmi(unsigned int type, const char *name)
139 struct nmi_desc *desc = nmi_to_desc(type);
143 spin_lock_irqsave(&desc->lock, flags);
145 list_for_each_entry_rcu(n, &desc->head, list) {
147 * the name passed in to describe the nmi handler
148 * is used as the lookup key
150 if (!strcmp(n->name, name)) {
152 "Trying to free NMI (%s) from NMI context!\n", n->name);
153 list_del_rcu(&n->list);
158 spin_unlock_irqrestore(&desc->lock, flags);
163 int register_nmi_handler(unsigned int type, nmi_handler_t handler,
164 unsigned long nmiflags, const char *devname)
166 struct nmiaction *action;
167 int retval = -ENOMEM;
172 action = kzalloc(sizeof(struct nmiaction), GFP_KERNEL);
176 action->handler = handler;
177 action->flags = nmiflags;
178 action->name = kstrndup(devname, NMI_MAX_NAMELEN, GFP_KERNEL);
180 goto fail_action_name;
182 retval = __setup_nmi(type, action);
197 EXPORT_SYMBOL_GPL(register_nmi_handler);
199 void unregister_nmi_handler(unsigned int type, const char *name)
203 a = __free_nmi(type, name);
210 EXPORT_SYMBOL_GPL(unregister_nmi_handler);
212 static notrace __kprobes void
213 pci_serr_error(unsigned char reason, struct pt_regs *regs)
215 pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n",
216 reason, smp_processor_id());
219 * On some machines, PCI SERR line is used to report memory
220 * errors. EDAC makes use of it.
222 #if defined(CONFIG_EDAC)
223 if (edac_handler_set()) {
224 edac_atomic_assert_error();
229 if (panic_on_unrecovered_nmi)
230 panic("NMI: Not continuing");
232 pr_emerg("Dazed and confused, but trying to continue\n");
234 /* Clear and disable the PCI SERR error line. */
235 clear_serr_error(reason);
238 static notrace __kprobes void
239 io_check_error(unsigned char reason, struct pt_regs *regs)
242 "NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n",
243 reason, smp_processor_id());
244 show_registers(regs);
247 panic("NMI IOCK error: Not continuing");
249 /* Re-enable the IOCK line, wait for a few seconds */
250 clear_io_check_error(reason);
253 static notrace __kprobes void
254 unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
259 * Use 'false' as back-to-back NMIs are dealt with one level up.
260 * Of course this makes having multiple 'unknown' handlers useless
261 * as only the first one is ever run (unless it can actually determine
262 * if it caused the NMI)
264 handled = nmi_handle(NMI_UNKNOWN, regs, false);
266 __this_cpu_add(nmi_stats.unknown, handled);
270 __this_cpu_add(nmi_stats.unknown, 1);
274 * Might actually be able to figure out what the guilty party
282 pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
283 reason, smp_processor_id());
285 pr_emerg("Do you have a strange power saving mode enabled?\n");
286 if (unknown_nmi_panic || panic_on_unrecovered_nmi)
287 panic("NMI: Not continuing");
289 pr_emerg("Dazed and confused, but trying to continue\n");
292 static DEFINE_PER_CPU(bool, swallow_nmi);
293 static DEFINE_PER_CPU(unsigned long, last_nmi_rip);
295 static notrace __kprobes void default_do_nmi(struct pt_regs *regs)
297 unsigned char reason = 0;
302 * CPU-specific NMI must be processed before non-CPU-specific
303 * NMI, otherwise we may lose it, because the CPU-specific
304 * NMI can not be detected/processed on other CPUs.
308 * Back-to-back NMIs are interesting because they can either
309 * be two NMI or more than two NMIs (any thing over two is dropped
310 * due to NMI being edge-triggered). If this is the second half
311 * of the back-to-back NMI, assume we dropped things and process
312 * more handlers. Otherwise reset the 'swallow' NMI behaviour
314 if (regs->ip == __this_cpu_read(last_nmi_rip))
317 __this_cpu_write(swallow_nmi, false);
319 __this_cpu_write(last_nmi_rip, regs->ip);
321 handled = nmi_handle(NMI_LOCAL, regs, b2b);
322 __this_cpu_add(nmi_stats.normal, handled);
325 * There are cases when a NMI handler handles multiple
326 * events in the current NMI. One of these events may
327 * be queued for in the next NMI. Because the event is
328 * already handled, the next NMI will result in an unknown
329 * NMI. Instead lets flag this for a potential NMI to
333 __this_cpu_write(swallow_nmi, true);
337 /* Non-CPU-specific NMI: NMI sources can be processed on any CPU */
338 raw_spin_lock(&nmi_reason_lock);
339 reason = x86_platform.get_nmi_reason();
341 if (reason & NMI_REASON_MASK) {
342 if (reason & NMI_REASON_SERR)
343 pci_serr_error(reason, regs);
344 else if (reason & NMI_REASON_IOCHK)
345 io_check_error(reason, regs);
348 * Reassert NMI in case it became active
349 * meanwhile as it's edge-triggered:
353 __this_cpu_add(nmi_stats.external, 1);
354 raw_spin_unlock(&nmi_reason_lock);
357 raw_spin_unlock(&nmi_reason_lock);
360 * Only one NMI can be latched at a time. To handle
361 * this we may process multiple nmi handlers at once to
362 * cover the case where an NMI is dropped. The downside
363 * to this approach is we may process an NMI prematurely,
364 * while its real NMI is sitting latched. This will cause
365 * an unknown NMI on the next run of the NMI processing.
367 * We tried to flag that condition above, by setting the
368 * swallow_nmi flag when we process more than one event.
369 * This condition is also only present on the second half
370 * of a back-to-back NMI, so we flag that condition too.
372 * If both are true, we assume we already processed this
373 * NMI previously and we swallow it. Otherwise we reset
376 * There are scenarios where we may accidentally swallow
377 * a 'real' unknown NMI. For example, while processing
378 * a perf NMI another perf NMI comes in along with a
379 * 'real' unknown NMI. These two NMIs get combined into
380 * one (as descibed above). When the next NMI gets
381 * processed, it will be flagged by perf as handled, but
382 * noone will know that there was a 'real' unknown NMI sent
383 * also. As a result it gets swallowed. Or if the first
384 * perf NMI returns two events handled then the second
385 * NMI will get eaten by the logic below, again losing a
386 * 'real' unknown NMI. But this is the best we can do
389 if (b2b && __this_cpu_read(swallow_nmi))
390 __this_cpu_add(nmi_stats.swallow, 1);
392 unknown_nmi_error(reason, regs);
396 * NMIs can hit breakpoints which will cause it to lose its
397 * NMI context with the CPU when the breakpoint does an iret.
401 * For i386, NMIs use the same stack as the kernel, and we can
402 * add a workaround to the iret problem in C. Simply have 3 states
409 * When no NMI is in progress, it is in the "not running" state.
410 * When an NMI comes in, it goes into the "executing" state.
411 * Normally, if another NMI is triggered, it does not interrupt
412 * the running NMI and the HW will simply latch it so that when
413 * the first NMI finishes, it will restart the second NMI.
414 * (Note, the latch is binary, thus multiple NMIs triggering,
415 * when one is running, are ignored. Only one NMI is restarted.)
417 * If an NMI hits a breakpoint that executes an iret, another
418 * NMI can preempt it. We do not want to allow this new NMI
419 * to run, but we want to execute it when the first one finishes.
420 * We set the state to "latched", and the first NMI will perform
421 * an cmpxchg on the state, and if it doesn't successfully
422 * reset the state to "not running" it will restart the next
430 static DEFINE_PER_CPU(enum nmi_states, nmi_state);
432 #define nmi_nesting_preprocess(regs) \
434 if (__get_cpu_var(nmi_state) != NMI_NOT_RUNNING) { \
435 __get_cpu_var(nmi_state) = NMI_LATCHED; \
439 __get_cpu_var(nmi_state) = NMI_EXECUTING; \
442 #define nmi_nesting_postprocess() \
444 if (cmpxchg(&__get_cpu_var(nmi_state), \
445 NMI_EXECUTING, NMI_NOT_RUNNING) != NMI_EXECUTING) \
450 * In x86_64 things are a bit more difficult. This has the same problem
451 * where an NMI hitting a breakpoint that calls iret will remove the
452 * NMI context, allowing a nested NMI to enter. What makes this more
453 * difficult is that both NMIs and breakpoints have their own stack.
454 * When a new NMI or breakpoint is executed, the stack is set to a fixed
455 * point. If an NMI is nested, it will have its stack set at that same
456 * fixed address that the first NMI had, and will start corrupting the
457 * stack. This is handled in entry_64.S, but the same problem exists with
458 * the breakpoint stack.
460 * If a breakpoint is being processed, and the debug stack is being used,
461 * if an NMI comes in and also hits a breakpoint, the stack pointer
462 * will be set to the same fixed address as the breakpoint that was
463 * interrupted, causing that stack to be corrupted. To handle this case,
464 * check if the stack that was interrupted is the debug stack, and if
465 * so, change the IDT so that new breakpoints will use the current stack
466 * and not switch to the fixed address. On return of the NMI, switch back
467 * to the original IDT.
469 static DEFINE_PER_CPU(int, update_debug_stack);
471 static inline void nmi_nesting_preprocess(struct pt_regs *regs)
474 * If we interrupted a breakpoint, it is possible that
475 * the nmi handler will have breakpoints too. We need to
476 * change the IDT such that breakpoints that happen here
477 * continue to use the NMI stack.
479 if (unlikely(is_debug_stack(regs->sp))) {
480 debug_stack_set_zero();
481 __get_cpu_var(update_debug_stack) = 1;
485 static inline void nmi_nesting_postprocess(void)
487 if (unlikely(__get_cpu_var(update_debug_stack)))
492 dotraplinkage notrace __kprobes void
493 do_nmi(struct pt_regs *regs, long error_code)
495 nmi_nesting_preprocess(regs);
499 inc_irq_stat(__nmi_count);
502 default_do_nmi(regs);
506 /* On i386, may loop back to preprocess */
507 nmi_nesting_postprocess();
515 void restart_nmi(void)
520 /* reset the back-to-back NMI logic */
521 void local_touch_nmi(void)
523 __this_cpu_write(last_nmi_rip, 0);